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1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <[email protected]>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
18#include <sys/utsname.h>
19
20#include <linux/kvm.h>
21#include <linux/kvm_para.h>
22
23#include "qemu-common.h"
24#include "sysemu.h"
25#include "kvm.h"
26#include "kvm_i386.h"
27#include "cpu.h"
28#include "gdbstub.h"
29#include "host-utils.h"
30#include "hw/pc.h"
31#include "hw/apic.h"
32#include "ioport.h"
33#include "hyperv.h"
34#include "hw/pci/pci.h"
35
36//#define DEBUG_KVM
37
38#ifdef DEBUG_KVM
39#define DPRINTF(fmt, ...) \
40 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
41#else
42#define DPRINTF(fmt, ...) \
43 do { } while (0)
44#endif
45
46#define MSR_KVM_WALL_CLOCK 0x11
47#define MSR_KVM_SYSTEM_TIME 0x12
48
49#ifndef BUS_MCEERR_AR
50#define BUS_MCEERR_AR 4
51#endif
52#ifndef BUS_MCEERR_AO
53#define BUS_MCEERR_AO 5
54#endif
55
56const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
57 KVM_CAP_INFO(SET_TSS_ADDR),
58 KVM_CAP_INFO(EXT_CPUID),
59 KVM_CAP_INFO(MP_STATE),
60 KVM_CAP_LAST_INFO
61};
62
63static bool has_msr_star;
64static bool has_msr_hsave_pa;
65static bool has_msr_tsc_deadline;
66static bool has_msr_async_pf_en;
67static bool has_msr_pv_eoi_en;
68static bool has_msr_misc_enable;
69static int lm_capable_kernel;
70
71bool kvm_allows_irq0_override(void)
72{
73 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
74}
75
76static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
77{
78 struct kvm_cpuid2 *cpuid;
79 int r, size;
80
81 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
82 cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
83 cpuid->nent = max;
84 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
85 if (r == 0 && cpuid->nent >= max) {
86 r = -E2BIG;
87 }
88 if (r < 0) {
89 if (r == -E2BIG) {
90 g_free(cpuid);
91 return NULL;
92 } else {
93 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
94 strerror(-r));
95 exit(1);
96 }
97 }
98 return cpuid;
99}
100
101/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
102 * for all entries.
103 */
104static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
105{
106 struct kvm_cpuid2 *cpuid;
107 int max = 1;
108 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
109 max *= 2;
110 }
111 return cpuid;
112}
113
114struct kvm_para_features {
115 int cap;
116 int feature;
117} para_features[] = {
118 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
119 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
120 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
121 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
122 { -1, -1 }
123};
124
125static int get_para_features(KVMState *s)
126{
127 int i, features = 0;
128
129 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
130 if (kvm_check_extension(s, para_features[i].cap)) {
131 features |= (1 << para_features[i].feature);
132 }
133 }
134
135 return features;
136}
137
138
139/* Returns the value for a specific register on the cpuid entry
140 */
141static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
142{
143 uint32_t ret = 0;
144 switch (reg) {
145 case R_EAX:
146 ret = entry->eax;
147 break;
148 case R_EBX:
149 ret = entry->ebx;
150 break;
151 case R_ECX:
152 ret = entry->ecx;
153 break;
154 case R_EDX:
155 ret = entry->edx;
156 break;
157 }
158 return ret;
159}
160
161/* Find matching entry for function/index on kvm_cpuid2 struct
162 */
163static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
164 uint32_t function,
165 uint32_t index)
166{
167 int i;
168 for (i = 0; i < cpuid->nent; ++i) {
169 if (cpuid->entries[i].function == function &&
170 cpuid->entries[i].index == index) {
171 return &cpuid->entries[i];
172 }
173 }
174 /* not found: */
175 return NULL;
176}
177
178uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
179 uint32_t index, int reg)
180{
181 struct kvm_cpuid2 *cpuid;
182 uint32_t ret = 0;
183 uint32_t cpuid_1_edx;
184 bool found = false;
185
186 cpuid = get_supported_cpuid(s);
187
188 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
189 if (entry) {
190 found = true;
191 ret = cpuid_entry_get_reg(entry, reg);
192 }
193
194 /* Fixups for the data returned by KVM, below */
195
196 if (function == 1 && reg == R_EDX) {
197 /* KVM before 2.6.30 misreports the following features */
198 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
199 } else if (function == 1 && reg == R_ECX) {
200 /* We can set the hypervisor flag, even if KVM does not return it on
201 * GET_SUPPORTED_CPUID
202 */
203 ret |= CPUID_EXT_HYPERVISOR;
204 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
205 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
206 * and the irqchip is in the kernel.
207 */
208 if (kvm_irqchip_in_kernel() &&
209 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
210 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
211 }
212
213 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
214 * without the in-kernel irqchip
215 */
216 if (!kvm_irqchip_in_kernel()) {
217 ret &= ~CPUID_EXT_X2APIC;
218 }
219 } else if (function == 0x80000001 && reg == R_EDX) {
220 /* On Intel, kvm returns cpuid according to the Intel spec,
221 * so add missing bits according to the AMD spec:
222 */
223 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
224 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
225 }
226
227 g_free(cpuid);
228
229 /* fallback for older kernels */
230 if ((function == KVM_CPUID_FEATURES) && !found) {
231 ret = get_para_features(s);
232 }
233
234 return ret;
235}
236
237typedef struct HWPoisonPage {
238 ram_addr_t ram_addr;
239 QLIST_ENTRY(HWPoisonPage) list;
240} HWPoisonPage;
241
242static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
243 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
244
245static void kvm_unpoison_all(void *param)
246{
247 HWPoisonPage *page, *next_page;
248
249 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
250 QLIST_REMOVE(page, list);
251 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
252 g_free(page);
253 }
254}
255
256static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
257{
258 HWPoisonPage *page;
259
260 QLIST_FOREACH(page, &hwpoison_page_list, list) {
261 if (page->ram_addr == ram_addr) {
262 return;
263 }
264 }
265 page = g_malloc(sizeof(HWPoisonPage));
266 page->ram_addr = ram_addr;
267 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
268}
269
270static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
271 int *max_banks)
272{
273 int r;
274
275 r = kvm_check_extension(s, KVM_CAP_MCE);
276 if (r > 0) {
277 *max_banks = r;
278 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
279 }
280 return -ENOSYS;
281}
282
283static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
284{
285 CPUX86State *env = &cpu->env;
286 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
287 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
288 uint64_t mcg_status = MCG_STATUS_MCIP;
289
290 if (code == BUS_MCEERR_AR) {
291 status |= MCI_STATUS_AR | 0x134;
292 mcg_status |= MCG_STATUS_EIPV;
293 } else {
294 status |= 0xc0;
295 mcg_status |= MCG_STATUS_RIPV;
296 }
297 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
298 (MCM_ADDR_PHYS << 6) | 0xc,
299 cpu_x86_support_mca_broadcast(env) ?
300 MCE_INJECT_BROADCAST : 0);
301}
302
303static void hardware_memory_error(void)
304{
305 fprintf(stderr, "Hardware memory error!\n");
306 exit(1);
307}
308
309int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
310{
311 X86CPU *cpu = x86_env_get_cpu(env);
312 ram_addr_t ram_addr;
313 hwaddr paddr;
314
315 if ((env->mcg_cap & MCG_SER_P) && addr
316 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
317 if (qemu_ram_addr_from_host(addr, &ram_addr) ||
318 !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) {
319 fprintf(stderr, "Hardware memory error for memory used by "
320 "QEMU itself instead of guest system!\n");
321 /* Hope we are lucky for AO MCE */
322 if (code == BUS_MCEERR_AO) {
323 return 0;
324 } else {
325 hardware_memory_error();
326 }
327 }
328 kvm_hwpoison_page_add(ram_addr);
329 kvm_mce_inject(cpu, paddr, code);
330 } else {
331 if (code == BUS_MCEERR_AO) {
332 return 0;
333 } else if (code == BUS_MCEERR_AR) {
334 hardware_memory_error();
335 } else {
336 return 1;
337 }
338 }
339 return 0;
340}
341
342int kvm_arch_on_sigbus(int code, void *addr)
343{
344 if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
345 ram_addr_t ram_addr;
346 hwaddr paddr;
347
348 /* Hope we are lucky for AO MCE */
349 if (qemu_ram_addr_from_host(addr, &ram_addr) ||
350 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr,
351 &paddr)) {
352 fprintf(stderr, "Hardware memory error for memory used by "
353 "QEMU itself instead of guest system!: %p\n", addr);
354 return 0;
355 }
356 kvm_hwpoison_page_add(ram_addr);
357 kvm_mce_inject(x86_env_get_cpu(first_cpu), paddr, code);
358 } else {
359 if (code == BUS_MCEERR_AO) {
360 return 0;
361 } else if (code == BUS_MCEERR_AR) {
362 hardware_memory_error();
363 } else {
364 return 1;
365 }
366 }
367 return 0;
368}
369
370static int kvm_inject_mce_oldstyle(CPUX86State *env)
371{
372 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
373 unsigned int bank, bank_num = env->mcg_cap & 0xff;
374 struct kvm_x86_mce mce;
375
376 env->exception_injected = -1;
377
378 /*
379 * There must be at least one bank in use if an MCE is pending.
380 * Find it and use its values for the event injection.
381 */
382 for (bank = 0; bank < bank_num; bank++) {
383 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
384 break;
385 }
386 }
387 assert(bank < bank_num);
388
389 mce.bank = bank;
390 mce.status = env->mce_banks[bank * 4 + 1];
391 mce.mcg_status = env->mcg_status;
392 mce.addr = env->mce_banks[bank * 4 + 2];
393 mce.misc = env->mce_banks[bank * 4 + 3];
394
395 return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
396 }
397 return 0;
398}
399
400static void cpu_update_state(void *opaque, int running, RunState state)
401{
402 CPUX86State *env = opaque;
403
404 if (running) {
405 env->tsc_valid = false;
406 }
407}
408
409int kvm_arch_init_vcpu(CPUX86State *env)
410{
411 struct {
412 struct kvm_cpuid2 cpuid;
413 struct kvm_cpuid_entry2 entries[100];
414 } QEMU_PACKED cpuid_data;
415 uint32_t limit, i, j, cpuid_i;
416 uint32_t unused;
417 struct kvm_cpuid_entry2 *c;
418 uint32_t signature[3];
419 int r;
420
421 cpuid_i = 0;
422
423 /* Paravirtualization CPUIDs */
424 c = &cpuid_data.entries[cpuid_i++];
425 memset(c, 0, sizeof(*c));
426 c->function = KVM_CPUID_SIGNATURE;
427 if (!hyperv_enabled()) {
428 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
429 c->eax = 0;
430 } else {
431 memcpy(signature, "Microsoft Hv", 12);
432 c->eax = HYPERV_CPUID_MIN;
433 }
434 c->ebx = signature[0];
435 c->ecx = signature[1];
436 c->edx = signature[2];
437
438 c = &cpuid_data.entries[cpuid_i++];
439 memset(c, 0, sizeof(*c));
440 c->function = KVM_CPUID_FEATURES;
441 c->eax = env->cpuid_kvm_features;
442
443 if (hyperv_enabled()) {
444 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
445 c->eax = signature[0];
446
447 c = &cpuid_data.entries[cpuid_i++];
448 memset(c, 0, sizeof(*c));
449 c->function = HYPERV_CPUID_VERSION;
450 c->eax = 0x00001bbc;
451 c->ebx = 0x00060001;
452
453 c = &cpuid_data.entries[cpuid_i++];
454 memset(c, 0, sizeof(*c));
455 c->function = HYPERV_CPUID_FEATURES;
456 if (hyperv_relaxed_timing_enabled()) {
457 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
458 }
459 if (hyperv_vapic_recommended()) {
460 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
461 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
462 }
463
464 c = &cpuid_data.entries[cpuid_i++];
465 memset(c, 0, sizeof(*c));
466 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
467 if (hyperv_relaxed_timing_enabled()) {
468 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
469 }
470 if (hyperv_vapic_recommended()) {
471 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
472 }
473 c->ebx = hyperv_get_spinlock_retries();
474
475 c = &cpuid_data.entries[cpuid_i++];
476 memset(c, 0, sizeof(*c));
477 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
478 c->eax = 0x40;
479 c->ebx = 0x40;
480
481 c = &cpuid_data.entries[cpuid_i++];
482 memset(c, 0, sizeof(*c));
483 c->function = KVM_CPUID_SIGNATURE_NEXT;
484 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
485 c->eax = 0;
486 c->ebx = signature[0];
487 c->ecx = signature[1];
488 c->edx = signature[2];
489 }
490
491 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
492
493 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
494
495 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
496
497 for (i = 0; i <= limit; i++) {
498 c = &cpuid_data.entries[cpuid_i++];
499
500 switch (i) {
501 case 2: {
502 /* Keep reading function 2 till all the input is received */
503 int times;
504
505 c->function = i;
506 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
507 KVM_CPUID_FLAG_STATE_READ_NEXT;
508 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
509 times = c->eax & 0xff;
510
511 for (j = 1; j < times; ++j) {
512 c = &cpuid_data.entries[cpuid_i++];
513 c->function = i;
514 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
515 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
516 }
517 break;
518 }
519 case 4:
520 case 0xb:
521 case 0xd:
522 for (j = 0; ; j++) {
523 if (i == 0xd && j == 64) {
524 break;
525 }
526 c->function = i;
527 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
528 c->index = j;
529 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
530
531 if (i == 4 && c->eax == 0) {
532 break;
533 }
534 if (i == 0xb && !(c->ecx & 0xff00)) {
535 break;
536 }
537 if (i == 0xd && c->eax == 0) {
538 continue;
539 }
540 c = &cpuid_data.entries[cpuid_i++];
541 }
542 break;
543 default:
544 c->function = i;
545 c->flags = 0;
546 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
547 break;
548 }
549 }
550 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
551
552 for (i = 0x80000000; i <= limit; i++) {
553 c = &cpuid_data.entries[cpuid_i++];
554
555 c->function = i;
556 c->flags = 0;
557 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
558 }
559
560 /* Call Centaur's CPUID instructions they are supported. */
561 if (env->cpuid_xlevel2 > 0) {
562 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
563
564 for (i = 0xC0000000; i <= limit; i++) {
565 c = &cpuid_data.entries[cpuid_i++];
566
567 c->function = i;
568 c->flags = 0;
569 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
570 }
571 }
572
573 cpuid_data.cpuid.nent = cpuid_i;
574
575 if (((env->cpuid_version >> 8)&0xF) >= 6
576 && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
577 && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
578 uint64_t mcg_cap;
579 int banks;
580 int ret;
581
582 ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
583 if (ret < 0) {
584 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
585 return ret;
586 }
587
588 if (banks > MCE_BANKS_DEF) {
589 banks = MCE_BANKS_DEF;
590 }
591 mcg_cap &= MCE_CAP_DEF;
592 mcg_cap |= banks;
593 ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
594 if (ret < 0) {
595 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
596 return ret;
597 }
598
599 env->mcg_cap = mcg_cap;
600 }
601
602 qemu_add_vm_change_state_handler(cpu_update_state, env);
603
604 cpuid_data.cpuid.padding = 0;
605 r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
606 if (r) {
607 return r;
608 }
609
610 r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
611 if (r && env->tsc_khz) {
612 r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
613 if (r < 0) {
614 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
615 return r;
616 }
617 }
618
619 if (kvm_has_xsave()) {
620 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
621 }
622
623 return 0;
624}
625
626void kvm_arch_reset_vcpu(CPUX86State *env)
627{
628 X86CPU *cpu = x86_env_get_cpu(env);
629
630 env->exception_injected = -1;
631 env->interrupt_injected = -1;
632 env->xcr0 = 1;
633 if (kvm_irqchip_in_kernel()) {
634 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
635 KVM_MP_STATE_UNINITIALIZED;
636 } else {
637 env->mp_state = KVM_MP_STATE_RUNNABLE;
638 }
639}
640
641static int kvm_get_supported_msrs(KVMState *s)
642{
643 static int kvm_supported_msrs;
644 int ret = 0;
645
646 /* first time */
647 if (kvm_supported_msrs == 0) {
648 struct kvm_msr_list msr_list, *kvm_msr_list;
649
650 kvm_supported_msrs = -1;
651
652 /* Obtain MSR list from KVM. These are the MSRs that we must
653 * save/restore */
654 msr_list.nmsrs = 0;
655 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
656 if (ret < 0 && ret != -E2BIG) {
657 return ret;
658 }
659 /* Old kernel modules had a bug and could write beyond the provided
660 memory. Allocate at least a safe amount of 1K. */
661 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
662 msr_list.nmsrs *
663 sizeof(msr_list.indices[0])));
664
665 kvm_msr_list->nmsrs = msr_list.nmsrs;
666 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
667 if (ret >= 0) {
668 int i;
669
670 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
671 if (kvm_msr_list->indices[i] == MSR_STAR) {
672 has_msr_star = true;
673 continue;
674 }
675 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
676 has_msr_hsave_pa = true;
677 continue;
678 }
679 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
680 has_msr_tsc_deadline = true;
681 continue;
682 }
683 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
684 has_msr_misc_enable = true;
685 continue;
686 }
687 }
688 }
689
690 g_free(kvm_msr_list);
691 }
692
693 return ret;
694}
695
696int kvm_arch_init(KVMState *s)
697{
698 QemuOptsList *list = qemu_find_opts("machine");
699 uint64_t identity_base = 0xfffbc000;
700 uint64_t shadow_mem;
701 int ret;
702 struct utsname utsname;
703
704 ret = kvm_get_supported_msrs(s);
705 if (ret < 0) {
706 return ret;
707 }
708
709 uname(&utsname);
710 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
711
712 /*
713 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
714 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
715 * Since these must be part of guest physical memory, we need to allocate
716 * them, both by setting their start addresses in the kernel and by
717 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
718 *
719 * Older KVM versions may not support setting the identity map base. In
720 * that case we need to stick with the default, i.e. a 256K maximum BIOS
721 * size.
722 */
723 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
724 /* Allows up to 16M BIOSes. */
725 identity_base = 0xfeffc000;
726
727 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
728 if (ret < 0) {
729 return ret;
730 }
731 }
732
733 /* Set TSS base one page after EPT identity map. */
734 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
735 if (ret < 0) {
736 return ret;
737 }
738
739 /* Tell fw_cfg to notify the BIOS to reserve the range. */
740 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
741 if (ret < 0) {
742 fprintf(stderr, "e820_add_entry() table is full\n");
743 return ret;
744 }
745 qemu_register_reset(kvm_unpoison_all, NULL);
746
747 if (!QTAILQ_EMPTY(&list->head)) {
748 shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
749 "kvm_shadow_mem", -1);
750 if (shadow_mem != -1) {
751 shadow_mem /= 4096;
752 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
753 if (ret < 0) {
754 return ret;
755 }
756 }
757 }
758 return 0;
759}
760
761static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
762{
763 lhs->selector = rhs->selector;
764 lhs->base = rhs->base;
765 lhs->limit = rhs->limit;
766 lhs->type = 3;
767 lhs->present = 1;
768 lhs->dpl = 3;
769 lhs->db = 0;
770 lhs->s = 1;
771 lhs->l = 0;
772 lhs->g = 0;
773 lhs->avl = 0;
774 lhs->unusable = 0;
775}
776
777static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
778{
779 unsigned flags = rhs->flags;
780 lhs->selector = rhs->selector;
781 lhs->base = rhs->base;
782 lhs->limit = rhs->limit;
783 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
784 lhs->present = (flags & DESC_P_MASK) != 0;
785 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
786 lhs->db = (flags >> DESC_B_SHIFT) & 1;
787 lhs->s = (flags & DESC_S_MASK) != 0;
788 lhs->l = (flags >> DESC_L_SHIFT) & 1;
789 lhs->g = (flags & DESC_G_MASK) != 0;
790 lhs->avl = (flags & DESC_AVL_MASK) != 0;
791 lhs->unusable = 0;
792 lhs->padding = 0;
793}
794
795static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
796{
797 lhs->selector = rhs->selector;
798 lhs->base = rhs->base;
799 lhs->limit = rhs->limit;
800 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
801 (rhs->present * DESC_P_MASK) |
802 (rhs->dpl << DESC_DPL_SHIFT) |
803 (rhs->db << DESC_B_SHIFT) |
804 (rhs->s * DESC_S_MASK) |
805 (rhs->l << DESC_L_SHIFT) |
806 (rhs->g * DESC_G_MASK) |
807 (rhs->avl * DESC_AVL_MASK);
808}
809
810static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
811{
812 if (set) {
813 *kvm_reg = *qemu_reg;
814 } else {
815 *qemu_reg = *kvm_reg;
816 }
817}
818
819static int kvm_getput_regs(CPUX86State *env, int set)
820{
821 struct kvm_regs regs;
822 int ret = 0;
823
824 if (!set) {
825 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
826 if (ret < 0) {
827 return ret;
828 }
829 }
830
831 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
832 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
833 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
834 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
835 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
836 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
837 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
838 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
839#ifdef TARGET_X86_64
840 kvm_getput_reg(&regs.r8, &env->regs[8], set);
841 kvm_getput_reg(&regs.r9, &env->regs[9], set);
842 kvm_getput_reg(&regs.r10, &env->regs[10], set);
843 kvm_getput_reg(&regs.r11, &env->regs[11], set);
844 kvm_getput_reg(&regs.r12, &env->regs[12], set);
845 kvm_getput_reg(&regs.r13, &env->regs[13], set);
846 kvm_getput_reg(&regs.r14, &env->regs[14], set);
847 kvm_getput_reg(&regs.r15, &env->regs[15], set);
848#endif
849
850 kvm_getput_reg(&regs.rflags, &env->eflags, set);
851 kvm_getput_reg(&regs.rip, &env->eip, set);
852
853 if (set) {
854 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
855 }
856
857 return ret;
858}
859
860static int kvm_put_fpu(CPUX86State *env)
861{
862 struct kvm_fpu fpu;
863 int i;
864
865 memset(&fpu, 0, sizeof fpu);
866 fpu.fsw = env->fpus & ~(7 << 11);
867 fpu.fsw |= (env->fpstt & 7) << 11;
868 fpu.fcw = env->fpuc;
869 fpu.last_opcode = env->fpop;
870 fpu.last_ip = env->fpip;
871 fpu.last_dp = env->fpdp;
872 for (i = 0; i < 8; ++i) {
873 fpu.ftwx |= (!env->fptags[i]) << i;
874 }
875 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
876 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
877 fpu.mxcsr = env->mxcsr;
878
879 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
880}
881
882#define XSAVE_FCW_FSW 0
883#define XSAVE_FTW_FOP 1
884#define XSAVE_CWD_RIP 2
885#define XSAVE_CWD_RDP 4
886#define XSAVE_MXCSR 6
887#define XSAVE_ST_SPACE 8
888#define XSAVE_XMM_SPACE 40
889#define XSAVE_XSTATE_BV 128
890#define XSAVE_YMMH_SPACE 144
891
892static int kvm_put_xsave(CPUX86State *env)
893{
894 struct kvm_xsave* xsave = env->kvm_xsave_buf;
895 uint16_t cwd, swd, twd;
896 int i, r;
897
898 if (!kvm_has_xsave()) {
899 return kvm_put_fpu(env);
900 }
901
902 memset(xsave, 0, sizeof(struct kvm_xsave));
903 twd = 0;
904 swd = env->fpus & ~(7 << 11);
905 swd |= (env->fpstt & 7) << 11;
906 cwd = env->fpuc;
907 for (i = 0; i < 8; ++i) {
908 twd |= (!env->fptags[i]) << i;
909 }
910 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
911 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
912 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
913 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
914 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
915 sizeof env->fpregs);
916 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
917 sizeof env->xmm_regs);
918 xsave->region[XSAVE_MXCSR] = env->mxcsr;
919 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
920 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
921 sizeof env->ymmh_regs);
922 r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
923 return r;
924}
925
926static int kvm_put_xcrs(CPUX86State *env)
927{
928 struct kvm_xcrs xcrs;
929
930 if (!kvm_has_xcrs()) {
931 return 0;
932 }
933
934 xcrs.nr_xcrs = 1;
935 xcrs.flags = 0;
936 xcrs.xcrs[0].xcr = 0;
937 xcrs.xcrs[0].value = env->xcr0;
938 return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
939}
940
941static int kvm_put_sregs(CPUX86State *env)
942{
943 struct kvm_sregs sregs;
944
945 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
946 if (env->interrupt_injected >= 0) {
947 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
948 (uint64_t)1 << (env->interrupt_injected % 64);
949 }
950
951 if ((env->eflags & VM_MASK)) {
952 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
953 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
954 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
955 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
956 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
957 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
958 } else {
959 set_seg(&sregs.cs, &env->segs[R_CS]);
960 set_seg(&sregs.ds, &env->segs[R_DS]);
961 set_seg(&sregs.es, &env->segs[R_ES]);
962 set_seg(&sregs.fs, &env->segs[R_FS]);
963 set_seg(&sregs.gs, &env->segs[R_GS]);
964 set_seg(&sregs.ss, &env->segs[R_SS]);
965 }
966
967 set_seg(&sregs.tr, &env->tr);
968 set_seg(&sregs.ldt, &env->ldt);
969
970 sregs.idt.limit = env->idt.limit;
971 sregs.idt.base = env->idt.base;
972 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
973 sregs.gdt.limit = env->gdt.limit;
974 sregs.gdt.base = env->gdt.base;
975 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
976
977 sregs.cr0 = env->cr[0];
978 sregs.cr2 = env->cr[2];
979 sregs.cr3 = env->cr[3];
980 sregs.cr4 = env->cr[4];
981
982 sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
983 sregs.apic_base = cpu_get_apic_base(env->apic_state);
984
985 sregs.efer = env->efer;
986
987 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
988}
989
990static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
991 uint32_t index, uint64_t value)
992{
993 entry->index = index;
994 entry->data = value;
995}
996
997static int kvm_put_msrs(CPUX86State *env, int level)
998{
999 struct {
1000 struct kvm_msrs info;
1001 struct kvm_msr_entry entries[100];
1002 } msr_data;
1003 struct kvm_msr_entry *msrs = msr_data.entries;
1004 int n = 0;
1005
1006 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1007 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1008 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1009 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1010 if (has_msr_star) {
1011 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1012 }
1013 if (has_msr_hsave_pa) {
1014 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1015 }
1016 if (has_msr_tsc_deadline) {
1017 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1018 }
1019 if (has_msr_misc_enable) {
1020 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1021 env->msr_ia32_misc_enable);
1022 }
1023#ifdef TARGET_X86_64
1024 if (lm_capable_kernel) {
1025 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1026 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1027 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1028 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1029 }
1030#endif
1031 if (level == KVM_PUT_FULL_STATE) {
1032 /*
1033 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1034 * writeback. Until this is fixed, we only write the offset to SMP
1035 * guests after migration, desynchronizing the VCPUs, but avoiding
1036 * huge jump-backs that would occur without any writeback at all.
1037 */
1038 if (smp_cpus == 1 || env->tsc != 0) {
1039 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1040 }
1041 }
1042 /*
1043 * The following paravirtual MSRs have side effects on the guest or are
1044 * too heavy for normal writeback. Limit them to reset or full state
1045 * updates.
1046 */
1047 if (level >= KVM_PUT_RESET_STATE) {
1048 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1049 env->system_time_msr);
1050 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1051 if (has_msr_async_pf_en) {
1052 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1053 env->async_pf_en_msr);
1054 }
1055 if (has_msr_pv_eoi_en) {
1056 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1057 env->pv_eoi_en_msr);
1058 }
1059 if (hyperv_hypercall_available()) {
1060 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1061 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1062 }
1063 if (hyperv_vapic_recommended()) {
1064 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1065 }
1066 }
1067 if (env->mcg_cap) {
1068 int i;
1069
1070 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1071 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1072 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1073 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1074 }
1075 }
1076
1077 msr_data.info.nmsrs = n;
1078
1079 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
1080
1081}
1082
1083
1084static int kvm_get_fpu(CPUX86State *env)
1085{
1086 struct kvm_fpu fpu;
1087 int i, ret;
1088
1089 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
1090 if (ret < 0) {
1091 return ret;
1092 }
1093
1094 env->fpstt = (fpu.fsw >> 11) & 7;
1095 env->fpus = fpu.fsw;
1096 env->fpuc = fpu.fcw;
1097 env->fpop = fpu.last_opcode;
1098 env->fpip = fpu.last_ip;
1099 env->fpdp = fpu.last_dp;
1100 for (i = 0; i < 8; ++i) {
1101 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1102 }
1103 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1104 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1105 env->mxcsr = fpu.mxcsr;
1106
1107 return 0;
1108}
1109
1110static int kvm_get_xsave(CPUX86State *env)
1111{
1112 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1113 int ret, i;
1114 uint16_t cwd, swd, twd;
1115
1116 if (!kvm_has_xsave()) {
1117 return kvm_get_fpu(env);
1118 }
1119
1120 ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
1121 if (ret < 0) {
1122 return ret;
1123 }
1124
1125 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1126 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1127 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1128 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1129 env->fpstt = (swd >> 11) & 7;
1130 env->fpus = swd;
1131 env->fpuc = cwd;
1132 for (i = 0; i < 8; ++i) {
1133 env->fptags[i] = !((twd >> i) & 1);
1134 }
1135 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1136 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1137 env->mxcsr = xsave->region[XSAVE_MXCSR];
1138 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1139 sizeof env->fpregs);
1140 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1141 sizeof env->xmm_regs);
1142 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1143 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1144 sizeof env->ymmh_regs);
1145 return 0;
1146}
1147
1148static int kvm_get_xcrs(CPUX86State *env)
1149{
1150 int i, ret;
1151 struct kvm_xcrs xcrs;
1152
1153 if (!kvm_has_xcrs()) {
1154 return 0;
1155 }
1156
1157 ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1158 if (ret < 0) {
1159 return ret;
1160 }
1161
1162 for (i = 0; i < xcrs.nr_xcrs; i++) {
1163 /* Only support xcr0 now */
1164 if (xcrs.xcrs[0].xcr == 0) {
1165 env->xcr0 = xcrs.xcrs[0].value;
1166 break;
1167 }
1168 }
1169 return 0;
1170}
1171
1172static int kvm_get_sregs(CPUX86State *env)
1173{
1174 struct kvm_sregs sregs;
1175 uint32_t hflags;
1176 int bit, i, ret;
1177
1178 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1179 if (ret < 0) {
1180 return ret;
1181 }
1182
1183 /* There can only be one pending IRQ set in the bitmap at a time, so try
1184 to find it and save its number instead (-1 for none). */
1185 env->interrupt_injected = -1;
1186 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1187 if (sregs.interrupt_bitmap[i]) {
1188 bit = ctz64(sregs.interrupt_bitmap[i]);
1189 env->interrupt_injected = i * 64 + bit;
1190 break;
1191 }
1192 }
1193
1194 get_seg(&env->segs[R_CS], &sregs.cs);
1195 get_seg(&env->segs[R_DS], &sregs.ds);
1196 get_seg(&env->segs[R_ES], &sregs.es);
1197 get_seg(&env->segs[R_FS], &sregs.fs);
1198 get_seg(&env->segs[R_GS], &sregs.gs);
1199 get_seg(&env->segs[R_SS], &sregs.ss);
1200
1201 get_seg(&env->tr, &sregs.tr);
1202 get_seg(&env->ldt, &sregs.ldt);
1203
1204 env->idt.limit = sregs.idt.limit;
1205 env->idt.base = sregs.idt.base;
1206 env->gdt.limit = sregs.gdt.limit;
1207 env->gdt.base = sregs.gdt.base;
1208
1209 env->cr[0] = sregs.cr0;
1210 env->cr[2] = sregs.cr2;
1211 env->cr[3] = sregs.cr3;
1212 env->cr[4] = sregs.cr4;
1213
1214 env->efer = sregs.efer;
1215
1216 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1217
1218#define HFLAG_COPY_MASK \
1219 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1220 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1221 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1222 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1223
1224 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1225 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1226 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1227 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1228 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1229 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1230 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1231
1232 if (env->efer & MSR_EFER_LMA) {
1233 hflags |= HF_LMA_MASK;
1234 }
1235
1236 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1237 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1238 } else {
1239 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1240 (DESC_B_SHIFT - HF_CS32_SHIFT);
1241 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1242 (DESC_B_SHIFT - HF_SS32_SHIFT);
1243 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1244 !(hflags & HF_CS32_MASK)) {
1245 hflags |= HF_ADDSEG_MASK;
1246 } else {
1247 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1248 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1249 }
1250 }
1251 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1252
1253 return 0;
1254}
1255
1256static int kvm_get_msrs(CPUX86State *env)
1257{
1258 struct {
1259 struct kvm_msrs info;
1260 struct kvm_msr_entry entries[100];
1261 } msr_data;
1262 struct kvm_msr_entry *msrs = msr_data.entries;
1263 int ret, i, n;
1264
1265 n = 0;
1266 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1267 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1268 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1269 msrs[n++].index = MSR_PAT;
1270 if (has_msr_star) {
1271 msrs[n++].index = MSR_STAR;
1272 }
1273 if (has_msr_hsave_pa) {
1274 msrs[n++].index = MSR_VM_HSAVE_PA;
1275 }
1276 if (has_msr_tsc_deadline) {
1277 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1278 }
1279 if (has_msr_misc_enable) {
1280 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1281 }
1282
1283 if (!env->tsc_valid) {
1284 msrs[n++].index = MSR_IA32_TSC;
1285 env->tsc_valid = !runstate_is_running();
1286 }
1287
1288#ifdef TARGET_X86_64
1289 if (lm_capable_kernel) {
1290 msrs[n++].index = MSR_CSTAR;
1291 msrs[n++].index = MSR_KERNELGSBASE;
1292 msrs[n++].index = MSR_FMASK;
1293 msrs[n++].index = MSR_LSTAR;
1294 }
1295#endif
1296 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1297 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1298 if (has_msr_async_pf_en) {
1299 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1300 }
1301 if (has_msr_pv_eoi_en) {
1302 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1303 }
1304
1305 if (env->mcg_cap) {
1306 msrs[n++].index = MSR_MCG_STATUS;
1307 msrs[n++].index = MSR_MCG_CTL;
1308 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1309 msrs[n++].index = MSR_MC0_CTL + i;
1310 }
1311 }
1312
1313 msr_data.info.nmsrs = n;
1314 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1315 if (ret < 0) {
1316 return ret;
1317 }
1318
1319 for (i = 0; i < ret; i++) {
1320 switch (msrs[i].index) {
1321 case MSR_IA32_SYSENTER_CS:
1322 env->sysenter_cs = msrs[i].data;
1323 break;
1324 case MSR_IA32_SYSENTER_ESP:
1325 env->sysenter_esp = msrs[i].data;
1326 break;
1327 case MSR_IA32_SYSENTER_EIP:
1328 env->sysenter_eip = msrs[i].data;
1329 break;
1330 case MSR_PAT:
1331 env->pat = msrs[i].data;
1332 break;
1333 case MSR_STAR:
1334 env->star = msrs[i].data;
1335 break;
1336#ifdef TARGET_X86_64
1337 case MSR_CSTAR:
1338 env->cstar = msrs[i].data;
1339 break;
1340 case MSR_KERNELGSBASE:
1341 env->kernelgsbase = msrs[i].data;
1342 break;
1343 case MSR_FMASK:
1344 env->fmask = msrs[i].data;
1345 break;
1346 case MSR_LSTAR:
1347 env->lstar = msrs[i].data;
1348 break;
1349#endif
1350 case MSR_IA32_TSC:
1351 env->tsc = msrs[i].data;
1352 break;
1353 case MSR_IA32_TSCDEADLINE:
1354 env->tsc_deadline = msrs[i].data;
1355 break;
1356 case MSR_VM_HSAVE_PA:
1357 env->vm_hsave = msrs[i].data;
1358 break;
1359 case MSR_KVM_SYSTEM_TIME:
1360 env->system_time_msr = msrs[i].data;
1361 break;
1362 case MSR_KVM_WALL_CLOCK:
1363 env->wall_clock_msr = msrs[i].data;
1364 break;
1365 case MSR_MCG_STATUS:
1366 env->mcg_status = msrs[i].data;
1367 break;
1368 case MSR_MCG_CTL:
1369 env->mcg_ctl = msrs[i].data;
1370 break;
1371 case MSR_IA32_MISC_ENABLE:
1372 env->msr_ia32_misc_enable = msrs[i].data;
1373 break;
1374 default:
1375 if (msrs[i].index >= MSR_MC0_CTL &&
1376 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1377 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1378 }
1379 break;
1380 case MSR_KVM_ASYNC_PF_EN:
1381 env->async_pf_en_msr = msrs[i].data;
1382 break;
1383 case MSR_KVM_PV_EOI_EN:
1384 env->pv_eoi_en_msr = msrs[i].data;
1385 break;
1386 }
1387 }
1388
1389 return 0;
1390}
1391
1392static int kvm_put_mp_state(CPUX86State *env)
1393{
1394 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1395
1396 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1397}
1398
1399static int kvm_get_mp_state(X86CPU *cpu)
1400{
1401 CPUX86State *env = &cpu->env;
1402 struct kvm_mp_state mp_state;
1403 int ret;
1404
1405 ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1406 if (ret < 0) {
1407 return ret;
1408 }
1409 env->mp_state = mp_state.mp_state;
1410 if (kvm_irqchip_in_kernel()) {
1411 env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1412 }
1413 return 0;
1414}
1415
1416static int kvm_get_apic(CPUX86State *env)
1417{
1418 DeviceState *apic = env->apic_state;
1419 struct kvm_lapic_state kapic;
1420 int ret;
1421
1422 if (apic && kvm_irqchip_in_kernel()) {
1423 ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic);
1424 if (ret < 0) {
1425 return ret;
1426 }
1427
1428 kvm_get_apic_state(apic, &kapic);
1429 }
1430 return 0;
1431}
1432
1433static int kvm_put_apic(CPUX86State *env)
1434{
1435 DeviceState *apic = env->apic_state;
1436 struct kvm_lapic_state kapic;
1437
1438 if (apic && kvm_irqchip_in_kernel()) {
1439 kvm_put_apic_state(apic, &kapic);
1440
1441 return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);
1442 }
1443 return 0;
1444}
1445
1446static int kvm_put_vcpu_events(CPUX86State *env, int level)
1447{
1448 struct kvm_vcpu_events events;
1449
1450 if (!kvm_has_vcpu_events()) {
1451 return 0;
1452 }
1453
1454 events.exception.injected = (env->exception_injected >= 0);
1455 events.exception.nr = env->exception_injected;
1456 events.exception.has_error_code = env->has_error_code;
1457 events.exception.error_code = env->error_code;
1458 events.exception.pad = 0;
1459
1460 events.interrupt.injected = (env->interrupt_injected >= 0);
1461 events.interrupt.nr = env->interrupt_injected;
1462 events.interrupt.soft = env->soft_interrupt;
1463
1464 events.nmi.injected = env->nmi_injected;
1465 events.nmi.pending = env->nmi_pending;
1466 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1467 events.nmi.pad = 0;
1468
1469 events.sipi_vector = env->sipi_vector;
1470
1471 events.flags = 0;
1472 if (level >= KVM_PUT_RESET_STATE) {
1473 events.flags |=
1474 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1475 }
1476
1477 return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1478}
1479
1480static int kvm_get_vcpu_events(CPUX86State *env)
1481{
1482 struct kvm_vcpu_events events;
1483 int ret;
1484
1485 if (!kvm_has_vcpu_events()) {
1486 return 0;
1487 }
1488
1489 ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1490 if (ret < 0) {
1491 return ret;
1492 }
1493 env->exception_injected =
1494 events.exception.injected ? events.exception.nr : -1;
1495 env->has_error_code = events.exception.has_error_code;
1496 env->error_code = events.exception.error_code;
1497
1498 env->interrupt_injected =
1499 events.interrupt.injected ? events.interrupt.nr : -1;
1500 env->soft_interrupt = events.interrupt.soft;
1501
1502 env->nmi_injected = events.nmi.injected;
1503 env->nmi_pending = events.nmi.pending;
1504 if (events.nmi.masked) {
1505 env->hflags2 |= HF2_NMI_MASK;
1506 } else {
1507 env->hflags2 &= ~HF2_NMI_MASK;
1508 }
1509
1510 env->sipi_vector = events.sipi_vector;
1511
1512 return 0;
1513}
1514
1515static int kvm_guest_debug_workarounds(CPUX86State *env)
1516{
1517 int ret = 0;
1518 unsigned long reinject_trap = 0;
1519
1520 if (!kvm_has_vcpu_events()) {
1521 if (env->exception_injected == 1) {
1522 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1523 } else if (env->exception_injected == 3) {
1524 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1525 }
1526 env->exception_injected = -1;
1527 }
1528
1529 /*
1530 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1531 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1532 * by updating the debug state once again if single-stepping is on.
1533 * Another reason to call kvm_update_guest_debug here is a pending debug
1534 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1535 * reinject them via SET_GUEST_DEBUG.
1536 */
1537 if (reinject_trap ||
1538 (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1539 ret = kvm_update_guest_debug(env, reinject_trap);
1540 }
1541 return ret;
1542}
1543
1544static int kvm_put_debugregs(CPUX86State *env)
1545{
1546 struct kvm_debugregs dbgregs;
1547 int i;
1548
1549 if (!kvm_has_debugregs()) {
1550 return 0;
1551 }
1552
1553 for (i = 0; i < 4; i++) {
1554 dbgregs.db[i] = env->dr[i];
1555 }
1556 dbgregs.dr6 = env->dr[6];
1557 dbgregs.dr7 = env->dr[7];
1558 dbgregs.flags = 0;
1559
1560 return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1561}
1562
1563static int kvm_get_debugregs(CPUX86State *env)
1564{
1565 struct kvm_debugregs dbgregs;
1566 int i, ret;
1567
1568 if (!kvm_has_debugregs()) {
1569 return 0;
1570 }
1571
1572 ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1573 if (ret < 0) {
1574 return ret;
1575 }
1576 for (i = 0; i < 4; i++) {
1577 env->dr[i] = dbgregs.db[i];
1578 }
1579 env->dr[4] = env->dr[6] = dbgregs.dr6;
1580 env->dr[5] = env->dr[7] = dbgregs.dr7;
1581
1582 return 0;
1583}
1584
1585int kvm_arch_put_registers(CPUX86State *env, int level)
1586{
1587 CPUState *cpu = ENV_GET_CPU(env);
1588 int ret;
1589
1590 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1591
1592 ret = kvm_getput_regs(env, 1);
1593 if (ret < 0) {
1594 return ret;
1595 }
1596 ret = kvm_put_xsave(env);
1597 if (ret < 0) {
1598 return ret;
1599 }
1600 ret = kvm_put_xcrs(env);
1601 if (ret < 0) {
1602 return ret;
1603 }
1604 ret = kvm_put_sregs(env);
1605 if (ret < 0) {
1606 return ret;
1607 }
1608 /* must be before kvm_put_msrs */
1609 ret = kvm_inject_mce_oldstyle(env);
1610 if (ret < 0) {
1611 return ret;
1612 }
1613 ret = kvm_put_msrs(env, level);
1614 if (ret < 0) {
1615 return ret;
1616 }
1617 if (level >= KVM_PUT_RESET_STATE) {
1618 ret = kvm_put_mp_state(env);
1619 if (ret < 0) {
1620 return ret;
1621 }
1622 ret = kvm_put_apic(env);
1623 if (ret < 0) {
1624 return ret;
1625 }
1626 }
1627 ret = kvm_put_vcpu_events(env, level);
1628 if (ret < 0) {
1629 return ret;
1630 }
1631 ret = kvm_put_debugregs(env);
1632 if (ret < 0) {
1633 return ret;
1634 }
1635 /* must be last */
1636 ret = kvm_guest_debug_workarounds(env);
1637 if (ret < 0) {
1638 return ret;
1639 }
1640 return 0;
1641}
1642
1643int kvm_arch_get_registers(CPUX86State *env)
1644{
1645 X86CPU *cpu = x86_env_get_cpu(env);
1646 int ret;
1647
1648 assert(cpu_is_stopped(CPU(cpu)) || qemu_cpu_is_self(CPU(cpu)));
1649
1650 ret = kvm_getput_regs(env, 0);
1651 if (ret < 0) {
1652 return ret;
1653 }
1654 ret = kvm_get_xsave(env);
1655 if (ret < 0) {
1656 return ret;
1657 }
1658 ret = kvm_get_xcrs(env);
1659 if (ret < 0) {
1660 return ret;
1661 }
1662 ret = kvm_get_sregs(env);
1663 if (ret < 0) {
1664 return ret;
1665 }
1666 ret = kvm_get_msrs(env);
1667 if (ret < 0) {
1668 return ret;
1669 }
1670 ret = kvm_get_mp_state(cpu);
1671 if (ret < 0) {
1672 return ret;
1673 }
1674 ret = kvm_get_apic(env);
1675 if (ret < 0) {
1676 return ret;
1677 }
1678 ret = kvm_get_vcpu_events(env);
1679 if (ret < 0) {
1680 return ret;
1681 }
1682 ret = kvm_get_debugregs(env);
1683 if (ret < 0) {
1684 return ret;
1685 }
1686 return 0;
1687}
1688
1689void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run)
1690{
1691 int ret;
1692
1693 /* Inject NMI */
1694 if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1695 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1696 DPRINTF("injected NMI\n");
1697 ret = kvm_vcpu_ioctl(env, KVM_NMI);
1698 if (ret < 0) {
1699 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1700 strerror(-ret));
1701 }
1702 }
1703
1704 if (!kvm_irqchip_in_kernel()) {
1705 /* Force the VCPU out of its inner loop to process any INIT requests
1706 * or pending TPR access reports. */
1707 if (env->interrupt_request &
1708 (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1709 env->exit_request = 1;
1710 }
1711
1712 /* Try to inject an interrupt if the guest can accept it */
1713 if (run->ready_for_interrupt_injection &&
1714 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1715 (env->eflags & IF_MASK)) {
1716 int irq;
1717
1718 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1719 irq = cpu_get_pic_interrupt(env);
1720 if (irq >= 0) {
1721 struct kvm_interrupt intr;
1722
1723 intr.irq = irq;
1724 DPRINTF("injected interrupt %d\n", irq);
1725 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1726 if (ret < 0) {
1727 fprintf(stderr,
1728 "KVM: injection failed, interrupt lost (%s)\n",
1729 strerror(-ret));
1730 }
1731 }
1732 }
1733
1734 /* If we have an interrupt but the guest is not ready to receive an
1735 * interrupt, request an interrupt window exit. This will
1736 * cause a return to userspace as soon as the guest is ready to
1737 * receive interrupts. */
1738 if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1739 run->request_interrupt_window = 1;
1740 } else {
1741 run->request_interrupt_window = 0;
1742 }
1743
1744 DPRINTF("setting tpr\n");
1745 run->cr8 = cpu_get_apic_tpr(env->apic_state);
1746 }
1747}
1748
1749void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run)
1750{
1751 if (run->if_flag) {
1752 env->eflags |= IF_MASK;
1753 } else {
1754 env->eflags &= ~IF_MASK;
1755 }
1756 cpu_set_apic_tpr(env->apic_state, run->cr8);
1757 cpu_set_apic_base(env->apic_state, run->apic_base);
1758}
1759
1760int kvm_arch_process_async_events(CPUX86State *env)
1761{
1762 X86CPU *cpu = x86_env_get_cpu(env);
1763
1764 if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1765 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1766 assert(env->mcg_cap);
1767
1768 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1769
1770 kvm_cpu_synchronize_state(env);
1771
1772 if (env->exception_injected == EXCP08_DBLE) {
1773 /* this means triple fault */
1774 qemu_system_reset_request();
1775 env->exit_request = 1;
1776 return 0;
1777 }
1778 env->exception_injected = EXCP12_MCHK;
1779 env->has_error_code = 0;
1780
1781 env->halted = 0;
1782 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1783 env->mp_state = KVM_MP_STATE_RUNNABLE;
1784 }
1785 }
1786
1787 if (kvm_irqchip_in_kernel()) {
1788 return 0;
1789 }
1790
1791 if (env->interrupt_request & CPU_INTERRUPT_POLL) {
1792 env->interrupt_request &= ~CPU_INTERRUPT_POLL;
1793 apic_poll_irq(env->apic_state);
1794 }
1795 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1796 (env->eflags & IF_MASK)) ||
1797 (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1798 env->halted = 0;
1799 }
1800 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1801 kvm_cpu_synchronize_state(env);
1802 do_cpu_init(cpu);
1803 }
1804 if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1805 kvm_cpu_synchronize_state(env);
1806 do_cpu_sipi(cpu);
1807 }
1808 if (env->interrupt_request & CPU_INTERRUPT_TPR) {
1809 env->interrupt_request &= ~CPU_INTERRUPT_TPR;
1810 kvm_cpu_synchronize_state(env);
1811 apic_handle_tpr_access_report(env->apic_state, env->eip,
1812 env->tpr_access_type);
1813 }
1814
1815 return env->halted;
1816}
1817
1818static int kvm_handle_halt(X86CPU *cpu)
1819{
1820 CPUX86State *env = &cpu->env;
1821
1822 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1823 (env->eflags & IF_MASK)) &&
1824 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1825 env->halted = 1;
1826 return EXCP_HLT;
1827 }
1828
1829 return 0;
1830}
1831
1832static int kvm_handle_tpr_access(CPUX86State *env)
1833{
1834 struct kvm_run *run = env->kvm_run;
1835
1836 apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1837 run->tpr_access.is_write ? TPR_ACCESS_WRITE
1838 : TPR_ACCESS_READ);
1839 return 1;
1840}
1841
1842int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1843{
1844 static const uint8_t int3 = 0xcc;
1845
1846 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1847 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1848 return -EINVAL;
1849 }
1850 return 0;
1851}
1852
1853int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1854{
1855 uint8_t int3;
1856
1857 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1858 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1859 return -EINVAL;
1860 }
1861 return 0;
1862}
1863
1864static struct {
1865 target_ulong addr;
1866 int len;
1867 int type;
1868} hw_breakpoint[4];
1869
1870static int nb_hw_breakpoint;
1871
1872static int find_hw_breakpoint(target_ulong addr, int len, int type)
1873{
1874 int n;
1875
1876 for (n = 0; n < nb_hw_breakpoint; n++) {
1877 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1878 (hw_breakpoint[n].len == len || len == -1)) {
1879 return n;
1880 }
1881 }
1882 return -1;
1883}
1884
1885int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1886 target_ulong len, int type)
1887{
1888 switch (type) {
1889 case GDB_BREAKPOINT_HW:
1890 len = 1;
1891 break;
1892 case GDB_WATCHPOINT_WRITE:
1893 case GDB_WATCHPOINT_ACCESS:
1894 switch (len) {
1895 case 1:
1896 break;
1897 case 2:
1898 case 4:
1899 case 8:
1900 if (addr & (len - 1)) {
1901 return -EINVAL;
1902 }
1903 break;
1904 default:
1905 return -EINVAL;
1906 }
1907 break;
1908 default:
1909 return -ENOSYS;
1910 }
1911
1912 if (nb_hw_breakpoint == 4) {
1913 return -ENOBUFS;
1914 }
1915 if (find_hw_breakpoint(addr, len, type) >= 0) {
1916 return -EEXIST;
1917 }
1918 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1919 hw_breakpoint[nb_hw_breakpoint].len = len;
1920 hw_breakpoint[nb_hw_breakpoint].type = type;
1921 nb_hw_breakpoint++;
1922
1923 return 0;
1924}
1925
1926int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1927 target_ulong len, int type)
1928{
1929 int n;
1930
1931 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1932 if (n < 0) {
1933 return -ENOENT;
1934 }
1935 nb_hw_breakpoint--;
1936 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1937
1938 return 0;
1939}
1940
1941void kvm_arch_remove_all_hw_breakpoints(void)
1942{
1943 nb_hw_breakpoint = 0;
1944}
1945
1946static CPUWatchpoint hw_watchpoint;
1947
1948static int kvm_handle_debug(CPUX86State *env,
1949 struct kvm_debug_exit_arch *arch_info)
1950{
1951 int ret = 0;
1952 int n;
1953
1954 if (arch_info->exception == 1) {
1955 if (arch_info->dr6 & (1 << 14)) {
1956 if (env->singlestep_enabled) {
1957 ret = EXCP_DEBUG;
1958 }
1959 } else {
1960 for (n = 0; n < 4; n++) {
1961 if (arch_info->dr6 & (1 << n)) {
1962 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1963 case 0x0:
1964 ret = EXCP_DEBUG;
1965 break;
1966 case 0x1:
1967 ret = EXCP_DEBUG;
1968 env->watchpoint_hit = &hw_watchpoint;
1969 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1970 hw_watchpoint.flags = BP_MEM_WRITE;
1971 break;
1972 case 0x3:
1973 ret = EXCP_DEBUG;
1974 env->watchpoint_hit = &hw_watchpoint;
1975 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1976 hw_watchpoint.flags = BP_MEM_ACCESS;
1977 break;
1978 }
1979 }
1980 }
1981 }
1982 } else if (kvm_find_sw_breakpoint(env, arch_info->pc)) {
1983 ret = EXCP_DEBUG;
1984 }
1985 if (ret == 0) {
1986 cpu_synchronize_state(env);
1987 assert(env->exception_injected == -1);
1988
1989 /* pass to guest */
1990 env->exception_injected = arch_info->exception;
1991 env->has_error_code = 0;
1992 }
1993
1994 return ret;
1995}
1996
1997void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg)
1998{
1999 const uint8_t type_code[] = {
2000 [GDB_BREAKPOINT_HW] = 0x0,
2001 [GDB_WATCHPOINT_WRITE] = 0x1,
2002 [GDB_WATCHPOINT_ACCESS] = 0x3
2003 };
2004 const uint8_t len_code[] = {
2005 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2006 };
2007 int n;
2008
2009 if (kvm_sw_breakpoints_active(env)) {
2010 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2011 }
2012 if (nb_hw_breakpoint > 0) {
2013 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2014 dbg->arch.debugreg[7] = 0x0600;
2015 for (n = 0; n < nb_hw_breakpoint; n++) {
2016 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2017 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2018 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2019 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2020 }
2021 }
2022}
2023
2024static bool host_supports_vmx(void)
2025{
2026 uint32_t ecx, unused;
2027
2028 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2029 return ecx & CPUID_EXT_VMX;
2030}
2031
2032#define VMX_INVALID_GUEST_STATE 0x80000021
2033
2034int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
2035{
2036 X86CPU *cpu = x86_env_get_cpu(env);
2037 uint64_t code;
2038 int ret;
2039
2040 switch (run->exit_reason) {
2041 case KVM_EXIT_HLT:
2042 DPRINTF("handle_hlt\n");
2043 ret = kvm_handle_halt(cpu);
2044 break;
2045 case KVM_EXIT_SET_TPR:
2046 ret = 0;
2047 break;
2048 case KVM_EXIT_TPR_ACCESS:
2049 ret = kvm_handle_tpr_access(env);
2050 break;
2051 case KVM_EXIT_FAIL_ENTRY:
2052 code = run->fail_entry.hardware_entry_failure_reason;
2053 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2054 code);
2055 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2056 fprintf(stderr,
2057 "\nIf you're running a guest on an Intel machine without "
2058 "unrestricted mode\n"
2059 "support, the failure can be most likely due to the guest "
2060 "entering an invalid\n"
2061 "state for Intel VT. For example, the guest maybe running "
2062 "in big real mode\n"
2063 "which is not supported on less recent Intel processors."
2064 "\n\n");
2065 }
2066 ret = -1;
2067 break;
2068 case KVM_EXIT_EXCEPTION:
2069 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2070 run->ex.exception, run->ex.error_code);
2071 ret = -1;
2072 break;
2073 case KVM_EXIT_DEBUG:
2074 DPRINTF("kvm_exit_debug\n");
2075 ret = kvm_handle_debug(env, &run->debug.arch);
2076 break;
2077 default:
2078 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2079 ret = -1;
2080 break;
2081 }
2082
2083 return ret;
2084}
2085
2086bool kvm_arch_stop_on_emulation_error(CPUX86State *env)
2087{
2088 kvm_cpu_synchronize_state(env);
2089 return !(env->cr[0] & CR0_PE_MASK) ||
2090 ((env->segs[R_CS].selector & 3) != 3);
2091}
2092
2093void kvm_arch_init_irq_routing(KVMState *s)
2094{
2095 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2096 /* If kernel can't do irq routing, interrupt source
2097 * override 0->2 cannot be set up as required by HPET.
2098 * So we have to disable it.
2099 */
2100 no_hpet = 1;
2101 }
2102 /* We know at this point that we're using the in-kernel
2103 * irqchip, so we can use irqfds, and on x86 we know
2104 * we can use msi via irqfd and GSI routing.
2105 */
2106 kvm_irqfds_allowed = true;
2107 kvm_msi_via_irqfd_allowed = true;
2108 kvm_gsi_routing_allowed = true;
2109}
2110
2111/* Classic KVM device assignment interface. Will remain x86 only. */
2112int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2113 uint32_t flags, uint32_t *dev_id)
2114{
2115 struct kvm_assigned_pci_dev dev_data = {
2116 .segnr = dev_addr->domain,
2117 .busnr = dev_addr->bus,
2118 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2119 .flags = flags,
2120 };
2121 int ret;
2122
2123 dev_data.assigned_dev_id =
2124 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2125
2126 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2127 if (ret < 0) {
2128 return ret;
2129 }
2130
2131 *dev_id = dev_data.assigned_dev_id;
2132
2133 return 0;
2134}
2135
2136int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2137{
2138 struct kvm_assigned_pci_dev dev_data = {
2139 .assigned_dev_id = dev_id,
2140 };
2141
2142 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2143}
2144
2145static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2146 uint32_t irq_type, uint32_t guest_irq)
2147{
2148 struct kvm_assigned_irq assigned_irq = {
2149 .assigned_dev_id = dev_id,
2150 .guest_irq = guest_irq,
2151 .flags = irq_type,
2152 };
2153
2154 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2155 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2156 } else {
2157 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2158 }
2159}
2160
2161int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2162 uint32_t guest_irq)
2163{
2164 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2165 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2166
2167 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2168}
2169
2170int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2171{
2172 struct kvm_assigned_pci_dev dev_data = {
2173 .assigned_dev_id = dev_id,
2174 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2175 };
2176
2177 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2178}
2179
2180static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2181 uint32_t type)
2182{
2183 struct kvm_assigned_irq assigned_irq = {
2184 .assigned_dev_id = dev_id,
2185 .flags = type,
2186 };
2187
2188 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2189}
2190
2191int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2192{
2193 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2194 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2195}
2196
2197int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2198{
2199 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2200 KVM_DEV_IRQ_GUEST_MSI, virq);
2201}
2202
2203int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2204{
2205 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2206 KVM_DEV_IRQ_HOST_MSI);
2207}
2208
2209bool kvm_device_msix_supported(KVMState *s)
2210{
2211 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2212 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2213 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2214}
2215
2216int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2217 uint32_t nr_vectors)
2218{
2219 struct kvm_assigned_msix_nr msix_nr = {
2220 .assigned_dev_id = dev_id,
2221 .entry_nr = nr_vectors,
2222 };
2223
2224 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2225}
2226
2227int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2228 int virq)
2229{
2230 struct kvm_assigned_msix_entry msix_entry = {
2231 .assigned_dev_id = dev_id,
2232 .gsi = virq,
2233 .entry = vector,
2234 };
2235
2236 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2237}
2238
2239int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2240{
2241 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2242 KVM_DEV_IRQ_GUEST_MSIX, 0);
2243}
2244
2245int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2246{
2247 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2248 KVM_DEV_IRQ_HOST_MSIX);
2249}
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