]> Git Repo - qemu.git/blame_incremental - target-sparc/cpu.h
projects / qemu.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
SuperSparc MXCC support (Robert Reif)
[qemu.git] / target-sparc / cpu.h
... / ...
CommitLineData
1#ifndef CPU_SPARC_H
2#define CPU_SPARC_H
3
4#include "config.h"
5
6#if !defined(TARGET_SPARC64)
7#define TARGET_LONG_BITS 32
8#define TARGET_FPREGS 32
9#define TARGET_PAGE_BITS 12 /* 4k */
10#else
11#define TARGET_LONG_BITS 64
12#define TARGET_FPREGS 64
13#define TARGET_PAGE_BITS 13 /* 8k */
14#endif
15
16#define TARGET_PHYS_ADDR_BITS 64
17
18#include "cpu-defs.h"
19
20#include "softfloat.h"
21
22#define TARGET_HAS_ICE 1
23
24#if !defined(TARGET_SPARC64)
25#define ELF_MACHINE EM_SPARC
26#else
27#define ELF_MACHINE EM_SPARCV9
28#endif
29
30/*#define EXCP_INTERRUPT 0x100*/
31
32/* trap definitions */
33#ifndef TARGET_SPARC64
34#define TT_TFAULT 0x01
35#define TT_ILL_INSN 0x02
36#define TT_PRIV_INSN 0x03
37#define TT_NFPU_INSN 0x04
38#define TT_WIN_OVF 0x05
39#define TT_WIN_UNF 0x06
40#define TT_UNALIGNED 0x07
41#define TT_FP_EXCP 0x08
42#define TT_DFAULT 0x09
43#define TT_TOVF 0x0a
44#define TT_EXTINT 0x10
45#define TT_CODE_ACCESS 0x21
46#define TT_DATA_ACCESS 0x29
47#define TT_DIV_ZERO 0x2a
48#define TT_NCP_INSN 0x24
49#define TT_TRAP 0x80
50#else
51#define TT_TFAULT 0x08
52#define TT_TMISS 0x09
53#define TT_CODE_ACCESS 0x0a
54#define TT_ILL_INSN 0x10
55#define TT_PRIV_INSN 0x11
56#define TT_NFPU_INSN 0x20
57#define TT_FP_EXCP 0x21
58#define TT_TOVF 0x23
59#define TT_CLRWIN 0x24
60#define TT_DIV_ZERO 0x28
61#define TT_DFAULT 0x30
62#define TT_DMISS 0x31
63#define TT_DATA_ACCESS 0x32
64#define TT_DPROT 0x33
65#define TT_UNALIGNED 0x34
66#define TT_PRIV_ACT 0x37
67#define TT_EXTINT 0x40
68#define TT_SPILL 0x80
69#define TT_FILL 0xc0
70#define TT_WOTHER 0x10
71#define TT_TRAP 0x100
72#endif
73
74#define PSR_NEG (1<<23)
75#define PSR_ZERO (1<<22)
76#define PSR_OVF (1<<21)
77#define PSR_CARRY (1<<20)
78#define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
79#define PSR_EF (1<<12)
80#define PSR_PIL 0xf00
81#define PSR_S (1<<7)
82#define PSR_PS (1<<6)
83#define PSR_ET (1<<5)
84#define PSR_CWP 0x1f
85
86/* Trap base register */
87#define TBR_BASE_MASK 0xfffff000
88
89#if defined(TARGET_SPARC64)
90#define PS_IG (1<<11)
91#define PS_MG (1<<10)
92#define PS_RMO (1<<7)
93#define PS_RED (1<<5)
94#define PS_PEF (1<<4)
95#define PS_AM (1<<3)
96#define PS_PRIV (1<<2)
97#define PS_IE (1<<1)
98#define PS_AG (1<<0)
99
100#define FPRS_FEF (1<<2)
101#endif
102
103/* Fcc */
104#define FSR_RD1 (1<<31)
105#define FSR_RD0 (1<<30)
106#define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
107#define FSR_RD_NEAREST 0
108#define FSR_RD_ZERO FSR_RD0
109#define FSR_RD_POS FSR_RD1
110#define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
111
112#define FSR_NVM (1<<27)
113#define FSR_OFM (1<<26)
114#define FSR_UFM (1<<25)
115#define FSR_DZM (1<<24)
116#define FSR_NXM (1<<23)
117#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
118
119#define FSR_NVA (1<<9)
120#define FSR_OFA (1<<8)
121#define FSR_UFA (1<<7)
122#define FSR_DZA (1<<6)
123#define FSR_NXA (1<<5)
124#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
125
126#define FSR_NVC (1<<4)
127#define FSR_OFC (1<<3)
128#define FSR_UFC (1<<2)
129#define FSR_DZC (1<<1)
130#define FSR_NXC (1<<0)
131#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
132
133#define FSR_FTT2 (1<<16)
134#define FSR_FTT1 (1<<15)
135#define FSR_FTT0 (1<<14)
136#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
137#define FSR_FTT_IEEE_EXCP (1 << 14)
138#define FSR_FTT_UNIMPFPOP (3 << 14)
139#define FSR_FTT_SEQ_ERROR (4 << 14)
140#define FSR_FTT_INVAL_FPR (6 << 14)
141
142#define FSR_FCC1 (1<<11)
143#define FSR_FCC0 (1<<10)
144
145/* MMU */
146#define MMU_E (1<<0)
147#define MMU_NF (1<<1)
148#define MMU_BM (1<<14)
149
150#define PTE_ENTRYTYPE_MASK 3
151#define PTE_ACCESS_MASK 0x1c
152#define PTE_ACCESS_SHIFT 2
153#define PTE_PPN_SHIFT 7
154#define PTE_ADDR_MASK 0xffffff00
155
156#define PG_ACCESSED_BIT 5
157#define PG_MODIFIED_BIT 6
158#define PG_CACHE_BIT 7
159
160#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
161#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
162#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
163
164/* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
165#define NWINDOWS 8
166
167typedef struct sparc_def_t sparc_def_t;
168
169#define NB_MMU_MODES 2
170
171typedef struct CPUSPARCState {
172 target_ulong gregs[8]; /* general registers */
173 target_ulong *regwptr; /* pointer to current register window */
174 float32 fpr[TARGET_FPREGS]; /* floating point registers */
175 target_ulong pc; /* program counter */
176 target_ulong npc; /* next program counter */
177 target_ulong y; /* multiply/divide register */
178 uint32_t psr; /* processor state register */
179 target_ulong fsr; /* FPU state register */
180 uint32_t cwp; /* index of current register window (extracted
181 from PSR) */
182 uint32_t wim; /* window invalid mask */
183 target_ulong tbr; /* trap base register */
184 int psrs; /* supervisor mode (extracted from PSR) */
185 int psrps; /* previous supervisor mode */
186 int psret; /* enable traps */
187 uint32_t psrpil; /* interrupt blocking level */
188 uint32_t pil_in; /* incoming interrupt level bitmap */
189 int psref; /* enable fpu */
190 target_ulong version;
191 jmp_buf jmp_env;
192 int user_mode_only;
193 int exception_index;
194 int interrupt_index;
195 int interrupt_request;
196 int halted;
197 /* NOTE: we allow 8 more registers to handle wrapping */
198 target_ulong regbase[NWINDOWS * 16 + 8];
199
200 CPU_COMMON
201
202 /* MMU regs */
203#if defined(TARGET_SPARC64)
204 uint64_t lsu;
205#define DMMU_E 0x8
206#define IMMU_E 0x4
207 uint64_t immuregs[16];
208 uint64_t dmmuregs[16];
209 uint64_t itlb_tag[64];
210 uint64_t itlb_tte[64];
211 uint64_t dtlb_tag[64];
212 uint64_t dtlb_tte[64];
213#else
214 uint32_t mmuregs[16];
215 uint64_t mxccdata[4];
216 uint64_t mxccregs[8];
217#endif
218 /* temporary float registers */
219 float32 ft0, ft1;
220 float64 dt0, dt1;
221 float_status fp_status;
222#if defined(TARGET_SPARC64)
223#define MAXTL 4
224 uint64_t t0, t1, t2;
225 uint64_t tpc[MAXTL];
226 uint64_t tnpc[MAXTL];
227 uint64_t tstate[MAXTL];
228 uint32_t tt[MAXTL];
229 uint32_t xcc; /* Extended integer condition codes */
230 uint32_t asi;
231 uint32_t pstate;
232 uint32_t tl;
233 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
234 uint64_t agregs[8]; /* alternate general registers */
235 uint64_t bgregs[8]; /* backup for normal global registers */
236 uint64_t igregs[8]; /* interrupt general registers */
237 uint64_t mgregs[8]; /* mmu general registers */
238 uint64_t fprs;
239 uint64_t tick_cmpr, stick_cmpr;
240 void *tick, *stick;
241 uint64_t gsr;
242 uint32_t gl; // UA2005
243 /* UA 2005 hyperprivileged registers */
244 uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr;
245 void *hstick; // UA 2005
246#endif
247#if !defined(TARGET_SPARC64) && !defined(reg_T2)
248 target_ulong t2;
249#endif
250} CPUSPARCState;
251#if defined(TARGET_SPARC64)
252#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
253#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
254 env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
255 } while (0)
256#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
257#define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
258 env->fsr = _tmp & 0x3fcfc1c3ffULL; \
259 } while (0)
260#else
261#define GET_FSR32(env) (env->fsr)
262#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
263 env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \
264 } while (0)
265#endif
266
267CPUSPARCState *cpu_sparc_init(void);
268int cpu_sparc_exec(CPUSPARCState *s);
269int cpu_sparc_close(CPUSPARCState *s);
270int sparc_find_by_name (const unsigned char *name, const sparc_def_t **def);
271void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
272 ...));
273int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def,
274 unsigned int cpu);
275
276#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
277 (env->psref? PSR_EF : 0) | \
278 (env->psrpil << 8) | \
279 (env->psrs? PSR_S : 0) | \
280 (env->psrps? PSR_PS : 0) | \
281 (env->psret? PSR_ET : 0) | env->cwp)
282
283#ifndef NO_CPU_IO_DEFS
284void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
285#endif
286
287#define PUT_PSR(env, val) do { int _tmp = val; \
288 env->psr = _tmp & PSR_ICC; \
289 env->psref = (_tmp & PSR_EF)? 1 : 0; \
290 env->psrpil = (_tmp & PSR_PIL) >> 8; \
291 env->psrs = (_tmp & PSR_S)? 1 : 0; \
292 env->psrps = (_tmp & PSR_PS)? 1 : 0; \
293 env->psret = (_tmp & PSR_ET)? 1 : 0; \
294 cpu_set_cwp(env, _tmp & PSR_CWP); \
295 } while (0)
296
297#ifdef TARGET_SPARC64
298#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
299#define PUT_CCR(env, val) do { int _tmp = val; \
300 env->xcc = (_tmp >> 4) << 20; \
301 env->psr = (_tmp & 0xf) << 20; \
302 } while (0)
303#define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
304#define PUT_CWP64(env, val) \
305 cpu_set_cwp(env, NWINDOWS - 1 - ((val) & (NWINDOWS - 1)))
306
307#endif
308
309int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
310void raise_exception(int tt);
311void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
312 int is_asi);
313void do_tick_set_count(void *opaque, uint64_t count);
314uint64_t do_tick_get_count(void *opaque);
315void do_tick_set_limit(void *opaque, uint64_t limit);
316void cpu_check_irqs(CPUSPARCState *env);
317
318#define CPUState CPUSPARCState
319#define cpu_init cpu_sparc_init
320#define cpu_exec cpu_sparc_exec
321#define cpu_gen_code cpu_sparc_gen_code
322#define cpu_signal_handler cpu_sparc_signal_handler
323#define cpu_list sparc_cpu_list
324
325/* MMU modes definitions */
326#define MMU_MODE0_SUFFIX _kernel
327#define MMU_MODE1_SUFFIX _user
328#define MMU_USER_IDX 1
329static inline int cpu_mmu_index (CPUState *env)
330{
331 return env->psrs == 0 ? 1 : 0;
332}
333
334#include "cpu-all.h"
335
336#endif
Empty description
This page took 0.023916 seconds and 4 git commands to generate.