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	1	/*
	2	* PPC emulation cpu definitions for qemu.
	3	*
	4	* Copyright (c) 2003 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#if !defined (__CPU_PPC_H__)
	21	#define __CPU_PPC_H__
	22
	23	#define TARGET_LONG_BITS 32
	24
	25	#include "cpu-defs.h"
	26
	27	//#define USE_OPEN_FIRMWARE
	28
	29	/* Sign extend constants */
	30	/* 8 to 32 bits */
	31	static inline int32_t s_ext8 (uint8_t value)
	32	{
	33	int8_t *tmp = &value;
	34
	35	return *tmp;
	36	}
	37
	38	/* 16 to 32 bits */
	39	static inline int32_t s_ext16 (uint16_t value)
	40	{
	41	int16_t *tmp = &value;
	42
	43	return *tmp;
	44	}
	45
	46	/* 24 to 32 bits */
	47	static inline int32_t s_ext24 (uint32_t value)
	48	{
	49	uint16_t utmp = (value >> 8) & 0xFFFF;
	50	int16_t *tmp = &utmp;
	51
	52	return (*tmp << 8) \| (value & 0xFF);
	53	}
	54
	55	#include "config.h"
	56	#include <setjmp.h>
	57
	58	/* Instruction types */
	59	enum {
	60	PPC_NONE = 0x0000,
	61	PPC_INTEGER = 0x0001, /* CPU has integer operations instructions */
	62	PPC_FLOAT = 0x0002, /* CPU has floating point operations instructions */
	63	PPC_FLOW = 0x0004, /* CPU has flow control instructions */
	64	PPC_MEM = 0x0008, /* CPU has virtual memory instructions */
	65	PPC_RES = 0x0010, /* CPU has ld/st with reservation instructions */
	66	PPC_CACHE = 0x0020, /* CPU has cache control instructions */
	67	PPC_MISC = 0x0040, /* CPU has spr/msr access instructions */
	68	PPC_EXTERN = 0x0080, /* CPU has external control instructions */
	69	PPC_SEGMENT = 0x0100, /* CPU has memory segment instructions */
	70	PPC_CACHE_OPT= 0x0200,
	71	PPC_FLOAT_OPT= 0x0400,
	72	PPC_MEM_OPT = 0x0800,
	73	};
	74
	75	#define PPC_COMMON (PPC_INTEGER \| PPC_FLOAT \| PPC_FLOW \| PPC_MEM \| \
	76	PPC_RES \| PPC_CACHE \| PPC_MISC \| PPC_SEGMENT)
	77	/* PPC 604 */
	78	#define PPC_604 (PPC_INTEGER \| PPC_FLOAT \| PPC_FLOW \| PPC_MEM \| \
	79	PPC_RES \| PPC_CACHE \| PPC_MISC \| PPC_EXTERN \| PPC_SEGMENT \
	80	PPC_MEM_OPT)
	81	/* PPC 740/745/750/755 (aka G3) has external access instructions */
	82	#define PPC_750 (PPC_INTEGER \| PPC_FLOAT \| PPC_FLOW \| PPC_MEM \| \
	83	PPC_RES \| PPC_CACHE \| PPC_MISC \| PPC_EXTERN \| PPC_SEGMENT)
	84
	85	typedef struct ppc_tb_t ppc_tb_t;
	86
	87	/* Supervisor mode registers */
	88	/* Machine state register */
	89	#define MSR_POW 18
	90	#define MSR_ILE 16
	91	#define MSR_EE 15
	92	#define MSR_PR 14
	93	#define MSR_FP 13
	94	#define MSR_ME 12
	95	#define MSR_FE0 11
	96	#define MSR_SE 10
	97	#define MSR_BE 9
	98	#define MSR_FE1 8
	99	#define MSR_IP 6
	100	#define MSR_IR 5
	101	#define MSR_DR 4
	102	#define MSR_RI 1
	103	#define MSR_LE 0
	104	#define msr_pow env->msr[MSR_POW]
	105	#define msr_ile env->msr[MSR_ILE]
	106	#define msr_ee env->msr[MSR_EE]
	107	#define msr_pr env->msr[MSR_PR]
	108	#define msr_fp env->msr[MSR_FP]
	109	#define msr_me env->msr[MSR_ME]
	110	#define msr_fe0 env->msr[MSR_FE0]
	111	#define msr_se env->msr[MSR_SE]
	112	#define msr_be env->msr[MSR_BE]
	113	#define msr_fe1 env->msr[MSR_FE1]
	114	#define msr_ip env->msr[MSR_IP]
	115	#define msr_ir env->msr[MSR_IR]
	116	#define msr_dr env->msr[MSR_DR]
	117	#define msr_ri env->msr[MSR_RI]
	118	#define msr_le env->msr[MSR_LE]
	119
	120	/* Segment registers */
	121	typedef struct CPUPPCState {
	122	/* general purpose registers */
	123	uint32_t gpr[32];
	124	/* floating point registers */
	125	double fpr[32];
	126	/* segment registers */
	127	uint32_t sdr1;
	128	uint32_t sr[16];
	129	/* XER */
	130	uint8_t xer[4];
	131	/* Reservation address */
	132	uint32_t reserve;
	133	/* machine state register */
	134	uint8_t msr[32];
	135	/* condition register */
	136	uint8_t crf[8];
	137	/* floating point status and control register */
	138	uint8_t fpscr[8];
	139	uint32_t nip;
	140	/* special purpose registers */
	141	uint32_t lr;
	142	uint32_t ctr;
	143	/* BATs */
	144	uint32_t DBAT[2][8];
	145	uint32_t IBAT[2][8];
	146	/* all others */
	147	uint32_t spr[1024];
	148	/* qemu dedicated */
	149	/* temporary float registers */
	150	double ft0;
	151	double ft1;
	152	double ft2;
	153	int interrupt_request;
	154	jmp_buf jmp_env;
	155	int exception_index;
	156	int error_code;
	157	int access_type; /* when a memory exception occurs, the access
	158	type is stored here */
	159	int user_mode_only; /* user mode only simulation */
	160	struct TranslationBlock current_tb; / currently executing TB */
	161	/* soft mmu support */
	162	/* in order to avoid passing too many arguments to the memory
	163	write helpers, we store some rarely used information in the CPU
	164	context) */
	165	unsigned long mem_write_pc; /* host pc at which the memory was
	166	written */
	167	unsigned long mem_write_vaddr; /* target virtual addr at which the
	168	memory was written */
	169	/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
	170	CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
	171	CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
	172
	173	/* ice debug support */
	174	uint32_t breakpoints[MAX_BREAKPOINTS];
	175	int nb_breakpoints;
	176	int singlestep_enabled; /* XXX: should use CPU single step mode instead */
	177
	178	/* Time base and decrementer */
	179	ppc_tb_t *tb_env;
	180
	181	/* Power management */
	182	int power_mode;
	183
	184	/* user data */
	185	void *opaque;
	186	} CPUPPCState;
	187
	188	CPUPPCState *cpu_ppc_init(void);
	189	int cpu_ppc_exec(CPUPPCState *s);
	190	void cpu_ppc_close(CPUPPCState *s);
	191	/* you can call this signal handler from your SIGBUS and SIGSEGV
	192	signal handlers to inform the virtual CPU of exceptions. non zero
	193	is returned if the signal was handled by the virtual CPU. */
	194	struct siginfo;
	195	int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
	196	void *puc);
	197
	198	void do_interrupt (CPUPPCState *env);
	199	void cpu_loop_exit(void);
	200
	201	void cpu_ppc_dump_state(CPUPPCState env, FILE f, int flags);
	202	void dump_stack (CPUPPCState *env);
	203
	204	uint32_t _load_xer (CPUPPCState *env);
	205	void _store_xer (CPUPPCState *env, uint32_t value);
	206	uint32_t _load_msr (CPUPPCState *env);
	207	void _store_msr (CPUPPCState *env, uint32_t value);
	208
	209	int cpu_ppc_register (CPUPPCState *env, uint32_t pvr);
	210
	211	/* Time-base and decrementer management */
	212	#ifndef NO_CPU_IO_DEFS
	213	uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
	214	uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
	215	void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
	216	void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
	217	uint32_t cpu_ppc_load_decr (CPUPPCState *env);
	218	void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
	219	#endif
	220
	221	#define TARGET_PAGE_BITS 12
	222	#include "cpu-all.h"
	223
	224	#define ugpr(n) (env->gpr[n])
	225	#define fprd(n) (env->fpr[n])
	226	#define fprs(n) ((float)env->fpr[n])
	227	#define fpru(n) ((uint32_t)env->fpr[n])
	228	#define fpri(n) ((int32_t)env->fpr[n])
	229
	230	#define SPR_ENCODE(sprn) \
	231	(((sprn) >> 5) \| (((sprn) & 0x1F) << 5))
	232
	233	/* User mode SPR */
	234	#define spr(n) env->spr[n]
	235	#define XER_SO 31
	236	#define XER_OV 30
	237	#define XER_CA 29
	238	#define XER_BC 0
	239	#define xer_so env->xer[3]
	240	#define xer_ov env->xer[2]
	241	#define xer_ca env->xer[1]
	242	#define xer_bc env->xer[0]
	243
	244	#define MQ SPR_ENCODE(0)
	245	#define XER SPR_ENCODE(1)
	246	#define RTCUR SPR_ENCODE(4)
	247	#define RTCLR SPR_ENCODE(5)
	248	#define LR SPR_ENCODE(8)
	249	#define CTR SPR_ENCODE(9)
	250	/* VEA mode SPR */
	251	#define V_TBL SPR_ENCODE(268)
	252	#define V_TBU SPR_ENCODE(269)
	253	/* supervisor mode SPR */
	254	#define DSISR SPR_ENCODE(18)
	255	#define DAR SPR_ENCODE(19)
	256	#define RTCUW SPR_ENCODE(20)
	257	#define RTCLW SPR_ENCODE(21)
	258	#define DECR SPR_ENCODE(22)
	259	#define SDR1 SPR_ENCODE(25)
	260	#define SRR0 SPR_ENCODE(26)
	261	#define SRR1 SPR_ENCODE(27)
	262	#define SPRG0 SPR_ENCODE(272)
	263	#define SPRG1 SPR_ENCODE(273)
	264	#define SPRG2 SPR_ENCODE(274)
	265	#define SPRG3 SPR_ENCODE(275)
	266	#define SPRG4 SPR_ENCODE(276)
	267	#define SPRG5 SPR_ENCODE(277)
	268	#define SPRG6 SPR_ENCODE(278)
	269	#define SPRG7 SPR_ENCODE(279)
	270	#define ASR SPR_ENCODE(280)
	271	#define EAR SPR_ENCODE(282)
	272	#define O_TBL SPR_ENCODE(284)
	273	#define O_TBU SPR_ENCODE(285)
	274	#define PVR SPR_ENCODE(287)
	275	#define IBAT0U SPR_ENCODE(528)
	276	#define IBAT0L SPR_ENCODE(529)
	277	#define IBAT1U SPR_ENCODE(530)
	278	#define IBAT1L SPR_ENCODE(531)
	279	#define IBAT2U SPR_ENCODE(532)
	280	#define IBAT2L SPR_ENCODE(533)
	281	#define IBAT3U SPR_ENCODE(534)
	282	#define IBAT3L SPR_ENCODE(535)
	283	#define DBAT0U SPR_ENCODE(536)
	284	#define DBAT0L SPR_ENCODE(537)
	285	#define DBAT1U SPR_ENCODE(538)
	286	#define DBAT1L SPR_ENCODE(539)
	287	#define DBAT2U SPR_ENCODE(540)
	288	#define DBAT2L SPR_ENCODE(541)
	289	#define DBAT3U SPR_ENCODE(542)
	290	#define DBAT3L SPR_ENCODE(543)
	291	#define IBAT4U SPR_ENCODE(560)
	292	#define IBAT4L SPR_ENCODE(561)
	293	#define IBAT5U SPR_ENCODE(562)
	294	#define IBAT5L SPR_ENCODE(563)
	295	#define IBAT6U SPR_ENCODE(564)
	296	#define IBAT6L SPR_ENCODE(565)
	297	#define IBAT7U SPR_ENCODE(566)
	298	#define IBAT7L SPR_ENCODE(567)
	299	#define DBAT4U SPR_ENCODE(568)
	300	#define DBAT4L SPR_ENCODE(569)
	301	#define DBAT5U SPR_ENCODE(570)
	302	#define DBAT5L SPR_ENCODE(571)
	303	#define DBAT6U SPR_ENCODE(572)
	304	#define DBAT6L SPR_ENCODE(573)
	305	#define DBAT7U SPR_ENCODE(574)
	306	#define DBAT7L SPR_ENCODE(575)
	307	#define UMMCR0 SPR_ENCODE(936)
	308	#define UPMC1 SPR_ENCODE(937)
	309	#define UPMC2 SPR_ENCODE(938)
	310	#define USIA SPR_ENCODE(939)
	311	#define UMMCR1 SPR_ENCODE(940)
	312	#define UPMC3 SPR_ENCODE(941)
	313	#define UPMC4 SPR_ENCODE(942)
	314	#define MMCR0 SPR_ENCODE(952)
	315	#define PMC1 SPR_ENCODE(953)
	316	#define PMC2 SPR_ENCODE(954)
	317	#define SIA SPR_ENCODE(955)
	318	#define MMCR1 SPR_ENCODE(956)
	319	#define PMC3 SPR_ENCODE(957)
	320	#define PMC4 SPR_ENCODE(958)
	321	#define SDA SPR_ENCODE(959)
	322	#define DMISS SPR_ENCODE(976)
	323	#define DCMP SPR_ENCODE(977)
	324	#define DHASH1 SPR_ENCODE(978)
	325	#define DHASH2 SPR_ENCODE(979)
	326	#define IMISS SPR_ENCODE(980)
	327	#define ICMP SPR_ENCODE(981)
	328	#define RPA SPR_ENCODE(982)
	329	#define TCR SPR_ENCODE(984)
	330	#define IBR SPR_ENCODE(986)
	331	#define ESASRR SPR_ENCODE(987)
	332	#define SEBR SPR_ENCODE(990)
	333	#define SER SPR_ENCODE(991)
	334	#define HID0 SPR_ENCODE(1008)
	335	#define HID1 SPR_ENCODE(1009)
	336	#define IABR SPR_ENCODE(1010)
	337	#define HID2 SPR_ENCODE(1011)
	338	#define DABR SPR_ENCODE(1013)
	339	#define L2PM SPR_ENCODE(1016)
	340	#define L2CR SPR_ENCODE(1017)
	341	#define ICTC SPR_ENCODE(1019)
	342	#define THRM1 SPR_ENCODE(1020)
	343	#define THRM2 SPR_ENCODE(1021)
	344	#define THRM3 SPR_ENCODE(1022)
	345	#define SP SPR_ENCODE(1021)
	346	#define LP SPR_ENCODE(1022)
	347	#define DABR_MASK 0xFFFFFFF8
	348	#define FPECR SPR_ENCODE(1022)
	349	#define PIR SPR_ENCODE(1023)
	350
	351	/* Memory access type :
	352	* may be needed for precise access rights control and precise exceptions.
	353	*/
	354	enum {
	355	/* 1 bit to define user level / supervisor access */
	356	ACCESS_USER = 0x00,
	357	ACCESS_SUPER = 0x01,
	358	/* Type of instruction that generated the access */
	359	ACCESS_CODE = 0x10, /* Code fetch access */
	360	ACCESS_INT = 0x20, /* Integer load/store access */
	361	ACCESS_FLOAT = 0x30, /* floating point load/store access */
	362	ACCESS_RES = 0x40, /* load/store with reservation */
	363	ACCESS_EXT = 0x50, /* external access */
	364	ACCESS_CACHE = 0x60, /* Cache manipulation */
	365	};
	366
	367	/*****************************************************************************/
	368	/* Exceptions */
	369	enum {
	370	EXCP_NONE = -1,
	371	/* PPC hardware exceptions : exception vector / 0x100 */
	372	EXCP_RESET = 0x01, /* System reset */
	373	EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */
	374	EXCP_DSI = 0x03, /* Impossible memory access */
	375	EXCP_ISI = 0x04, /* Impossible instruction fetch */
	376	EXCP_EXTERNAL = 0x05, /* External interruption */
	377	EXCP_ALIGN = 0x06, /* Alignment exception */
	378	EXCP_PROGRAM = 0x07, /* Program exception */
	379	EXCP_NO_FP = 0x08, /* No floating point */
	380	EXCP_DECR = 0x09, /* Decrementer exception */
	381	EXCP_RESA = 0x0A, /* Implementation specific */
	382	EXCP_RESB = 0x0B, /* Implementation specific */
	383	EXCP_SYSCALL = 0x0C, /* System call */
	384	EXCP_TRACE = 0x0D, /* Trace exception (optional) */
	385	EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */
	386	/* MPC740/745/750 & IBM 750 */
	387	EXCP_PERF = 0x0F, /* Performance monitor */
	388	EXCP_IABR = 0x13, /* Instruction address breakpoint */
	389	EXCP_SMI = 0x14, /* System management interrupt */
	390	EXCP_THRM = 0x15, /* Thermal management interrupt */
	391	/* MPC755 */
	392	EXCP_TLBMISS = 0x10, /* Instruction TLB miss */
	393	EXCP_TLBMISS_DL = 0x11, /* Data TLB miss for load */
	394	EXCP_TLBMISS_DS = 0x12, /* Data TLB miss for store */
	395	EXCP_PPC_MAX = 0x16,
	396	/* Qemu exception */
	397	EXCP_OFCALL = 0x20, /* Call open-firmware emulator */
	398	EXCP_RTASCALL = 0x21, /* Call RTAS emulator */
	399	/* Special cases where we want to stop translation */
	400	EXCP_MTMSR = 0x104, /* mtmsr instruction: */
	401	/* may change privilege level */
	402	EXCP_BRANCH = 0x108, /* branch instruction */
	403	EXCP_RFI = 0x10C, /* return from interrupt */
	404	EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
	405	};
	406	/* Error codes */
	407	enum {
	408	/* Exception subtypes for EXCP_DSI */
	409	EXCP_DSI_TRANSLATE = 0x01, /* Data address can't be translated */
	410	EXCP_DSI_NOTSUP = 0x02, /* Access type not supported */
	411	EXCP_DSI_PROT = 0x03, /* Memory protection violation */
	412	EXCP_DSI_EXTERNAL = 0x04, /* External access disabled */
	413	EXCP_DSI_DABR = 0x05, /* Data address breakpoint */
	414	/* flags for EXCP_DSI */
	415	EXCP_DSI_DIRECT = 0x10,
	416	EXCP_DSI_STORE = 0x20,
	417	EXCP_DSI_ECXW = 0x40,
	418	/* Exception subtypes for EXCP_ISI */
	419	EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */
	420	EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */
	421	EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */
	422	EXCP_ISI_PROT = 0x04, /* Memory protection violation */
	423	EXCP_ISI_DIRECT = 0x05, /* Trying to fetch from *
	424	* a direct store segment */
	425	/* Exception subtypes for EXCP_ALIGN */
	426	EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
	427	EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
	428	EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
	429	EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
	430	EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
	431	EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
	432	/* Exception subtypes for EXCP_PROGRAM */
	433	/* FP exceptions */
	434	EXCP_FP = 0x10,
	435	EXCP_FP_OX = 0x01, /* FP overflow */
	436	EXCP_FP_UX = 0x02, /* FP underflow */
	437	EXCP_FP_ZX = 0x03, /* FP divide by zero */
	438	EXCP_FP_XX = 0x04, /* FP inexact */
	439	EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
	440	EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */
	441	EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
	442	EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
	443	EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
	444	EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
	445	EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
	446	EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
	447	EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
	448	/* Invalid instruction */
	449	EXCP_INVAL = 0x20,
	450	EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
	451	EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
	452	EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
	453	EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
	454	/* Privileged instruction */
	455	EXCP_PRIV = 0x30,
	456	EXCP_PRIV_OPC = 0x01,
	457	EXCP_PRIV_REG = 0x02,
	458	/* Trap */
	459	EXCP_TRAP = 0x40,
	460	};
	461
	462	/*****************************************************************************/
	463
	464	#endif /* !defined (__CPU_PPC_H__) */