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target/s390x: Diagnose specification exception for atomics
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1/*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23#ifndef S390X_CPU_H
24#define S390X_CPU_H
25
26#include "qemu-common.h"
27#include "cpu-qom.h"
28
29#define TARGET_LONG_BITS 64
30
31#define ELF_MACHINE_UNAME "S390X"
32
33#define CPUArchState struct CPUS390XState
34
35#include "exec/cpu-defs.h"
36#define TARGET_PAGE_BITS 12
37
38#define TARGET_PHYS_ADDR_SPACE_BITS 64
39#define TARGET_VIRT_ADDR_SPACE_BITS 64
40
41#include "exec/cpu-all.h"
42
43#include "fpu/softfloat.h"
44
45#define NB_MMU_MODES 3
46#define TARGET_INSN_START_EXTRA_WORDS 1
47
48#define MMU_MODE0_SUFFIX _primary
49#define MMU_MODE1_SUFFIX _secondary
50#define MMU_MODE2_SUFFIX _home
51
52#define MMU_USER_IDX 0
53
54#define MAX_EXT_QUEUE 16
55#define MAX_IO_QUEUE 16
56#define MAX_MCHK_QUEUE 16
57
58#define PSW_MCHK_MASK 0x0004000000000000
59#define PSW_IO_MASK 0x0200000000000000
60
61typedef struct PSW {
62 uint64_t mask;
63 uint64_t addr;
64} PSW;
65
66typedef struct ExtQueue {
67 uint32_t code;
68 uint32_t param;
69 uint32_t param64;
70} ExtQueue;
71
72typedef struct IOIntQueue {
73 uint16_t id;
74 uint16_t nr;
75 uint32_t parm;
76 uint32_t word;
77} IOIntQueue;
78
79typedef struct MchkQueue {
80 uint16_t type;
81} MchkQueue;
82
83typedef struct CPUS390XState {
84 uint64_t regs[16]; /* GP registers */
85 /*
86 * The floating point registers are part of the vector registers.
87 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
88 */
89 CPU_DoubleU vregs[32][2]; /* vector registers */
90 uint32_t aregs[16]; /* access registers */
91
92 uint32_t fpc; /* floating-point control register */
93 uint32_t cc_op;
94
95 float_status fpu_status; /* passed to softfloat lib */
96
97 /* The low part of a 128-bit return, or remainder of a divide. */
98 uint64_t retxl;
99
100 PSW psw;
101
102 uint64_t cc_src;
103 uint64_t cc_dst;
104 uint64_t cc_vr;
105
106 uint64_t __excp_addr;
107 uint64_t psa;
108
109 uint32_t int_pgm_code;
110 uint32_t int_pgm_ilen;
111
112 uint32_t int_svc_code;
113 uint32_t int_svc_ilen;
114
115 uint64_t per_address;
116 uint16_t per_perc_atmid;
117
118 uint64_t cregs[16]; /* control registers */
119
120 ExtQueue ext_queue[MAX_EXT_QUEUE];
121 IOIntQueue io_queue[MAX_IO_QUEUE][8];
122 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
123
124 int pending_int;
125 int ext_index;
126 int io_index[8];
127 int mchk_index;
128
129 uint64_t ckc;
130 uint64_t cputm;
131 uint32_t todpr;
132
133 uint64_t pfault_token;
134 uint64_t pfault_compare;
135 uint64_t pfault_select;
136
137 uint64_t gbea;
138 uint64_t pp;
139
140 uint8_t riccb[64];
141
142 /* Fields up to this point are cleared by a CPU reset */
143 struct {} end_reset_fields;
144
145 CPU_COMMON
146
147 uint32_t cpu_num;
148 uint32_t machine_type;
149
150 uint64_t tod_offset;
151 uint64_t tod_basetime;
152 QEMUTimer *tod_timer;
153
154 QEMUTimer *cpu_timer;
155
156 /*
157 * The cpu state represents the logical state of a cpu. In contrast to other
158 * architectures, there is a difference between a halt and a stop on s390.
159 * If all cpus are either stopped (including check stop) or in the disabled
160 * wait state, the vm can be shut down.
161 */
162#define CPU_STATE_UNINITIALIZED 0x00
163#define CPU_STATE_STOPPED 0x01
164#define CPU_STATE_CHECK_STOP 0x02
165#define CPU_STATE_OPERATING 0x03
166#define CPU_STATE_LOAD 0x04
167 uint8_t cpu_state;
168
169 /* currently processed sigp order */
170 uint8_t sigp_order;
171
172} CPUS390XState;
173
174static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
175{
176 return &cs->vregs[nr][0];
177}
178
179/**
180 * S390CPU:
181 * @env: #CPUS390XState.
182 *
183 * An S/390 CPU.
184 */
185struct S390CPU {
186 /*< private >*/
187 CPUState parent_obj;
188 /*< public >*/
189
190 CPUS390XState env;
191 int64_t id;
192 S390CPUModel *model;
193 /* needed for live migration */
194 void *irqstate;
195 uint32_t irqstate_saved_size;
196};
197
198static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
199{
200 return container_of(env, S390CPU, env);
201}
202
203#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
204
205#define ENV_OFFSET offsetof(S390CPU, env)
206
207#ifndef CONFIG_USER_ONLY
208extern const struct VMStateDescription vmstate_s390_cpu;
209#endif
210
211void s390_cpu_do_interrupt(CPUState *cpu);
212bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
213void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
214 int flags);
215int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
216 int cpuid, void *opaque);
217
218hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
219hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
220int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
221int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
222void s390_cpu_gdb_init(CPUState *cs);
223void s390x_cpu_debug_excp_handler(CPUState *cs);
224
225#include "sysemu/kvm.h"
226
227/* distinguish between 24 bit and 31 bit addressing */
228#define HIGH_ORDER_BIT 0x80000000
229
230/* Interrupt Codes */
231/* Program Interrupts */
232#define PGM_OPERATION 0x0001
233#define PGM_PRIVILEGED 0x0002
234#define PGM_EXECUTE 0x0003
235#define PGM_PROTECTION 0x0004
236#define PGM_ADDRESSING 0x0005
237#define PGM_SPECIFICATION 0x0006
238#define PGM_DATA 0x0007
239#define PGM_FIXPT_OVERFLOW 0x0008
240#define PGM_FIXPT_DIVIDE 0x0009
241#define PGM_DEC_OVERFLOW 0x000a
242#define PGM_DEC_DIVIDE 0x000b
243#define PGM_HFP_EXP_OVERFLOW 0x000c
244#define PGM_HFP_EXP_UNDERFLOW 0x000d
245#define PGM_HFP_SIGNIFICANCE 0x000e
246#define PGM_HFP_DIVIDE 0x000f
247#define PGM_SEGMENT_TRANS 0x0010
248#define PGM_PAGE_TRANS 0x0011
249#define PGM_TRANS_SPEC 0x0012
250#define PGM_SPECIAL_OP 0x0013
251#define PGM_OPERAND 0x0015
252#define PGM_TRACE_TABLE 0x0016
253#define PGM_SPACE_SWITCH 0x001c
254#define PGM_HFP_SQRT 0x001d
255#define PGM_PC_TRANS_SPEC 0x001f
256#define PGM_AFX_TRANS 0x0020
257#define PGM_ASX_TRANS 0x0021
258#define PGM_LX_TRANS 0x0022
259#define PGM_EX_TRANS 0x0023
260#define PGM_PRIM_AUTH 0x0024
261#define PGM_SEC_AUTH 0x0025
262#define PGM_ALET_SPEC 0x0028
263#define PGM_ALEN_SPEC 0x0029
264#define PGM_ALE_SEQ 0x002a
265#define PGM_ASTE_VALID 0x002b
266#define PGM_ASTE_SEQ 0x002c
267#define PGM_EXT_AUTH 0x002d
268#define PGM_STACK_FULL 0x0030
269#define PGM_STACK_EMPTY 0x0031
270#define PGM_STACK_SPEC 0x0032
271#define PGM_STACK_TYPE 0x0033
272#define PGM_STACK_OP 0x0034
273#define PGM_ASCE_TYPE 0x0038
274#define PGM_REG_FIRST_TRANS 0x0039
275#define PGM_REG_SEC_TRANS 0x003a
276#define PGM_REG_THIRD_TRANS 0x003b
277#define PGM_MONITOR 0x0040
278#define PGM_PER 0x0080
279#define PGM_CRYPTO 0x0119
280
281/* External Interrupts */
282#define EXT_INTERRUPT_KEY 0x0040
283#define EXT_CLOCK_COMP 0x1004
284#define EXT_CPU_TIMER 0x1005
285#define EXT_MALFUNCTION 0x1200
286#define EXT_EMERGENCY 0x1201
287#define EXT_EXTERNAL_CALL 0x1202
288#define EXT_ETR 0x1406
289#define EXT_SERVICE 0x2401
290#define EXT_VIRTIO 0x2603
291
292/* PSW defines */
293#undef PSW_MASK_PER
294#undef PSW_MASK_DAT
295#undef PSW_MASK_IO
296#undef PSW_MASK_EXT
297#undef PSW_MASK_KEY
298#undef PSW_SHIFT_KEY
299#undef PSW_MASK_MCHECK
300#undef PSW_MASK_WAIT
301#undef PSW_MASK_PSTATE
302#undef PSW_MASK_ASC
303#undef PSW_MASK_CC
304#undef PSW_MASK_PM
305#undef PSW_MASK_64
306#undef PSW_MASK_32
307#undef PSW_MASK_ESA_ADDR
308
309#define PSW_MASK_PER 0x4000000000000000ULL
310#define PSW_MASK_DAT 0x0400000000000000ULL
311#define PSW_MASK_IO 0x0200000000000000ULL
312#define PSW_MASK_EXT 0x0100000000000000ULL
313#define PSW_MASK_KEY 0x00F0000000000000ULL
314#define PSW_SHIFT_KEY 56
315#define PSW_MASK_MCHECK 0x0004000000000000ULL
316#define PSW_MASK_WAIT 0x0002000000000000ULL
317#define PSW_MASK_PSTATE 0x0001000000000000ULL
318#define PSW_MASK_ASC 0x0000C00000000000ULL
319#define PSW_MASK_CC 0x0000300000000000ULL
320#define PSW_MASK_PM 0x00000F0000000000ULL
321#define PSW_MASK_64 0x0000000100000000ULL
322#define PSW_MASK_32 0x0000000080000000ULL
323#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
324
325#undef PSW_ASC_PRIMARY
326#undef PSW_ASC_ACCREG
327#undef PSW_ASC_SECONDARY
328#undef PSW_ASC_HOME
329
330#define PSW_ASC_PRIMARY 0x0000000000000000ULL
331#define PSW_ASC_ACCREG 0x0000400000000000ULL
332#define PSW_ASC_SECONDARY 0x0000800000000000ULL
333#define PSW_ASC_HOME 0x0000C00000000000ULL
334
335/* tb flags */
336
337#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
338#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
339#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
340#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
341#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
342#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
343#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
344#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
345#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
346#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
347#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
348#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
349#define FLAG_MASK_32 0x00001000
350
351/* Control register 0 bits */
352#define CR0_LOWPROT 0x0000000010000000ULL
353#define CR0_EDAT 0x0000000000800000ULL
354
355/* MMU */
356#define MMU_PRIMARY_IDX 0
357#define MMU_SECONDARY_IDX 1
358#define MMU_HOME_IDX 2
359
360static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
361{
362 switch (env->psw.mask & PSW_MASK_ASC) {
363 case PSW_ASC_PRIMARY:
364 return MMU_PRIMARY_IDX;
365 case PSW_ASC_SECONDARY:
366 return MMU_SECONDARY_IDX;
367 case PSW_ASC_HOME:
368 return MMU_HOME_IDX;
369 case PSW_ASC_ACCREG:
370 /* Fallthrough: access register mode is not yet supported */
371 default:
372 abort();
373 }
374}
375
376static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
377{
378 switch (mmu_idx) {
379 case MMU_PRIMARY_IDX:
380 return PSW_ASC_PRIMARY;
381 case MMU_SECONDARY_IDX:
382 return PSW_ASC_SECONDARY;
383 case MMU_HOME_IDX:
384 return PSW_ASC_HOME;
385 default:
386 abort();
387 }
388}
389
390static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
391 target_ulong *cs_base, uint32_t *flags)
392{
393 *pc = env->psw.addr;
394 *cs_base = 0;
395 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
396 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
397}
398
399#define MAX_ILEN 6
400
401/* While the PoO talks about ILC (a number between 1-3) what is actually
402 stored in LowCore is shifted left one bit (an even between 2-6). As
403 this is the actual length of the insn and therefore more useful, that
404 is what we want to pass around and manipulate. To make sure that we
405 have applied this distinction universally, rename the "ILC" to "ILEN". */
406static inline int get_ilen(uint8_t opc)
407{
408 switch (opc >> 6) {
409 case 0:
410 return 2;
411 case 1:
412 case 2:
413 return 4;
414 default:
415 return 6;
416 }
417}
418
419/* PER bits from control register 9 */
420#define PER_CR9_EVENT_BRANCH 0x80000000
421#define PER_CR9_EVENT_IFETCH 0x40000000
422#define PER_CR9_EVENT_STORE 0x20000000
423#define PER_CR9_EVENT_STORE_REAL 0x08000000
424#define PER_CR9_EVENT_NULLIFICATION 0x01000000
425#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
426#define PER_CR9_CONTROL_ALTERATION 0x00200000
427
428/* PER bits from the PER CODE/ATMID/AI in lowcore */
429#define PER_CODE_EVENT_BRANCH 0x8000
430#define PER_CODE_EVENT_IFETCH 0x4000
431#define PER_CODE_EVENT_STORE 0x2000
432#define PER_CODE_EVENT_STORE_REAL 0x0800
433#define PER_CODE_EVENT_NULLIFICATION 0x0100
434
435/* Compute the ATMID field that is stored in the per_perc_atmid lowcore
436 entry when a PER exception is triggered. */
437static inline uint8_t get_per_atmid(CPUS390XState *env)
438{
439 return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) |
440 ( (1 << 6) ) |
441 ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) |
442 ((env->psw.mask & PSW_MASK_DAT)? (1 << 4) : 0) |
443 ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
444 ((env->psw.mask & PSW_ASC_ACCREG)? (1 << 2) : 0);
445}
446
447/* Check if an address is within the PER starting address and the PER
448 ending address. The address range might loop. */
449static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
450{
451 if (env->cregs[10] <= env->cregs[11]) {
452 return env->cregs[10] <= addr && addr <= env->cregs[11];
453 } else {
454 return env->cregs[10] <= addr || addr <= env->cregs[11];
455 }
456}
457
458#ifndef CONFIG_USER_ONLY
459/* In several cases of runtime exceptions, we havn't recorded the true
460 instruction length. Use these codes when raising exceptions in order
461 to re-compute the length by examining the insn in memory. */
462#define ILEN_LATER 0x20
463#define ILEN_LATER_INC 0x21
464void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
465#endif
466
467S390CPU *cpu_s390x_init(const char *cpu_model);
468S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp);
469S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp);
470void s390x_translate_init(void);
471
472/* you can call this signal handler from your SIGBUS and SIGSEGV
473 signal handlers to inform the virtual CPU of exceptions. non zero
474 is returned if the signal was handled by the virtual CPU. */
475int cpu_s390x_signal_handler(int host_signum, void *pinfo,
476 void *puc);
477int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
478 int mmu_idx);
479
480
481#ifndef CONFIG_USER_ONLY
482void do_restart_interrupt(CPUS390XState *env);
483void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
484 MMUAccessType access_type,
485 int mmu_idx, uintptr_t retaddr);
486
487static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
488 uint8_t *ar)
489{
490 hwaddr addr = 0;
491 uint8_t reg;
492
493 reg = ipb >> 28;
494 if (reg > 0) {
495 addr = env->regs[reg];
496 }
497 addr += (ipb >> 16) & 0xfff;
498 if (ar) {
499 *ar = reg;
500 }
501
502 return addr;
503}
504
505/* Base/displacement are at the same locations. */
506#define decode_basedisp_rs decode_basedisp_s
507
508/* helper functions for run_on_cpu() */
509static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
510{
511 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
512
513 scc->cpu_reset(cs);
514}
515static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
516{
517 cpu_reset(cs);
518}
519
520void s390x_tod_timer(void *opaque);
521void s390x_cpu_timer(void *opaque);
522
523int s390_virtio_hypercall(CPUS390XState *env);
524
525#ifdef CONFIG_KVM
526void kvm_s390_service_interrupt(uint32_t parm);
527void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
528void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
529int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
530void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
531int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
532 int len, bool is_write);
533int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
534int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
535#else
536static inline void kvm_s390_service_interrupt(uint32_t parm)
537{
538}
539static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
540{
541 return -ENOSYS;
542}
543static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
544{
545 return -ENOSYS;
546}
547static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
548 void *hostbuf, int len, bool is_write)
549{
550 return -ENOSYS;
551}
552static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
553 uint64_t te_code)
554{
555}
556#endif
557
558static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
559{
560 if (kvm_enabled()) {
561 return kvm_s390_get_clock(tod_high, tod_low);
562 }
563 /* Fixme TCG */
564 *tod_high = 0;
565 *tod_low = 0;
566 return 0;
567}
568
569static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
570{
571 if (kvm_enabled()) {
572 return kvm_s390_set_clock(tod_high, tod_low);
573 }
574 /* Fixme TCG */
575 return 0;
576}
577
578S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
579unsigned int s390_cpu_halt(S390CPU *cpu);
580void s390_cpu_unhalt(S390CPU *cpu);
581unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
582static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
583{
584 return cpu->env.cpu_state;
585}
586
587void gtod_save(QEMUFile *f, void *opaque);
588int gtod_load(QEMUFile *f, void *opaque, int version_id);
589
590void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
591 uint64_t param64);
592
593/* ioinst.c */
594void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1);
595void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1);
596void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1);
597void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
598void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
599void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb);
600void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
601int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
602void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb);
603int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb);
604void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
605 uint32_t ipb);
606void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1);
607void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1);
608void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1);
609
610/* service interrupts are floating therefore we must not pass an cpustate */
611void s390_sclp_extint(uint32_t parm);
612
613#else
614static inline unsigned int s390_cpu_halt(S390CPU *cpu)
615{
616 return 0;
617}
618
619static inline void s390_cpu_unhalt(S390CPU *cpu)
620{
621}
622
623static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
624{
625 return 0;
626}
627#endif
628
629extern void subsystem_reset(void);
630
631#define cpu_init(model) CPU(cpu_s390x_init(model))
632#define cpu_signal_handler cpu_s390x_signal_handler
633
634void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
635#define cpu_list s390_cpu_list
636void s390_cpu_model_register_props(Object *obj);
637void s390_cpu_model_class_register_props(ObjectClass *oc);
638void s390_realize_cpu_model(CPUState *cs, Error **errp);
639ObjectClass *s390_cpu_class_by_name(const char *name);
640
641#define EXCP_EXT 1 /* external interrupt */
642#define EXCP_SVC 2 /* supervisor call (syscall) */
643#define EXCP_PGM 3 /* program interruption */
644#define EXCP_IO 7 /* I/O interrupt */
645#define EXCP_MCHK 8 /* machine check */
646
647#define INTERRUPT_EXT (1 << 0)
648#define INTERRUPT_TOD (1 << 1)
649#define INTERRUPT_CPUTIMER (1 << 2)
650#define INTERRUPT_IO (1 << 3)
651#define INTERRUPT_MCHK (1 << 4)
652
653/* Program Status Word. */
654#define S390_PSWM_REGNUM 0
655#define S390_PSWA_REGNUM 1
656/* General Purpose Registers. */
657#define S390_R0_REGNUM 2
658#define S390_R1_REGNUM 3
659#define S390_R2_REGNUM 4
660#define S390_R3_REGNUM 5
661#define S390_R4_REGNUM 6
662#define S390_R5_REGNUM 7
663#define S390_R6_REGNUM 8
664#define S390_R7_REGNUM 9
665#define S390_R8_REGNUM 10
666#define S390_R9_REGNUM 11
667#define S390_R10_REGNUM 12
668#define S390_R11_REGNUM 13
669#define S390_R12_REGNUM 14
670#define S390_R13_REGNUM 15
671#define S390_R14_REGNUM 16
672#define S390_R15_REGNUM 17
673/* Total Core Registers. */
674#define S390_NUM_CORE_REGS 18
675
676/* CC optimization */
677
678/* Instead of computing the condition codes after each x86 instruction,
679 * QEMU just stores the result (called CC_DST), the type of operation
680 * (called CC_OP) and whatever operands are needed (CC_SRC and possibly
681 * CC_VR). When the condition codes are needed, the condition codes can
682 * be calculated using this information. Condition codes are not generated
683 * if they are only needed for conditional branches.
684 */
685enum cc_op {
686 CC_OP_CONST0 = 0, /* CC is 0 */
687 CC_OP_CONST1, /* CC is 1 */
688 CC_OP_CONST2, /* CC is 2 */
689 CC_OP_CONST3, /* CC is 3 */
690
691 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
692 CC_OP_STATIC, /* CC value is env->cc_op */
693
694 CC_OP_NZ, /* env->cc_dst != 0 */
695 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
696 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
697 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
698 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
699 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
700 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
701
702 CC_OP_ADD_64, /* overflow on add (64bit) */
703 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
704 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
705 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
706 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
707 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
708 CC_OP_ABS_64, /* sign eval on abs (64bit) */
709 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
710
711 CC_OP_ADD_32, /* overflow on add (32bit) */
712 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
713 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
714 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
715 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
716 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
717 CC_OP_ABS_32, /* sign eval on abs (64bit) */
718 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
719
720 CC_OP_COMP_32, /* complement */
721 CC_OP_COMP_64, /* complement */
722
723 CC_OP_TM_32, /* test under mask (32bit) */
724 CC_OP_TM_64, /* test under mask (64bit) */
725
726 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
727 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
728 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
729
730 CC_OP_ICM, /* insert characters under mask */
731 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
732 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
733 CC_OP_FLOGR, /* find leftmost one */
734 CC_OP_MAX
735};
736
737static const char *cc_names[] = {
738 [CC_OP_CONST0] = "CC_OP_CONST0",
739 [CC_OP_CONST1] = "CC_OP_CONST1",
740 [CC_OP_CONST2] = "CC_OP_CONST2",
741 [CC_OP_CONST3] = "CC_OP_CONST3",
742 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
743 [CC_OP_STATIC] = "CC_OP_STATIC",
744 [CC_OP_NZ] = "CC_OP_NZ",
745 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
746 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
747 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
748 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
749 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
750 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
751 [CC_OP_ADD_64] = "CC_OP_ADD_64",
752 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
753 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
754 [CC_OP_SUB_64] = "CC_OP_SUB_64",
755 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
756 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
757 [CC_OP_ABS_64] = "CC_OP_ABS_64",
758 [CC_OP_NABS_64] = "CC_OP_NABS_64",
759 [CC_OP_ADD_32] = "CC_OP_ADD_32",
760 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
761 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
762 [CC_OP_SUB_32] = "CC_OP_SUB_32",
763 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
764 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
765 [CC_OP_ABS_32] = "CC_OP_ABS_32",
766 [CC_OP_NABS_32] = "CC_OP_NABS_32",
767 [CC_OP_COMP_32] = "CC_OP_COMP_32",
768 [CC_OP_COMP_64] = "CC_OP_COMP_64",
769 [CC_OP_TM_32] = "CC_OP_TM_32",
770 [CC_OP_TM_64] = "CC_OP_TM_64",
771 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
772 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
773 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
774 [CC_OP_ICM] = "CC_OP_ICM",
775 [CC_OP_SLA_32] = "CC_OP_SLA_32",
776 [CC_OP_SLA_64] = "CC_OP_SLA_64",
777 [CC_OP_FLOGR] = "CC_OP_FLOGR",
778};
779
780static inline const char *cc_name(int cc_op)
781{
782 return cc_names[cc_op];
783}
784
785static inline void setcc(S390CPU *cpu, uint64_t cc)
786{
787 CPUS390XState *env = &cpu->env;
788
789 env->psw.mask &= ~(3ull << 44);
790 env->psw.mask |= (cc & 3) << 44;
791 env->cc_op = cc;
792}
793
794typedef struct LowCore
795{
796 /* prefix area: defined by architecture */
797 uint32_t ccw1[2]; /* 0x000 */
798 uint32_t ccw2[4]; /* 0x008 */
799 uint8_t pad1[0x80-0x18]; /* 0x018 */
800 uint32_t ext_params; /* 0x080 */
801 uint16_t cpu_addr; /* 0x084 */
802 uint16_t ext_int_code; /* 0x086 */
803 uint16_t svc_ilen; /* 0x088 */
804 uint16_t svc_code; /* 0x08a */
805 uint16_t pgm_ilen; /* 0x08c */
806 uint16_t pgm_code; /* 0x08e */
807 uint32_t data_exc_code; /* 0x090 */
808 uint16_t mon_class_num; /* 0x094 */
809 uint16_t per_perc_atmid; /* 0x096 */
810 uint64_t per_address; /* 0x098 */
811 uint8_t exc_access_id; /* 0x0a0 */
812 uint8_t per_access_id; /* 0x0a1 */
813 uint8_t op_access_id; /* 0x0a2 */
814 uint8_t ar_access_id; /* 0x0a3 */
815 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
816 uint64_t trans_exc_code; /* 0x0a8 */
817 uint64_t monitor_code; /* 0x0b0 */
818 uint16_t subchannel_id; /* 0x0b8 */
819 uint16_t subchannel_nr; /* 0x0ba */
820 uint32_t io_int_parm; /* 0x0bc */
821 uint32_t io_int_word; /* 0x0c0 */
822 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
823 uint32_t stfl_fac_list; /* 0x0c8 */
824 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
825 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
826 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
827 uint32_t external_damage_code; /* 0x0f4 */
828 uint64_t failing_storage_address; /* 0x0f8 */
829 uint8_t pad6[0x110-0x100]; /* 0x100 */
830 uint64_t per_breaking_event_addr; /* 0x110 */
831 uint8_t pad7[0x120-0x118]; /* 0x118 */
832 PSW restart_old_psw; /* 0x120 */
833 PSW external_old_psw; /* 0x130 */
834 PSW svc_old_psw; /* 0x140 */
835 PSW program_old_psw; /* 0x150 */
836 PSW mcck_old_psw; /* 0x160 */
837 PSW io_old_psw; /* 0x170 */
838 uint8_t pad8[0x1a0-0x180]; /* 0x180 */
839 PSW restart_new_psw; /* 0x1a0 */
840 PSW external_new_psw; /* 0x1b0 */
841 PSW svc_new_psw; /* 0x1c0 */
842 PSW program_new_psw; /* 0x1d0 */
843 PSW mcck_new_psw; /* 0x1e0 */
844 PSW io_new_psw; /* 0x1f0 */
845 PSW return_psw; /* 0x200 */
846 uint8_t irb[64]; /* 0x210 */
847 uint64_t sync_enter_timer; /* 0x250 */
848 uint64_t async_enter_timer; /* 0x258 */
849 uint64_t exit_timer; /* 0x260 */
850 uint64_t last_update_timer; /* 0x268 */
851 uint64_t user_timer; /* 0x270 */
852 uint64_t system_timer; /* 0x278 */
853 uint64_t last_update_clock; /* 0x280 */
854 uint64_t steal_clock; /* 0x288 */
855 PSW return_mcck_psw; /* 0x290 */
856 uint8_t pad9[0xc00-0x2a0]; /* 0x2a0 */
857 /* System info area */
858 uint64_t save_area[16]; /* 0xc00 */
859 uint8_t pad10[0xd40-0xc80]; /* 0xc80 */
860 uint64_t kernel_stack; /* 0xd40 */
861 uint64_t thread_info; /* 0xd48 */
862 uint64_t async_stack; /* 0xd50 */
863 uint64_t kernel_asce; /* 0xd58 */
864 uint64_t user_asce; /* 0xd60 */
865 uint64_t panic_stack; /* 0xd68 */
866 uint64_t user_exec_asce; /* 0xd70 */
867 uint8_t pad11[0xdc0-0xd78]; /* 0xd78 */
868
869 /* SMP info area: defined by DJB */
870 uint64_t clock_comparator; /* 0xdc0 */
871 uint64_t ext_call_fast; /* 0xdc8 */
872 uint64_t percpu_offset; /* 0xdd0 */
873 uint64_t current_task; /* 0xdd8 */
874 uint32_t softirq_pending; /* 0xde0 */
875 uint32_t pad_0x0de4; /* 0xde4 */
876 uint64_t int_clock; /* 0xde8 */
877 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
878
879 /* 0xe00 is used as indicator for dump tools */
880 /* whether the kernel died with panic() or not */
881 uint32_t panic_magic; /* 0xe00 */
882
883 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
884
885 /* 64 bit extparam used for pfault, diag 250 etc */
886 uint64_t ext_params2; /* 0x11B8 */
887
888 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
889
890 /* System info area */
891
892 uint64_t floating_pt_save_area[16]; /* 0x1200 */
893 uint64_t gpregs_save_area[16]; /* 0x1280 */
894 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
895 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
896 uint32_t prefixreg_save_area; /* 0x1318 */
897 uint32_t fpt_creg_save_area; /* 0x131c */
898 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
899 uint32_t tod_progreg_save_area; /* 0x1324 */
900 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
901 uint32_t clock_comp_save_area[2]; /* 0x1330 */
902 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
903 uint32_t access_regs_save_area[16]; /* 0x1340 */
904 uint64_t cregs_save_area[16]; /* 0x1380 */
905
906 /* align to the top of the prefix area */
907
908 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
909} QEMU_PACKED LowCore;
910
911/* STSI */
912#define STSI_LEVEL_MASK 0x00000000f0000000ULL
913#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
914#define STSI_LEVEL_1 0x0000000010000000ULL
915#define STSI_LEVEL_2 0x0000000020000000ULL
916#define STSI_LEVEL_3 0x0000000030000000ULL
917#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
918#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
919#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
920#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
921
922/* Basic Machine Configuration */
923struct sysib_111 {
924 uint32_t res1[8];
925 uint8_t manuf[16];
926 uint8_t type[4];
927 uint8_t res2[12];
928 uint8_t model[16];
929 uint8_t sequence[16];
930 uint8_t plant[4];
931 uint8_t res3[156];
932};
933
934/* Basic Machine CPU */
935struct sysib_121 {
936 uint32_t res1[80];
937 uint8_t sequence[16];
938 uint8_t plant[4];
939 uint8_t res2[2];
940 uint16_t cpu_addr;
941 uint8_t res3[152];
942};
943
944/* Basic Machine CPUs */
945struct sysib_122 {
946 uint8_t res1[32];
947 uint32_t capability;
948 uint16_t total_cpus;
949 uint16_t active_cpus;
950 uint16_t standby_cpus;
951 uint16_t reserved_cpus;
952 uint16_t adjustments[2026];
953};
954
955/* LPAR CPU */
956struct sysib_221 {
957 uint32_t res1[80];
958 uint8_t sequence[16];
959 uint8_t plant[4];
960 uint16_t cpu_id;
961 uint16_t cpu_addr;
962 uint8_t res3[152];
963};
964
965/* LPAR CPUs */
966struct sysib_222 {
967 uint32_t res1[32];
968 uint16_t lpar_num;
969 uint8_t res2;
970 uint8_t lcpuc;
971 uint16_t total_cpus;
972 uint16_t conf_cpus;
973 uint16_t standby_cpus;
974 uint16_t reserved_cpus;
975 uint8_t name[8];
976 uint32_t caf;
977 uint8_t res3[16];
978 uint16_t dedicated_cpus;
979 uint16_t shared_cpus;
980 uint8_t res4[180];
981};
982
983/* VM CPUs */
984struct sysib_322 {
985 uint8_t res1[31];
986 uint8_t count;
987 struct {
988 uint8_t res2[4];
989 uint16_t total_cpus;
990 uint16_t conf_cpus;
991 uint16_t standby_cpus;
992 uint16_t reserved_cpus;
993 uint8_t name[8];
994 uint32_t caf;
995 uint8_t cpi[16];
996 uint8_t res5[3];
997 uint8_t ext_name_encoding;
998 uint32_t res3;
999 uint8_t uuid[16];
1000 } vm[8];
1001 uint8_t res4[1504];
1002 uint8_t ext_names[8][256];
1003};
1004
1005/* MMU defines */
1006#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
1007#define _ASCE_SUBSPACE 0x200 /* subspace group control */
1008#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
1009#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
1010#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
1011#define _ASCE_REAL_SPACE 0x20 /* real space control */
1012#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
1013#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
1014#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
1015#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
1016#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
1017#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
1018
1019#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
1020#define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
1021#define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
1022#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
1023#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
1024#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
1025#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
1026#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
1027#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
1028
1029#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
1030#define _SEGMENT_ENTRY_FC 0x400 /* format control */
1031#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
1032#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
1033
1034#define _PAGE_RO 0x200 /* HW read-only bit */
1035#define _PAGE_INVALID 0x400 /* HW invalid bit */
1036#define _PAGE_RES0 0x800 /* bit must be zero */
1037
1038#define SK_C (0x1 << 1)
1039#define SK_R (0x1 << 2)
1040#define SK_F (0x1 << 3)
1041#define SK_ACC_MASK (0xf << 4)
1042
1043/* SIGP order codes */
1044#define SIGP_SENSE 0x01
1045#define SIGP_EXTERNAL_CALL 0x02
1046#define SIGP_EMERGENCY 0x03
1047#define SIGP_START 0x04
1048#define SIGP_STOP 0x05
1049#define SIGP_RESTART 0x06
1050#define SIGP_STOP_STORE_STATUS 0x09
1051#define SIGP_INITIAL_CPU_RESET 0x0b
1052#define SIGP_CPU_RESET 0x0c
1053#define SIGP_SET_PREFIX 0x0d
1054#define SIGP_STORE_STATUS_ADDR 0x0e
1055#define SIGP_SET_ARCH 0x12
1056#define SIGP_STORE_ADTL_STATUS 0x17
1057
1058/* SIGP condition codes */
1059#define SIGP_CC_ORDER_CODE_ACCEPTED 0
1060#define SIGP_CC_STATUS_STORED 1
1061#define SIGP_CC_BUSY 2
1062#define SIGP_CC_NOT_OPERATIONAL 3
1063
1064/* SIGP status bits */
1065#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
1066#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
1067#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1068#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
1069#define SIGP_STAT_STOPPED 0x00000040UL
1070#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
1071#define SIGP_STAT_CHECK_STOP 0x00000010UL
1072#define SIGP_STAT_INOPERATIVE 0x00000004UL
1073#define SIGP_STAT_INVALID_ORDER 0x00000002UL
1074#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
1075
1076/* SIGP SET ARCHITECTURE modes */
1077#define SIGP_MODE_ESA_S390 0
1078#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1079#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1080
1081void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1082int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1083 target_ulong *raddr, int *flags, bool exc);
1084int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1085uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1086 uint64_t vr);
1087void s390_cpu_recompute_watchpoints(CPUState *cs);
1088
1089int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1090 int len, bool is_write);
1091
1092#define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
1093 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1094#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
1095 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1096#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
1097 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1098
1099/* The value of the TOD clock for 1.1.1970. */
1100#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1101
1102/* Converts ns to s390's clock format */
1103static inline uint64_t time2tod(uint64_t ns) {
1104 return (ns << 9) / 125;
1105}
1106
1107/* Converts s390's clock format to ns */
1108static inline uint64_t tod2time(uint64_t t) {
1109 return (t * 125) >> 9;
1110}
1111
1112/* from s390-virtio-ccw */
1113#define MEM_SECTION_SIZE 0x10000000UL
1114#define MAX_AVAIL_SLOTS 32
1115
1116/* fpu_helper.c */
1117uint32_t set_cc_nz_f32(float32 v);
1118uint32_t set_cc_nz_f64(float64 v);
1119uint32_t set_cc_nz_f128(float128 v);
1120
1121/* misc_helper.c */
1122#ifndef CONFIG_USER_ONLY
1123int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1124void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1125#endif
1126void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1127void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1128 uintptr_t retaddr);
1129
1130#ifdef CONFIG_KVM
1131void kvm_s390_io_interrupt(uint16_t subchannel_id,
1132 uint16_t subchannel_nr, uint32_t io_int_parm,
1133 uint32_t io_int_word);
1134void kvm_s390_crw_mchk(void);
1135void kvm_s390_enable_css_support(S390CPU *cpu);
1136int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1137 int vq, bool assign);
1138int kvm_s390_cpu_restart(S390CPU *cpu);
1139int kvm_s390_get_memslot_count(KVMState *s);
1140void kvm_s390_cmma_reset(void);
1141int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1142void kvm_s390_reset_vcpu(S390CPU *cpu);
1143int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1144void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1145int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1146int kvm_s390_get_ri(void);
1147void kvm_s390_crypto_reset(void);
1148#else
1149static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1150 uint16_t subchannel_nr,
1151 uint32_t io_int_parm,
1152 uint32_t io_int_word)
1153{
1154}
1155static inline void kvm_s390_crw_mchk(void)
1156{
1157}
1158static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1159{
1160}
1161static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1162 uint32_t sch, int vq,
1163 bool assign)
1164{
1165 return -ENOSYS;
1166}
1167static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1168{
1169 return -ENOSYS;
1170}
1171static inline void kvm_s390_cmma_reset(void)
1172{
1173}
1174static inline int kvm_s390_get_memslot_count(KVMState *s)
1175{
1176 return MAX_AVAIL_SLOTS;
1177}
1178static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1179{
1180 return -ENOSYS;
1181}
1182static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1183{
1184}
1185static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1186 uint64_t *hw_limit)
1187{
1188 return 0;
1189}
1190static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1191{
1192}
1193static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1194{
1195 return 0;
1196}
1197static inline int kvm_s390_get_ri(void)
1198{
1199 return 0;
1200}
1201static inline void kvm_s390_crypto_reset(void)
1202{
1203}
1204#endif
1205
1206static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1207{
1208 if (kvm_enabled()) {
1209 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1210 }
1211 return 0;
1212}
1213
1214static inline void s390_cmma_reset(void)
1215{
1216 if (kvm_enabled()) {
1217 kvm_s390_cmma_reset();
1218 }
1219}
1220
1221static inline int s390_cpu_restart(S390CPU *cpu)
1222{
1223 if (kvm_enabled()) {
1224 return kvm_s390_cpu_restart(cpu);
1225 }
1226 return -ENOSYS;
1227}
1228
1229static inline int s390_get_memslot_count(KVMState *s)
1230{
1231 if (kvm_enabled()) {
1232 return kvm_s390_get_memslot_count(s);
1233 } else {
1234 return MAX_AVAIL_SLOTS;
1235 }
1236}
1237
1238void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1239 uint32_t io_int_parm, uint32_t io_int_word);
1240void s390_crw_mchk(void);
1241
1242static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1243 uint32_t sch_id, int vq,
1244 bool assign)
1245{
1246 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1247}
1248
1249static inline void s390_crypto_reset(void)
1250{
1251 if (kvm_enabled()) {
1252 kvm_s390_crypto_reset();
1253 }
1254}
1255
1256/* machine check interruption code */
1257
1258/* subclasses */
1259#define MCIC_SC_SD 0x8000000000000000ULL
1260#define MCIC_SC_PD 0x4000000000000000ULL
1261#define MCIC_SC_SR 0x2000000000000000ULL
1262#define MCIC_SC_CD 0x0800000000000000ULL
1263#define MCIC_SC_ED 0x0400000000000000ULL
1264#define MCIC_SC_DG 0x0100000000000000ULL
1265#define MCIC_SC_W 0x0080000000000000ULL
1266#define MCIC_SC_CP 0x0040000000000000ULL
1267#define MCIC_SC_SP 0x0020000000000000ULL
1268#define MCIC_SC_CK 0x0010000000000000ULL
1269
1270/* subclass modifiers */
1271#define MCIC_SCM_B 0x0002000000000000ULL
1272#define MCIC_SCM_DA 0x0000000020000000ULL
1273#define MCIC_SCM_AP 0x0000000000080000ULL
1274
1275/* storage errors */
1276#define MCIC_SE_SE 0x0000800000000000ULL
1277#define MCIC_SE_SC 0x0000400000000000ULL
1278#define MCIC_SE_KE 0x0000200000000000ULL
1279#define MCIC_SE_DS 0x0000100000000000ULL
1280#define MCIC_SE_IE 0x0000000080000000ULL
1281
1282/* validity bits */
1283#define MCIC_VB_WP 0x0000080000000000ULL
1284#define MCIC_VB_MS 0x0000040000000000ULL
1285#define MCIC_VB_PM 0x0000020000000000ULL
1286#define MCIC_VB_IA 0x0000010000000000ULL
1287#define MCIC_VB_FA 0x0000008000000000ULL
1288#define MCIC_VB_VR 0x0000004000000000ULL
1289#define MCIC_VB_EC 0x0000002000000000ULL
1290#define MCIC_VB_FP 0x0000001000000000ULL
1291#define MCIC_VB_GR 0x0000000800000000ULL
1292#define MCIC_VB_CR 0x0000000400000000ULL
1293#define MCIC_VB_ST 0x0000000100000000ULL
1294#define MCIC_VB_AR 0x0000000040000000ULL
1295#define MCIC_VB_PR 0x0000000000200000ULL
1296#define MCIC_VB_FC 0x0000000000100000ULL
1297#define MCIC_VB_CT 0x0000000000020000ULL
1298#define MCIC_VB_CC 0x0000000000010000ULL
1299
1300#endif
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