| | 1 | /* |
| | 2 | * KVM ARM ABI constant definitions |
| | 3 | * |
| | 4 | * Copyright (c) 2013 Linaro Limited |
| | 5 | * |
| | 6 | * Provide versions of KVM constant defines that can be used even |
| | 7 | * when CONFIG_KVM is not set and we don't have access to the |
| | 8 | * KVM headers. If CONFIG_KVM is set, we do a compile-time check |
| | 9 | * that we haven't got out of sync somehow. |
| | 10 | * |
| | 11 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| | 12 | * See the COPYING file in the top-level directory. |
| | 13 | */ |
| | 14 | #ifndef ARM_KVM_CONSTS_H |
| | 15 | #define ARM_KVM_CONSTS_H |
| | 16 | |
| | 17 | #ifdef CONFIG_KVM |
| | 18 | #include "qemu/compiler.h" |
| | 19 | #include <linux/kvm.h> |
| | 20 | #include <linux/psci.h> |
| | 21 | |
| | 22 | #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y) |
| | 23 | |
| | 24 | #else |
| | 25 | #define MISMATCH_CHECK(X, Y) |
| | 26 | #endif |
| | 27 | |
| | 28 | #define CP_REG_SIZE_SHIFT 52 |
| | 29 | #define CP_REG_SIZE_MASK 0x00f0000000000000ULL |
| | 30 | #define CP_REG_SIZE_U32 0x0020000000000000ULL |
| | 31 | #define CP_REG_SIZE_U64 0x0030000000000000ULL |
| | 32 | #define CP_REG_ARM 0x4000000000000000ULL |
| | 33 | #define CP_REG_ARCH_MASK 0xff00000000000000ULL |
| | 34 | |
| | 35 | MISMATCH_CHECK(CP_REG_SIZE_SHIFT, KVM_REG_SIZE_SHIFT) |
| | 36 | MISMATCH_CHECK(CP_REG_SIZE_MASK, KVM_REG_SIZE_MASK) |
| | 37 | MISMATCH_CHECK(CP_REG_SIZE_U32, KVM_REG_SIZE_U32) |
| | 38 | MISMATCH_CHECK(CP_REG_SIZE_U64, KVM_REG_SIZE_U64) |
| | 39 | MISMATCH_CHECK(CP_REG_ARM, KVM_REG_ARM) |
| | 40 | MISMATCH_CHECK(CP_REG_ARCH_MASK, KVM_REG_ARCH_MASK) |
| | 41 | |
| | 42 | #define QEMU_PSCI_0_1_FN_BASE 0x95c1ba5e |
| | 43 | #define QEMU_PSCI_0_1_FN(n) (QEMU_PSCI_0_1_FN_BASE + (n)) |
| | 44 | #define QEMU_PSCI_0_1_FN_CPU_SUSPEND QEMU_PSCI_0_1_FN(0) |
| | 45 | #define QEMU_PSCI_0_1_FN_CPU_OFF QEMU_PSCI_0_1_FN(1) |
| | 46 | #define QEMU_PSCI_0_1_FN_CPU_ON QEMU_PSCI_0_1_FN(2) |
| | 47 | #define QEMU_PSCI_0_1_FN_MIGRATE QEMU_PSCI_0_1_FN(3) |
| | 48 | |
| | 49 | MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_SUSPEND, KVM_PSCI_FN_CPU_SUSPEND) |
| | 50 | MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_OFF, KVM_PSCI_FN_CPU_OFF) |
| | 51 | MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_ON, KVM_PSCI_FN_CPU_ON) |
| | 52 | MISMATCH_CHECK(QEMU_PSCI_0_1_FN_MIGRATE, KVM_PSCI_FN_MIGRATE) |
| | 53 | |
| | 54 | #define QEMU_PSCI_0_2_FN_BASE 0x84000000 |
| | 55 | #define QEMU_PSCI_0_2_FN(n) (QEMU_PSCI_0_2_FN_BASE + (n)) |
| | 56 | |
| | 57 | #define QEMU_PSCI_0_2_64BIT 0x40000000 |
| | 58 | #define QEMU_PSCI_0_2_FN64_BASE \ |
| | 59 | (QEMU_PSCI_0_2_FN_BASE + QEMU_PSCI_0_2_64BIT) |
| | 60 | #define QEMU_PSCI_0_2_FN64(n) (QEMU_PSCI_0_2_FN64_BASE + (n)) |
| | 61 | |
| | 62 | #define QEMU_PSCI_0_2_FN_CPU_SUSPEND QEMU_PSCI_0_2_FN(1) |
| | 63 | #define QEMU_PSCI_0_2_FN_CPU_OFF QEMU_PSCI_0_2_FN(2) |
| | 64 | #define QEMU_PSCI_0_2_FN_CPU_ON QEMU_PSCI_0_2_FN(3) |
| | 65 | #define QEMU_PSCI_0_2_FN_MIGRATE QEMU_PSCI_0_2_FN(5) |
| | 66 | |
| | 67 | #define QEMU_PSCI_0_2_FN64_CPU_SUSPEND QEMU_PSCI_0_2_FN64(1) |
| | 68 | #define QEMU_PSCI_0_2_FN64_CPU_OFF QEMU_PSCI_0_2_FN64(2) |
| | 69 | #define QEMU_PSCI_0_2_FN64_CPU_ON QEMU_PSCI_0_2_FN64(3) |
| | 70 | #define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5) |
| | 71 | |
| | 72 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND) |
| | 73 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF) |
| | 74 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON) |
| | 75 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE) |
| | 76 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND) |
| | 77 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON) |
| | 78 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE) |
| | 79 | |
| | 80 | /* Note that KVM uses overlapping values for AArch32 and AArch64 |
| | 81 | * target CPU numbers. AArch32 targets: |
| | 82 | */ |
| | 83 | #define QEMU_KVM_ARM_TARGET_CORTEX_A15 0 |
| | 84 | #define QEMU_KVM_ARM_TARGET_CORTEX_A7 1 |
| | 85 | |
| | 86 | /* AArch64 targets: */ |
| | 87 | #define QEMU_KVM_ARM_TARGET_AEM_V8 0 |
| | 88 | #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 |
| | 89 | #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 |
| | 90 | |
| | 91 | /* There's no kernel define for this: sentinel value which |
| | 92 | * matches no KVM target value for either 64 or 32 bit |
| | 93 | */ |
| | 94 | #define QEMU_KVM_ARM_TARGET_NONE UINT_MAX |
| | 95 | |
| | 96 | #ifdef TARGET_AARCH64 |
| | 97 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8) |
| | 98 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8) |
| | 99 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57) |
| | 100 | #else |
| | 101 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15) |
| | 102 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7) |
| | 103 | #endif |
| | 104 | |
| | 105 | #define CP_REG_ARM64 0x6000000000000000ULL |
| | 106 | #define CP_REG_ARM_COPROC_MASK 0x000000000FFF0000 |
| | 107 | #define CP_REG_ARM_COPROC_SHIFT 16 |
| | 108 | #define CP_REG_ARM64_SYSREG (0x0013 << CP_REG_ARM_COPROC_SHIFT) |
| | 109 | #define CP_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 |
| | 110 | #define CP_REG_ARM64_SYSREG_OP0_SHIFT 14 |
| | 111 | #define CP_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 |
| | 112 | #define CP_REG_ARM64_SYSREG_OP1_SHIFT 11 |
| | 113 | #define CP_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 |
| | 114 | #define CP_REG_ARM64_SYSREG_CRN_SHIFT 7 |
| | 115 | #define CP_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 |
| | 116 | #define CP_REG_ARM64_SYSREG_CRM_SHIFT 3 |
| | 117 | #define CP_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 |
| | 118 | #define CP_REG_ARM64_SYSREG_OP2_SHIFT 0 |
| | 119 | |
| | 120 | /* No kernel define but it's useful to QEMU */ |
| | 121 | #define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_SHIFT) |
| | 122 | |
| | 123 | #ifdef TARGET_AARCH64 |
| | 124 | MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64) |
| | 125 | MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK) |
| | 126 | MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT) |
| | 127 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG, KVM_REG_ARM64_SYSREG) |
| | 128 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_MASK) |
| | 129 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_SHIFT, KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
| | 130 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_MASK, KVM_REG_ARM64_SYSREG_OP1_MASK) |
| | 131 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_SHIFT, KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
| | 132 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_MASK, KVM_REG_ARM64_SYSREG_CRN_MASK) |
| | 133 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_SHIFT, KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
| | 134 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_MASK, KVM_REG_ARM64_SYSREG_CRM_MASK) |
| | 135 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
| | 136 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_MASK) |
| | 137 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_ARM64_SYSREG_OP2_SHIFT) |
| | 138 | #endif |
| | 139 | |
| | 140 | #undef MISMATCH_CHECK |
| | 141 | |
| | 142 | #endif |
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