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Commit	Line	Data
	1	/*
	2	* QEMU NE2000 emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "hw.h"
	25	#include "pci.h"
	26	#include "pc.h"
	27	#include "net.h"
	28
	29	/* debug NE2000 card */
	30	//#define DEBUG_NE2000
	31
	32	#define MAX_ETH_FRAME_SIZE 1514
	33
	34	#define E8390_CMD 0x00 /* The command register (for all pages) */
	35	/* Page 0 register offsets. */
	36	#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
	37	#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
	38	#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
	39	#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
	40	#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
	41	#define EN0_TSR 0x04 /* Transmit status reg RD */
	42	#define EN0_TPSR 0x04 /* Transmit starting page WR */
	43	#define EN0_NCR 0x05 /* Number of collision reg RD */
	44	#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
	45	#define EN0_FIFO 0x06 /* FIFO RD */
	46	#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
	47	#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
	48	#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
	49	#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
	50	#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
	51	#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
	52	#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
	53	#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
	54	#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
	55	#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
	56	#define EN0_RSR 0x0c /* rx status reg RD */
	57	#define EN0_RXCR 0x0c /* RX configuration reg WR */
	58	#define EN0_TXCR 0x0d /* TX configuration reg WR */
	59	#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
	60	#define EN0_DCFG 0x0e /* Data configuration reg WR */
	61	#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
	62	#define EN0_IMR 0x0f /* Interrupt mask reg WR */
	63	#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
	64
	65	#define EN1_PHYS 0x11
	66	#define EN1_CURPAG 0x17
	67	#define EN1_MULT 0x18
	68
	69	#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
	70	#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
	71
	72	#define EN3_CONFIG0 0x33
	73	#define EN3_CONFIG1 0x34
	74	#define EN3_CONFIG2 0x35
	75	#define EN3_CONFIG3 0x36
	76
	77	/* Register accessed at EN_CMD, the 8390 base addr. */
	78	#define E8390_STOP 0x01 /* Stop and reset the chip */
	79	#define E8390_START 0x02 /* Start the chip, clear reset */
	80	#define E8390_TRANS 0x04 /* Transmit a frame */
	81	#define E8390_RREAD 0x08 /* Remote read */
	82	#define E8390_RWRITE 0x10 /* Remote write */
	83	#define E8390_NODMA 0x20 /* Remote DMA */
	84	#define E8390_PAGE0 0x00 /* Select page chip registers */
	85	#define E8390_PAGE1 0x40 /* using the two high-order bits */
	86	#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
	87
	88	/* Bits in EN0_ISR - Interrupt status register */
	89	#define ENISR_RX 0x01 /* Receiver, no error */
	90	#define ENISR_TX 0x02 /* Transmitter, no error */
	91	#define ENISR_RX_ERR 0x04 /* Receiver, with error */
	92	#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
	93	#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
	94	#define ENISR_COUNTERS 0x20 /* Counters need emptying */
	95	#define ENISR_RDC 0x40 /* remote dma complete */
	96	#define ENISR_RESET 0x80 /* Reset completed */
	97	#define ENISR_ALL 0x3f /* Interrupts we will enable */
	98
	99	/* Bits in received packet status byte and EN0_RSR*/
	100	#define ENRSR_RXOK 0x01 /* Received a good packet */
	101	#define ENRSR_CRC 0x02 /* CRC error */
	102	#define ENRSR_FAE 0x04 /* frame alignment error */
	103	#define ENRSR_FO 0x08 /* FIFO overrun */
	104	#define ENRSR_MPA 0x10 /* missed pkt */
	105	#define ENRSR_PHY 0x20 /* physical/multicast address */
	106	#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
	107	#define ENRSR_DEF 0x80 /* deferring */
	108
	109	/* Transmitted packet status, EN0_TSR. */
	110	#define ENTSR_PTX 0x01 /* Packet transmitted without error */
	111	#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
	112	#define ENTSR_COL 0x04 /* The transmit collided at least once. */
	113	#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
	114	#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
	115	#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
	116	#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
	117	#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
	118
	119	#define NE2000_PMEM_SIZE (32*1024)
	120	#define NE2000_PMEM_START (16*1024)
	121	#define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
	122	#define NE2000_MEM_SIZE NE2000_PMEM_END
	123
	124	typedef struct NE2000State {
	125	uint8_t cmd;
	126	uint32_t start;
	127	uint32_t stop;
	128	uint8_t boundary;
	129	uint8_t tsr;
	130	uint8_t tpsr;
	131	uint16_t tcnt;
	132	uint16_t rcnt;
	133	uint32_t rsar;
	134	uint8_t rsr;
	135	uint8_t rxcr;
	136	uint8_t isr;
	137	uint8_t dcfg;
	138	uint8_t imr;
	139	uint8_t phys[6]; /* mac address */
	140	uint8_t curpag;
	141	uint8_t mult[8]; /* multicast mask array */
	142	qemu_irq irq;
	143	int isa_io_base;
	144	PCIDevice *pci_dev;
	145	VLANClientState *vc;
	146	uint8_t macaddr[6];
	147	uint8_t mem[NE2000_MEM_SIZE];
	148	} NE2000State;
	149
	150	typedef struct PCINE2000State {
	151	PCIDevice dev;
	152	NE2000State ne2000;
	153	} PCINE2000State;
	154
	155	static void ne2000_reset(NE2000State *s)
	156	{
	157	int i;
	158
	159	s->isr = ENISR_RESET;
	160	memcpy(s->mem, s->macaddr, 6);
	161	s->mem[14] = 0x57;
	162	s->mem[15] = 0x57;
	163
	164	/* duplicate prom data */
	165	for(i = 15;i >= 0; i--) {
	166	s->mem[2 * i] = s->mem[i];
	167	s->mem[2 * i + 1] = s->mem[i];
	168	}
	169	}
	170
	171	static void ne2000_update_irq(NE2000State *s)
	172	{
	173	int isr;
	174	isr = (s->isr & s->imr) & 0x7f;
	175	#if defined(DEBUG_NE2000)
	176	printf("NE2000: Set IRQ to %d (%02x %02x)\n",
	177	isr ? 1 : 0, s->isr, s->imr);
	178	#endif
	179	qemu_set_irq(s->irq, (isr != 0));
	180	}
	181
	182	#define POLYNOMIAL 0x04c11db6
	183
	184	/* From FreeBSD */
	185	/* XXX: optimize */
	186	static int compute_mcast_idx(const uint8_t *ep)
	187	{
	188	uint32_t crc;
	189	int carry, i, j;
	190	uint8_t b;
	191
	192	crc = 0xffffffff;
	193	for (i = 0; i < 6; i++) {
	194	b = *ep++;
	195	for (j = 0; j < 8; j++) {
	196	carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
	197	crc <<= 1;
	198	b >>= 1;
	199	if (carry)
	200	crc = ((crc ^ POLYNOMIAL) \| carry);
	201	}
	202	}
	203	return (crc >> 26);
	204	}
	205
	206	static int ne2000_buffer_full(NE2000State *s)
	207	{
	208	int avail, index, boundary;
	209
	210	index = s->curpag << 8;
	211	boundary = s->boundary << 8;
	212	if (index < boundary)
	213	avail = boundary - index;
	214	else
	215	avail = (s->stop - s->start) - (index - boundary);
	216	if (avail < (MAX_ETH_FRAME_SIZE + 4))
	217	return 1;
	218	return 0;
	219	}
	220
	221	static int ne2000_can_receive(VLANClientState *vc)
	222	{
	223	NE2000State *s = vc->opaque;
	224
	225	if (s->cmd & E8390_STOP)
	226	return 1;
	227	return !ne2000_buffer_full(s);
	228	}
	229
	230	#define MIN_BUF_SIZE 60
	231
	232	static ssize_t ne2000_receive(VLANClientState vc, const uint8_t buf, size_t size_)
	233	{
	234	NE2000State *s = vc->opaque;
	235	int size = size_;
	236	uint8_t *p;
	237	unsigned int total_len, next, avail, len, index, mcast_idx;
	238	uint8_t buf1[60];
	239	static const uint8_t broadcast_macaddr[6] =
	240	{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
	241
	242	#if defined(DEBUG_NE2000)
	243	printf("NE2000: received len=%d\n", size);
	244	#endif
	245
	246	if (s->cmd & E8390_STOP \|\| ne2000_buffer_full(s))
	247	return -1;
	248
	249	/* XXX: check this */
	250	if (s->rxcr & 0x10) {
	251	/* promiscuous: receive all */
	252	} else {
	253	if (!memcmp(buf, broadcast_macaddr, 6)) {
	254	/* broadcast address */
	255	if (!(s->rxcr & 0x04))
	256	return size;
	257	} else if (buf[0] & 0x01) {
	258	/* multicast */
	259	if (!(s->rxcr & 0x08))
	260	return size;
	261	mcast_idx = compute_mcast_idx(buf);
	262	if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
	263	return size;
	264	} else if (s->mem[0] == buf[0] &&
	265	s->mem[2] == buf[1] &&
	266	s->mem[4] == buf[2] &&
	267	s->mem[6] == buf[3] &&
	268	s->mem[8] == buf[4] &&
	269	s->mem[10] == buf[5]) {
	270	/* match */
	271	} else {
	272	return size;
	273	}
	274	}
	275
	276
	277	/* if too small buffer, then expand it */
	278	if (size < MIN_BUF_SIZE) {
	279	memcpy(buf1, buf, size);
	280	memset(buf1 + size, 0, MIN_BUF_SIZE - size);
	281	buf = buf1;
	282	size = MIN_BUF_SIZE;
	283	}
	284
	285	index = s->curpag << 8;
	286	/* 4 bytes for header */
	287	total_len = size + 4;
	288	/* address for next packet (4 bytes for CRC) */
	289	next = index + ((total_len + 4 + 255) & ~0xff);
	290	if (next >= s->stop)
	291	next -= (s->stop - s->start);
	292	/* prepare packet header */
	293	p = s->mem + index;
	294	s->rsr = ENRSR_RXOK; /* receive status */
	295	/* XXX: check this */
	296	if (buf[0] & 0x01)
	297	s->rsr \|= ENRSR_PHY;
	298	p[0] = s->rsr;
	299	p[1] = next >> 8;
	300	p[2] = total_len;
	301	p[3] = total_len >> 8;
	302	index += 4;
	303
	304	/* write packet data */
	305	while (size > 0) {
	306	if (index <= s->stop)
	307	avail = s->stop - index;
	308	else
	309	avail = 0;
	310	len = size;
	311	if (len > avail)
	312	len = avail;
	313	memcpy(s->mem + index, buf, len);
	314	buf += len;
	315	index += len;
	316	if (index == s->stop)
	317	index = s->start;
	318	size -= len;
	319	}
	320	s->curpag = next >> 8;
	321
	322	/* now we can signal we have received something */
	323	s->isr \|= ENISR_RX;
	324	ne2000_update_irq(s);
	325
	326	return size_;
	327	}
	328
	329	static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
	330	{
	331	NE2000State *s = opaque;
	332	int offset, page, index;
	333
	334	addr &= 0xf;
	335	#ifdef DEBUG_NE2000
	336	printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
	337	#endif
	338	if (addr == E8390_CMD) {
	339	/* control register */
	340	s->cmd = val;
	341	if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
	342	s->isr &= ~ENISR_RESET;
	343	/* test specific case: zero length transfer */
	344	if ((val & (E8390_RREAD \| E8390_RWRITE)) &&
	345	s->rcnt == 0) {
	346	s->isr \|= ENISR_RDC;
	347	ne2000_update_irq(s);
	348	}
	349	if (val & E8390_TRANS) {
	350	index = (s->tpsr << 8);
	351	/* XXX: next 2 lines are a hack to make netware 3.11 work */
	352	if (index >= NE2000_PMEM_END)
	353	index -= NE2000_PMEM_SIZE;
	354	/* fail safe: check range on the transmitted length */
	355	if (index + s->tcnt <= NE2000_PMEM_END) {
	356	qemu_send_packet(s->vc, s->mem + index, s->tcnt);
	357	}
	358	/* signal end of transfer */
	359	s->tsr = ENTSR_PTX;
	360	s->isr \|= ENISR_TX;
	361	s->cmd &= ~E8390_TRANS;
	362	ne2000_update_irq(s);
	363	}
	364	}
	365	} else {
	366	page = s->cmd >> 6;
	367	offset = addr \| (page << 4);
	368	switch(offset) {
	369	case EN0_STARTPG:
	370	s->start = val << 8;
	371	break;
	372	case EN0_STOPPG:
	373	s->stop = val << 8;
	374	break;
	375	case EN0_BOUNDARY:
	376	s->boundary = val;
	377	break;
	378	case EN0_IMR:
	379	s->imr = val;
	380	ne2000_update_irq(s);
	381	break;
	382	case EN0_TPSR:
	383	s->tpsr = val;
	384	break;
	385	case EN0_TCNTLO:
	386	s->tcnt = (s->tcnt & 0xff00) \| val;
	387	break;
	388	case EN0_TCNTHI:
	389	s->tcnt = (s->tcnt & 0x00ff) \| (val << 8);
	390	break;
	391	case EN0_RSARLO:
	392	s->rsar = (s->rsar & 0xff00) \| val;
	393	break;
	394	case EN0_RSARHI:
	395	s->rsar = (s->rsar & 0x00ff) \| (val << 8);
	396	break;
	397	case EN0_RCNTLO:
	398	s->rcnt = (s->rcnt & 0xff00) \| val;
	399	break;
	400	case EN0_RCNTHI:
	401	s->rcnt = (s->rcnt & 0x00ff) \| (val << 8);
	402	break;
	403	case EN0_RXCR:
	404	s->rxcr = val;
	405	break;
	406	case EN0_DCFG:
	407	s->dcfg = val;
	408	break;
	409	case EN0_ISR:
	410	s->isr &= ~(val & 0x7f);
	411	ne2000_update_irq(s);
	412	break;
	413	case EN1_PHYS ... EN1_PHYS + 5:
	414	s->phys[offset - EN1_PHYS] = val;
	415	break;
	416	case EN1_CURPAG:
	417	s->curpag = val;
	418	break;
	419	case EN1_MULT ... EN1_MULT + 7:
	420	s->mult[offset - EN1_MULT] = val;
	421	break;
	422	}
	423	}
	424	}
	425
	426	static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
	427	{
	428	NE2000State *s = opaque;
	429	int offset, page, ret;
	430
	431	addr &= 0xf;
	432	if (addr == E8390_CMD) {
	433	ret = s->cmd;
	434	} else {
	435	page = s->cmd >> 6;
	436	offset = addr \| (page << 4);
	437	switch(offset) {
	438	case EN0_TSR:
	439	ret = s->tsr;
	440	break;
	441	case EN0_BOUNDARY:
	442	ret = s->boundary;
	443	break;
	444	case EN0_ISR:
	445	ret = s->isr;
	446	break;
	447	case EN0_RSARLO:
	448	ret = s->rsar & 0x00ff;
	449	break;
	450	case EN0_RSARHI:
	451	ret = s->rsar >> 8;
	452	break;
	453	case EN1_PHYS ... EN1_PHYS + 5:
	454	ret = s->phys[offset - EN1_PHYS];
	455	break;
	456	case EN1_CURPAG:
	457	ret = s->curpag;
	458	break;
	459	case EN1_MULT ... EN1_MULT + 7:
	460	ret = s->mult[offset - EN1_MULT];
	461	break;
	462	case EN0_RSR:
	463	ret = s->rsr;
	464	break;
	465	case EN2_STARTPG:
	466	ret = s->start >> 8;
	467	break;
	468	case EN2_STOPPG:
	469	ret = s->stop >> 8;
	470	break;
	471	case EN0_RTL8029ID0:
	472	ret = 0x50;
	473	break;
	474	case EN0_RTL8029ID1:
	475	ret = 0x43;
	476	break;
	477	case EN3_CONFIG0:
	478	ret = 0; /* 10baseT media */
	479	break;
	480	case EN3_CONFIG2:
	481	ret = 0x40; /* 10baseT active */
	482	break;
	483	case EN3_CONFIG3:
	484	ret = 0x40; /* Full duplex */
	485	break;
	486	default:
	487	ret = 0x00;
	488	break;
	489	}
	490	}
	491	#ifdef DEBUG_NE2000
	492	printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
	493	#endif
	494	return ret;
	495	}
	496
	497	static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
	498	uint32_t val)
	499	{
	500	if (addr < 32 \|\|
	501	(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
	502	s->mem[addr] = val;
	503	}
	504	}
	505
	506	static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
	507	uint32_t val)
	508	{
	509	addr &= ~1; /* XXX: check exact behaviour if not even */
	510	if (addr < 32 \|\|
	511	(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
	512	(uint16_t )(s->mem + addr) = cpu_to_le16(val);
	513	}
	514	}
	515
	516	static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
	517	uint32_t val)
	518	{
	519	addr &= ~1; /* XXX: check exact behaviour if not even */
	520	if (addr < 32 \|\|
	521	(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
	522	cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
	523	}
	524	}
	525
	526	static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
	527	{
	528	if (addr < 32 \|\|
	529	(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
	530	return s->mem[addr];
	531	} else {
	532	return 0xff;
	533	}
	534	}
	535
	536	static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
	537	{
	538	addr &= ~1; /* XXX: check exact behaviour if not even */
	539	if (addr < 32 \|\|
	540	(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
	541	return le16_to_cpu((uint16_t )(s->mem + addr));
	542	} else {
	543	return 0xffff;
	544	}
	545	}
	546
	547	static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
	548	{
	549	addr &= ~1; /* XXX: check exact behaviour if not even */
	550	if (addr < 32 \|\|
	551	(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
	552	return le32_to_cpupu((uint32_t *)(s->mem + addr));
	553	} else {
	554	return 0xffffffff;
	555	}
	556	}
	557
	558	static inline void ne2000_dma_update(NE2000State *s, int len)
	559	{
	560	s->rsar += len;
	561	/* wrap */
	562	/* XXX: check what to do if rsar > stop */
	563	if (s->rsar == s->stop)
	564	s->rsar = s->start;
	565
	566	if (s->rcnt <= len) {
	567	s->rcnt = 0;
	568	/* signal end of transfer */
	569	s->isr \|= ENISR_RDC;
	570	ne2000_update_irq(s);
	571	} else {
	572	s->rcnt -= len;
	573	}
	574	}
	575
	576	static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
	577	{
	578	NE2000State *s = opaque;
	579
	580	#ifdef DEBUG_NE2000
	581	printf("NE2000: asic write val=0x%04x\n", val);
	582	#endif
	583	if (s->rcnt == 0)
	584	return;
	585	if (s->dcfg & 0x01) {
	586	/* 16 bit access */
	587	ne2000_mem_writew(s, s->rsar, val);
	588	ne2000_dma_update(s, 2);
	589	} else {
	590	/* 8 bit access */
	591	ne2000_mem_writeb(s, s->rsar, val);
	592	ne2000_dma_update(s, 1);
	593	}
	594	}
	595
	596	static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
	597	{
	598	NE2000State *s = opaque;
	599	int ret;
	600
	601	if (s->dcfg & 0x01) {
	602	/* 16 bit access */
	603	ret = ne2000_mem_readw(s, s->rsar);
	604	ne2000_dma_update(s, 2);
	605	} else {
	606	/* 8 bit access */
	607	ret = ne2000_mem_readb(s, s->rsar);
	608	ne2000_dma_update(s, 1);
	609	}
	610	#ifdef DEBUG_NE2000
	611	printf("NE2000: asic read val=0x%04x\n", ret);
	612	#endif
	613	return ret;
	614	}
	615
	616	static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
	617	{
	618	NE2000State *s = opaque;
	619
	620	#ifdef DEBUG_NE2000
	621	printf("NE2000: asic writel val=0x%04x\n", val);
	622	#endif
	623	if (s->rcnt == 0)
	624	return;
	625	/* 32 bit access */
	626	ne2000_mem_writel(s, s->rsar, val);
	627	ne2000_dma_update(s, 4);
	628	}
	629
	630	static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
	631	{
	632	NE2000State *s = opaque;
	633	int ret;
	634
	635	/* 32 bit access */
	636	ret = ne2000_mem_readl(s, s->rsar);
	637	ne2000_dma_update(s, 4);
	638	#ifdef DEBUG_NE2000
	639	printf("NE2000: asic readl val=0x%04x\n", ret);
	640	#endif
	641	return ret;
	642	}
	643
	644	static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
	645	{
	646	/* nothing to do (end of reset pulse) */
	647	}
	648
	649	static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
	650	{
	651	NE2000State *s = opaque;
	652	ne2000_reset(s);
	653	return 0;
	654	}
	655
	656	static void ne2000_save(QEMUFile* f,void* opaque)
	657	{
	658	NE2000State* s = opaque;
	659	uint32_t tmp;
	660
	661	if (s->pci_dev)
	662	pci_device_save(s->pci_dev, f);
	663
	664	qemu_put_8s(f, &s->rxcr);
	665
	666	qemu_put_8s(f, &s->cmd);
	667	qemu_put_be32s(f, &s->start);
	668	qemu_put_be32s(f, &s->stop);
	669	qemu_put_8s(f, &s->boundary);
	670	qemu_put_8s(f, &s->tsr);
	671	qemu_put_8s(f, &s->tpsr);
	672	qemu_put_be16s(f, &s->tcnt);
	673	qemu_put_be16s(f, &s->rcnt);
	674	qemu_put_be32s(f, &s->rsar);
	675	qemu_put_8s(f, &s->rsr);
	676	qemu_put_8s(f, &s->isr);
	677	qemu_put_8s(f, &s->dcfg);
	678	qemu_put_8s(f, &s->imr);
	679	qemu_put_buffer(f, s->phys, 6);
	680	qemu_put_8s(f, &s->curpag);
	681	qemu_put_buffer(f, s->mult, 8);
	682	tmp = 0;
	683	qemu_put_be32s(f, &tmp); /* ignored, was irq */
	684	qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
	685	}
	686
	687	static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
	688	{
	689	NE2000State* s = opaque;
	690	int ret;
	691	uint32_t tmp;
	692
	693	if (version_id > 3)
	694	return -EINVAL;
	695
	696	if (s->pci_dev && version_id >= 3) {
	697	ret = pci_device_load(s->pci_dev, f);
	698	if (ret < 0)
	699	return ret;
	700	}
	701
	702	if (version_id >= 2) {
	703	qemu_get_8s(f, &s->rxcr);
	704	} else {
	705	s->rxcr = 0x0c;
	706	}
	707
	708	qemu_get_8s(f, &s->cmd);
	709	qemu_get_be32s(f, &s->start);
	710	qemu_get_be32s(f, &s->stop);
	711	qemu_get_8s(f, &s->boundary);
	712	qemu_get_8s(f, &s->tsr);
	713	qemu_get_8s(f, &s->tpsr);
	714	qemu_get_be16s(f, &s->tcnt);
	715	qemu_get_be16s(f, &s->rcnt);
	716	qemu_get_be32s(f, &s->rsar);
	717	qemu_get_8s(f, &s->rsr);
	718	qemu_get_8s(f, &s->isr);
	719	qemu_get_8s(f, &s->dcfg);
	720	qemu_get_8s(f, &s->imr);
	721	qemu_get_buffer(f, s->phys, 6);
	722	qemu_get_8s(f, &s->curpag);
	723	qemu_get_buffer(f, s->mult, 8);
	724	qemu_get_be32s(f, &tmp); /* ignored */
	725	qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
	726
	727	return 0;
	728	}
	729
	730	static void isa_ne2000_cleanup(VLANClientState *vc)
	731	{
	732	NE2000State *s = vc->opaque;
	733
	734	unregister_savevm("ne2000", s);
	735
	736	isa_unassign_ioport(s->isa_io_base, 16);
	737	isa_unassign_ioport(s->isa_io_base + 0x10, 2);
	738	isa_unassign_ioport(s->isa_io_base + 0x1f, 1);
	739
	740	qemu_free(s);
	741	}
	742
	743	void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd)
	744	{
	745	NE2000State *s;
	746
	747	qemu_check_nic_model(nd, "ne2k_isa");
	748
	749	s = qemu_mallocz(sizeof(NE2000State));
	750
	751	register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
	752	register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
	753
	754	register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
	755	register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
	756	register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
	757	register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
	758
	759	register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
	760	register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
	761	s->isa_io_base = base;
	762	s->irq = irq;
	763	memcpy(s->macaddr, nd->macaddr, 6);
	764
	765	ne2000_reset(s);
	766
	767	s->vc = nd->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
	768	ne2000_can_receive, ne2000_receive,
	769	NULL, isa_ne2000_cleanup, s);
	770
	771	qemu_format_nic_info_str(s->vc, s->macaddr);
	772
	773	register_savevm("ne2000", -1, 2, ne2000_save, ne2000_load, s);
	774	}
	775
	776	/***********************************************************/
	777	/* PCI NE2000 definitions */
	778
	779	static void ne2000_map(PCIDevice *pci_dev, int region_num,
	780	uint32_t addr, uint32_t size, int type)
	781	{
	782	PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
	783	NE2000State *s = &d->ne2000;
	784
	785	register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
	786	register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
	787
	788	register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
	789	register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
	790	register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
	791	register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
	792	register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
	793	register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
	794
	795	register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
	796	register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
	797	}
	798
	799	static void ne2000_cleanup(VLANClientState *vc)
	800	{
	801	NE2000State *s = vc->opaque;
	802
	803	unregister_savevm("ne2000", s);
	804	}
	805
	806	static int pci_ne2000_init(PCIDevice *pci_dev)
	807	{
	808	PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
	809	NE2000State *s;
	810	uint8_t *pci_conf;
	811
	812	pci_conf = d->dev.config;
	813	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
	814	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029);
	815	pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
	816	pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
	817	pci_conf[0x3d] = 1; // interrupt pin 0
	818
	819	pci_register_bar(&d->dev, 0, 0x100,
	820	PCI_ADDRESS_SPACE_IO, ne2000_map);
	821	s = &d->ne2000;
	822	s->irq = d->dev.irq[0];
	823	s->pci_dev = pci_dev;
	824	qdev_get_macaddr(&d->dev.qdev, s->macaddr);
	825	ne2000_reset(s);
	826	s->vc = qdev_get_vlan_client(&d->dev.qdev,
	827	ne2000_can_receive, ne2000_receive, NULL,
	828	ne2000_cleanup, s);
	829
	830	qemu_format_nic_info_str(s->vc, s->macaddr);
	831
	832	register_savevm("ne2000", -1, 3, ne2000_save, ne2000_load, s);
	833	return 0;
	834	}
	835
	836	static PCIDeviceInfo ne2000_info = {
	837	.qdev.name = "ne2k_pci",
	838	.qdev.size = sizeof(PCINE2000State),
	839	.init = pci_ne2000_init,
	840	};
	841
	842	static void ne2000_register_devices(void)
	843	{
	844	pci_qdev_register(&ne2000_info);
	845	}
	846
	847	device_init(ne2000_register_devices)