Git Repo - qemu.git/blame_incremental

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Commit	Line	Data
	1	/*
	2	* INTC device simulation in PKUnity SoC
	3	*
	4	* Copyright (C) 2010-2012 Guan Xuetao
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation, or any later version.
	9	* See the COPYING file in the top-level directory.
	10	*/
	11	#include "qemu/osdep.h"
	12	#include "hw/sysbus.h"
	13
	14	#undef DEBUG_PUV3
	15	#include "hw/unicore32/puv3.h"
	16
	17	#define TYPE_PUV3_INTC "puv3_intc"
	18	#define PUV3_INTC(obj) OBJECT_CHECK(PUV3INTCState, (obj), TYPE_PUV3_INTC)
	19
	20	typedef struct PUV3INTCState {
	21	SysBusDevice parent_obj;
	22
	23	MemoryRegion iomem;
	24	qemu_irq parent_irq;
	25
	26	uint32_t reg_ICMR;
	27	uint32_t reg_ICPR;
	28	} PUV3INTCState;
	29
	30	/* Update interrupt status after enabled or pending bits have been changed. */
	31	static void puv3_intc_update(PUV3INTCState *s)
	32	{
	33	if (s->reg_ICMR & s->reg_ICPR) {
	34	qemu_irq_raise(s->parent_irq);
	35	} else {
	36	qemu_irq_lower(s->parent_irq);
	37	}
	38	}
	39
	40	/* Process a change in an external INTC input. */
	41	static void puv3_intc_handler(void *opaque, int irq, int level)
	42	{
	43	PUV3INTCState *s = opaque;
	44
	45	DPRINTF("irq 0x%x, level 0x%x\n", irq, level);
	46	if (level) {
	47	s->reg_ICPR \|= (1 << irq);
	48	} else {
	49	s->reg_ICPR &= ~(1 << irq);
	50	}
	51	puv3_intc_update(s);
	52	}
	53
	54	static uint64_t puv3_intc_read(void *opaque, hwaddr offset,
	55	unsigned size)
	56	{
	57	PUV3INTCState *s = opaque;
	58	uint32_t ret = 0;
	59
	60	switch (offset) {
	61	case 0x04: /* INTC_ICMR */
	62	ret = s->reg_ICMR;
	63	break;
	64	case 0x0c: /* INTC_ICIP */
	65	ret = s->reg_ICPR; /* the same value with ICPR */
	66	break;
	67	default:
	68	DPRINTF("Bad offset %x\n", (int)offset);
	69	}
	70	DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
	71	return ret;
	72	}
	73
	74	static void puv3_intc_write(void *opaque, hwaddr offset,
	75	uint64_t value, unsigned size)
	76	{
	77	PUV3INTCState *s = opaque;
	78
	79	DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
	80	switch (offset) {
	81	case 0x00: /* INTC_ICLR */
	82	case 0x14: /* INTC_ICCR */
	83	break;
	84	case 0x04: /* INTC_ICMR */
	85	s->reg_ICMR = value;
	86	break;
	87	default:
	88	DPRINTF("Bad offset 0x%x\n", (int)offset);
	89	return;
	90	}
	91	puv3_intc_update(s);
	92	}
	93
	94	static const MemoryRegionOps puv3_intc_ops = {
	95	.read = puv3_intc_read,
	96	.write = puv3_intc_write,
	97	.impl = {
	98	.min_access_size = 4,
	99	.max_access_size = 4,
	100	},
	101	.endianness = DEVICE_NATIVE_ENDIAN,
	102	};
	103
	104	static void puv3_intc_realize(DeviceState dev, Error *errp)
	105	{
	106	PUV3INTCState *s = PUV3_INTC(dev);
	107	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
	108
	109	qdev_init_gpio_in(dev, puv3_intc_handler, PUV3_IRQS_NR);
	110	sysbus_init_irq(sbd, &s->parent_irq);
	111
	112	s->reg_ICMR = 0;
	113	s->reg_ICPR = 0;
	114
	115	memory_region_init_io(&s->iomem, OBJECT(s), &puv3_intc_ops, s, "puv3_intc",
	116	PUV3_REGS_OFFSET);
	117	sysbus_init_mmio(sbd, &s->iomem);
	118	}
	119
	120	static void puv3_intc_class_init(ObjectClass klass, void data)
	121	{
	122	DeviceClass *dc = DEVICE_CLASS(klass);
	123	dc->realize = puv3_intc_realize;
	124	}
	125
	126	static const TypeInfo puv3_intc_info = {
	127	.name = TYPE_PUV3_INTC,
	128	.parent = TYPE_SYS_BUS_DEVICE,
	129	.instance_size = sizeof(PUV3INTCState),
	130	.class_init = puv3_intc_class_init,
	131	};
	132
	133	static void puv3_intc_register_type(void)
	134	{
	135	type_register_static(&puv3_intc_info);
	136	}
	137
	138	type_init(puv3_intc_register_type)