[qemu.git] / target-sh4 / op_helper.c

/*
 *  SH4 emulation
 *
 *  Copyright (c) 2005 Samuel Tardieu
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include <assert.h>
#include <stdlib.h>
#include "cpu.h"
#include "helper.h"

static void cpu_restore_state_from_retaddr(CPUSH4State *env, uintptr_t retaddr)
{
    TranslationBlock *tb;

    if (retaddr) {
        tb = tb_find_pc(retaddr);
        if (tb) {
            /* the PC is inside the translated code. It means that we have
               a virtual CPU fault */
            cpu_restore_state(tb, env, retaddr);
        }
    }
}

#ifndef CONFIG_USER_ONLY
#include "softmmu_exec.h"

#define MMUSUFFIX _mmu

#define SHIFT 0
#include "softmmu_template.h"

#define SHIFT 1
#include "softmmu_template.h"

#define SHIFT 2
#include "softmmu_template.h"

#define SHIFT 3
#include "softmmu_template.h"

void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
              uintptr_t retaddr)
{
    int ret;

    ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
    if (ret) {
        /* now we have a real cpu fault */
        cpu_restore_state_from_retaddr(env, retaddr);
        cpu_loop_exit(env);
    }
}

#endif

void helper_ldtlb(CPUSH4State *env)
{
#ifdef CONFIG_USER_ONLY
    /* XXXXX */
    cpu_abort(env, "Unhandled ldtlb");
#else
    cpu_load_tlb(env);
#endif
}

static inline void raise_exception(CPUSH4State *env, int index,
                                   uintptr_t retaddr)
{
    env->exception_index = index;
    cpu_restore_state_from_retaddr(env, retaddr);
    cpu_loop_exit(env);
}

void helper_raise_illegal_instruction(CPUSH4State *env)
{
    raise_exception(env, 0x180, GETPC());
}

void helper_raise_slot_illegal_instruction(CPUSH4State *env)
{
    raise_exception(env, 0x1a0, GETPC());
}

void helper_raise_fpu_disable(CPUSH4State *env)
{
    raise_exception(env, 0x800, GETPC());
}

void helper_raise_slot_fpu_disable(CPUSH4State *env)
{
    raise_exception(env, 0x820, GETPC());
}

void helper_debug(CPUSH4State *env)
{
    env->exception_index = EXCP_DEBUG;
    cpu_loop_exit(env);
}

void helper_sleep(CPUSH4State *env, uint32_t next_pc)
{
    env->halted = 1;
    env->in_sleep = 1;
    env->exception_index = EXCP_HLT;
    env->pc = next_pc;
    cpu_loop_exit(env);
}

void helper_trapa(CPUSH4State *env, uint32_t tra)
{
    env->tra = tra << 2;
    raise_exception(env, 0x160, GETPC());
}

void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
{
    if (cpu_sh4_is_cached (env, address))
    {
	memory_content *r = malloc (sizeof(memory_content));
	r->address = address;
	r->value = value;
	r->next = NULL;

	*(env->movcal_backup_tail) = r;
	env->movcal_backup_tail = &(r->next);
    }
}

void helper_discard_movcal_backup(CPUSH4State *env)
{
    memory_content *current = env->movcal_backup;

    while(current)
    {
	memory_content *next = current->next;
	free (current);
	env->movcal_backup = current = next;
	if (current == NULL)
	    env->movcal_backup_tail = &(env->movcal_backup);
    } 
}

void helper_ocbi(CPUSH4State *env, uint32_t address)
{
    memory_content **current = &(env->movcal_backup);
    while (*current)
    {
	uint32_t a = (*current)->address;
	if ((a & ~0x1F) == (address & ~0x1F))
	{
	    memory_content *next = (*current)->next;
            cpu_stl_data(env, a, (*current)->value);
	    
	    if (next == NULL)
	    {
		env->movcal_backup_tail = current;
	    }

	    free (*current);
	    *current = next;
	    break;
	}
    }
}

uint32_t helper_addc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
    uint32_t tmp0, tmp1;

    tmp1 = arg0 + arg1;
    tmp0 = arg1;
    arg1 = tmp1 + (env->sr & 1);
    if (tmp0 > tmp1)
	env->sr |= SR_T;
    else
	env->sr &= ~SR_T;
    if (tmp1 > arg1)
	env->sr |= SR_T;
    return arg1;
}

uint32_t helper_addv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
    uint32_t dest, src, ans;

    if ((int32_t) arg1 >= 0)
	dest = 0;
    else
	dest = 1;
    if ((int32_t) arg0 >= 0)
	src = 0;
    else
	src = 1;
    src += dest;
    arg1 += arg0;
    if ((int32_t) arg1 >= 0)
	ans = 0;
    else
	ans = 1;
    ans += dest;
    if (src == 0 || src == 2) {
	if (ans == 1)
	    env->sr |= SR_T;
	else
	    env->sr &= ~SR_T;
    } else
	env->sr &= ~SR_T;
    return arg1;
}

#define T (env->sr & SR_T)
#define Q (env->sr & SR_Q ? 1 : 0)
#define M (env->sr & SR_M ? 1 : 0)
#define SETT env->sr |= SR_T
#define CLRT env->sr &= ~SR_T
#define SETQ env->sr |= SR_Q
#define CLRQ env->sr &= ~SR_Q
#define SETM env->sr |= SR_M
#define CLRM env->sr &= ~SR_M

uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
    uint32_t tmp0, tmp2;
    uint8_t old_q, tmp1 = 0xff;

    //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
    old_q = Q;
    if ((0x80000000 & arg1) != 0)
	SETQ;
    else
	CLRQ;
    tmp2 = arg0;
    arg1 <<= 1;
    arg1 |= T;
    switch (old_q) {
    case 0:
	switch (M) {
	case 0:
	    tmp0 = arg1;
	    arg1 -= tmp2;
	    tmp1 = arg1 > tmp0;
	    switch (Q) {
	    case 0:
		if (tmp1)
		    SETQ;
		else
		    CLRQ;
		break;
	    case 1:
		if (tmp1 == 0)
		    SETQ;
		else
		    CLRQ;
		break;
	    }
	    break;
	case 1:
	    tmp0 = arg1;
	    arg1 += tmp2;
	    tmp1 = arg1 < tmp0;
	    switch (Q) {
	    case 0:
		if (tmp1 == 0)
		    SETQ;
		else
		    CLRQ;
		break;
	    case 1:
		if (tmp1)
		    SETQ;
		else
		    CLRQ;
		break;
	    }
	    break;
	}
	break;
    case 1:
	switch (M) {
	case 0:
	    tmp0 = arg1;
	    arg1 += tmp2;
	    tmp1 = arg1 < tmp0;
	    switch (Q) {
	    case 0:
		if (tmp1)
		    SETQ;
		else
		    CLRQ;
		break;
	    case 1:
		if (tmp1 == 0)
		    SETQ;
		else
		    CLRQ;
		break;
	    }
	    break;
	case 1:
	    tmp0 = arg1;
	    arg1 -= tmp2;
	    tmp1 = arg1 > tmp0;
	    switch (Q) {
	    case 0:
		if (tmp1 == 0)
		    SETQ;
		else
		    CLRQ;
		break;
	    case 1:
		if (tmp1)
		    SETQ;
		else
		    CLRQ;
		break;
	    }
	    break;
	}
	break;
    }
    if (Q == M)
	SETT;
    else
	CLRT;
    //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
    return arg1;
}

void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
    int64_t res;

    res = ((uint64_t) env->mach << 32) | env->macl;
    res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
    env->mach = (res >> 32) & 0xffffffff;
    env->macl = res & 0xffffffff;
    if (env->sr & SR_S) {
	if (res < 0)
	    env->mach |= 0xffff0000;
	else
	    env->mach &= 0x00007fff;
    }
}

void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
    int64_t res;

    res = ((uint64_t) env->mach << 32) | env->macl;
    res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
    env->mach = (res >> 32) & 0xffffffff;
    env->macl = res & 0xffffffff;
    if (env->sr & SR_S) {
	if (res < -0x80000000) {
	    env->mach = 1;
	    env->macl = 0x80000000;
	} else if (res > 0x000000007fffffff) {
	    env->mach = 1;
	    env->macl = 0x7fffffff;
	}
    }
}

uint32_t helper_subc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
    uint32_t tmp0, tmp1;

    tmp1 = arg1 - arg0;
    tmp0 = arg1;
    arg1 = tmp1 - (env->sr & SR_T);
    if (tmp0 < tmp1)
	env->sr |= SR_T;
    else
	env->sr &= ~SR_T;
    if (tmp1 < arg1)
	env->sr |= SR_T;
    return arg1;
}

uint32_t helper_subv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
    int32_t dest, src, ans;

    if ((int32_t) arg1 >= 0)
	dest = 0;
    else
	dest = 1;
    if ((int32_t) arg0 >= 0)
	src = 0;
    else
	src = 1;
    src += dest;
    arg1 -= arg0;
    if ((int32_t) arg1 >= 0)
	ans = 0;
    else
	ans = 1;
    ans += dest;
    if (src == 1) {
	if (ans == 1)
	    env->sr |= SR_T;
	else
	    env->sr &= ~SR_T;
    } else
	env->sr &= ~SR_T;
    return arg1;
}

static inline void set_t(CPUSH4State *env)
{
    env->sr |= SR_T;
}

static inline void clr_t(CPUSH4State *env)
{
    env->sr &= ~SR_T;
}

void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
{
    env->fpscr = val & FPSCR_MASK;
    if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
	set_float_rounding_mode(float_round_to_zero, &env->fp_status);
    } else {
	set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
    }
    set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
}

static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
{
    int xcpt, cause, enable;

    xcpt = get_float_exception_flags(&env->fp_status);

    /* Clear the flag entries */
    env->fpscr &= ~FPSCR_FLAG_MASK;

    if (unlikely(xcpt)) {
        if (xcpt & float_flag_invalid) {
            env->fpscr |= FPSCR_FLAG_V;
        }
        if (xcpt & float_flag_divbyzero) {
            env->fpscr |= FPSCR_FLAG_Z;
        }
        if (xcpt & float_flag_overflow) {
            env->fpscr |= FPSCR_FLAG_O;
        }
        if (xcpt & float_flag_underflow) {
            env->fpscr |= FPSCR_FLAG_U;
        }
        if (xcpt & float_flag_inexact) {
            env->fpscr |= FPSCR_FLAG_I;
        }

        /* Accumulate in cause entries */
        env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
                      << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);

        /* Generate an exception if enabled */
        cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
        enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
        if (cause & enable) {
            cpu_restore_state_from_retaddr(env, retaddr);
            env->exception_index = 0x120;
            cpu_loop_exit(env);
        }
    }
}

float32 helper_fabs_FT(float32 t0)
{
    return float32_abs(t0);
}

float64 helper_fabs_DT(float64 t0)
{
    return float64_abs(t0);
}

float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float32_add(t0, t1, &env->fp_status);
    update_fpscr(env, GETPC());
    return t0;
}

float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float64_add(t0, t1, &env->fp_status);
    update_fpscr(env, GETPC());
    return t0;
}

void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
{
    int relation;

    set_float_exception_flags(0, &env->fp_status);
    relation = float32_compare(t0, t1, &env->fp_status);
    if (unlikely(relation == float_relation_unordered)) {
        update_fpscr(env, GETPC());
    } else if (relation == float_relation_equal) {
        set_t(env);
    } else {
        clr_t(env);
    }
}

void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
{
    int relation;

    set_float_exception_flags(0, &env->fp_status);
    relation = float64_compare(t0, t1, &env->fp_status);
    if (unlikely(relation == float_relation_unordered)) {
        update_fpscr(env, GETPC());
    } else if (relation == float_relation_equal) {
        set_t(env);
    } else {
        clr_t(env);
    }
}

void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
{
    int relation;

    set_float_exception_flags(0, &env->fp_status);
    relation = float32_compare(t0, t1, &env->fp_status);
    if (unlikely(relation == float_relation_unordered)) {
        update_fpscr(env, GETPC());
    } else if (relation == float_relation_greater) {
        set_t(env);
    } else {
        clr_t(env);
    }
}

void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
{
    int relation;

    set_float_exception_flags(0, &env->fp_status);
    relation = float64_compare(t0, t1, &env->fp_status);
    if (unlikely(relation == float_relation_unordered)) {
        update_fpscr(env, GETPC());
    } else if (relation == float_relation_greater) {
        set_t(env);
    } else {
        clr_t(env);
    }
}

float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
{
    float64 ret;
    set_float_exception_flags(0, &env->fp_status);
    ret = float32_to_float64(t0, &env->fp_status);
    update_fpscr(env, GETPC());
    return ret;
}

float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
{
    float32 ret;
    set_float_exception_flags(0, &env->fp_status);
    ret = float64_to_float32(t0, &env->fp_status);
    update_fpscr(env, GETPC());
    return ret;
}

float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float32_div(t0, t1, &env->fp_status);
    update_fpscr(env, GETPC());
    return t0;
}

float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float64_div(t0, t1, &env->fp_status);
    update_fpscr(env, GETPC());
    return t0;
}

float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
{
    float32 ret;
    set_float_exception_flags(0, &env->fp_status);
    ret = int32_to_float32(t0, &env->fp_status);
    update_fpscr(env, GETPC());
    return ret;
}

float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
{
    float64 ret;
    set_float_exception_flags(0, &env->fp_status);
    ret = int32_to_float64(t0, &env->fp_status);
    update_fpscr(env, GETPC());
    return ret;
}

float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
    update_fpscr(env, GETPC());
    return t0;
}

float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float32_mul(t0, t1, &env->fp_status);
    update_fpscr(env, GETPC());
    return t0;
}

float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float64_mul(t0, t1, &env->fp_status);
    update_fpscr(env, GETPC());
    return t0;
}

float32 helper_fneg_T(float32 t0)
{
    return float32_chs(t0);
}

float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float32_sqrt(t0, &env->fp_status);
    update_fpscr(env, GETPC());
    return t0;
}

float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float64_sqrt(t0, &env->fp_status);
    update_fpscr(env, GETPC());
    return t0;
}

float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float32_sub(t0, t1, &env->fp_status);
    update_fpscr(env, GETPC());
    return t0;
}

float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float64_sub(t0, t1, &env->fp_status);
    update_fpscr(env, GETPC());
    return t0;
}

uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
{
    uint32_t ret;
    set_float_exception_flags(0, &env->fp_status);
    ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
    update_fpscr(env, GETPC());
    return ret;
}

uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
{
    uint32_t ret;
    set_float_exception_flags(0, &env->fp_status);
    ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
    update_fpscr(env, GETPC());
    return ret;
}

void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
{
    int bank, i;
    float32 r, p;

    bank = (env->sr & FPSCR_FR) ? 16 : 0;
    r = float32_zero;
    set_float_exception_flags(0, &env->fp_status);

    for (i = 0 ; i < 4 ; i++) {
        p = float32_mul(env->fregs[bank + m + i],
                        env->fregs[bank + n + i],
                        &env->fp_status);
        r = float32_add(r, p, &env->fp_status);
    }
    update_fpscr(env, GETPC());

    env->fregs[bank + n + 3] = r;
}

void helper_ftrv(CPUSH4State *env, uint32_t n)
{
    int bank_matrix, bank_vector;
    int i, j;
    float32 r[4];
    float32 p;

    bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
    bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
    set_float_exception_flags(0, &env->fp_status);
    for (i = 0 ; i < 4 ; i++) {
        r[i] = float32_zero;
        for (j = 0 ; j < 4 ; j++) {
            p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
                            env->fregs[bank_vector + j],
                            &env->fp_status);
            r[i] = float32_add(r[i], p, &env->fp_status);
        }
    }
    update_fpscr(env, GETPC());

    for (i = 0 ; i < 4 ; i++) {
        env->fregs[bank_vector + i] = r[i];
    }
}
Commit	Line	Data
fdf9b3e8 FB	1	/*
fdf9b3e8 FB	2	* SH4 emulation
5fafdf24	3	*
fdf9b3e8 FB	4	* Copyright (c) 2005 Samuel Tardieu
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
fdf9b3e8 FB	18	*/
fdf9b3e8 FB	19	#include <assert.h>
852d481f	20	#include <stdlib.h>
3e457172	21	#include "cpu.h"
a7812ae4	22	#include "helper.h"
fdf9b3e8	23
485d0035	24	static void cpu_restore_state_from_retaddr(CPUSH4State *env, uintptr_t retaddr)
21829e9b AJ	25	{
21829e9b AJ	26	TranslationBlock *tb;
21829e9b AJ	27
21829e9b AJ	28	if (retaddr) {
20503968	29	tb = tb_find_pc(retaddr);
21829e9b AJ	30	if (tb) {
	31	/* the PC is inside the translated code. It means that we have
	32	a virtual CPU fault */
20503968	33	cpu_restore_state(tb, env, retaddr);
21829e9b AJ	34	}
	35	}
	36	}
	37
fdf9b3e8	38	#ifndef CONFIG_USER_ONLY
3e457172	39	#include "softmmu_exec.h"
fdf9b3e8 FB	40
fdf9b3e8 FB	41	#define MMUSUFFIX _mmu
fdf9b3e8 FB	42
	43	#define SHIFT 0
	44	#include "softmmu_template.h"
	45
	46	#define SHIFT 1
	47	#include "softmmu_template.h"
	48
	49	#define SHIFT 2
	50	#include "softmmu_template.h"
	51
	52	#define SHIFT 3
	53	#include "softmmu_template.h"
	54
485d0035	55	void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
20503968	56	uintptr_t retaddr)
fdf9b3e8	57	{
fdf9b3e8 FB	58	int ret;
fdf9b3e8 FB	59
97b348e7	60	ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
fdf9b3e8	61	if (ret) {
21829e9b	62	/* now we have a real cpu fault */
485d0035	63	cpu_restore_state_from_retaddr(env, retaddr);
1162c041	64	cpu_loop_exit(env);
fdf9b3e8	65	}
fdf9b3e8 FB	66	}
	67
	68	#endif
	69
485d0035	70	void helper_ldtlb(CPUSH4State *env)
ea2b542a AJ	71	{
	72	#ifdef CONFIG_USER_ONLY
	73	/* XXXXX */
43dc2a64	74	cpu_abort(env, "Unhandled ldtlb");
ea2b542a AJ	75	#else
	76	cpu_load_tlb(env);
	77	#endif
	78	}
	79
485d0035 BS	80	static inline void raise_exception(CPUSH4State *env, int index,
485d0035 BS	81	uintptr_t retaddr)
e6afc2f4	82	{
fd4bab10	83	env->exception_index = index;
485d0035	84	cpu_restore_state_from_retaddr(env, retaddr);
1162c041	85	cpu_loop_exit(env);
e6afc2f4 AJ	86	}
e6afc2f4 AJ	87
485d0035	88	void helper_raise_illegal_instruction(CPUSH4State *env)
fd4bab10	89	{
485d0035	90	raise_exception(env, 0x180, GETPC());
fd4bab10 AJ	91	}
fd4bab10 AJ	92
485d0035	93	void helper_raise_slot_illegal_instruction(CPUSH4State *env)
e6afc2f4	94	{
485d0035	95	raise_exception(env, 0x1a0, GETPC());
e6afc2f4 AJ	96	}
e6afc2f4 AJ	97
485d0035	98	void helper_raise_fpu_disable(CPUSH4State *env)
d8299bcc	99	{
485d0035	100	raise_exception(env, 0x800, GETPC());
d8299bcc AJ	101	}
d8299bcc AJ	102
485d0035	103	void helper_raise_slot_fpu_disable(CPUSH4State *env)
d8299bcc	104	{
485d0035	105	raise_exception(env, 0x820, GETPC());
d8299bcc AJ	106	}
d8299bcc AJ	107
485d0035	108	void helper_debug(CPUSH4State *env)
e6afc2f4 AJ	109	{
e6afc2f4 AJ	110	env->exception_index = EXCP_DEBUG;
1162c041	111	cpu_loop_exit(env);
e6afc2f4 AJ	112	}
e6afc2f4 AJ	113
485d0035	114	void helper_sleep(CPUSH4State *env, uint32_t next_pc)
e6afc2f4 AJ	115	{
e6afc2f4 AJ	116	env->halted = 1;
efac4154	117	env->in_sleep = 1;
e6afc2f4	118	env->exception_index = EXCP_HLT;
f24f381b	119	env->pc = next_pc;
1162c041	120	cpu_loop_exit(env);
e6afc2f4 AJ	121	}
e6afc2f4 AJ	122
485d0035	123	void helper_trapa(CPUSH4State *env, uint32_t tra)
e6afc2f4 AJ	124	{
e6afc2f4 AJ	125	env->tra = tra << 2;
485d0035	126	raise_exception(env, 0x160, GETPC());
e6afc2f4 AJ	127	}
e6afc2f4 AJ	128
485d0035	129	void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
852d481f EI	130	{
	131	if (cpu_sh4_is_cached (env, address))
	132	{
	133	memory_content *r = malloc (sizeof(memory_content));
	134	r->address = address;
	135	r->value = value;
	136	r->next = NULL;
	137
	138	*(env->movcal_backup_tail) = r;
	139	env->movcal_backup_tail = &(r->next);
	140	}
	141	}
	142
485d0035	143	void helper_discard_movcal_backup(CPUSH4State *env)
852d481f EI	144	{
	145	memory_content *current = env->movcal_backup;
	146
	147	while(current)
	148	{
	149	memory_content *next = current->next;
	150	free (current);
	151	env->movcal_backup = current = next;
b9d38e95	152	if (current == NULL)
852d481f EI	153	env->movcal_backup_tail = &(env->movcal_backup);
	154	}
	155	}
	156
485d0035	157	void helper_ocbi(CPUSH4State *env, uint32_t address)
852d481f EI	158	{
	159	memory_content **current = &(env->movcal_backup);
	160	while (*current)
	161	{
	162	uint32_t a = (*current)->address;
	163	if ((a & ~0x1F) == (address & ~0x1F))
	164	{
	165	memory_content next = (current)->next;
485d0035	166	cpu_stl_data(env, a, (*current)->value);
852d481f	167
b9d38e95	168	if (next == NULL)
852d481f EI	169	{
	170	env->movcal_backup_tail = current;
	171	}
	172
	173	free (*current);
	174	*current = next;
	175	break;
	176	}
	177	}
	178	}
	179
485d0035	180	uint32_t helper_addc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	181	{
	182	uint32_t tmp0, tmp1;
	183
6f06939b AJ	184	tmp1 = arg0 + arg1;
	185	tmp0 = arg1;
	186	arg1 = tmp1 + (env->sr & 1);
fdf9b3e8 FB	187	if (tmp0 > tmp1)
	188	env->sr \|= SR_T;
	189	else
	190	env->sr &= ~SR_T;
6f06939b	191	if (tmp1 > arg1)
fdf9b3e8	192	env->sr \|= SR_T;
6f06939b	193	return arg1;
fdf9b3e8 FB	194	}
fdf9b3e8 FB	195
485d0035	196	uint32_t helper_addv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	197	{
	198	uint32_t dest, src, ans;
	199
6f06939b	200	if ((int32_t) arg1 >= 0)
fdf9b3e8 FB	201	dest = 0;
	202	else
	203	dest = 1;
6f06939b	204	if ((int32_t) arg0 >= 0)
fdf9b3e8 FB	205	src = 0;
	206	else
	207	src = 1;
	208	src += dest;
6f06939b AJ	209	arg1 += arg0;
6f06939b AJ	210	if ((int32_t) arg1 >= 0)
fdf9b3e8 FB	211	ans = 0;
	212	else
	213	ans = 1;
	214	ans += dest;
	215	if (src == 0 \|\| src == 2) {
	216	if (ans == 1)
	217	env->sr \|= SR_T;
	218	else
	219	env->sr &= ~SR_T;
	220	} else
	221	env->sr &= ~SR_T;
6f06939b	222	return arg1;
fdf9b3e8 FB	223	}
	224
	225	#define T (env->sr & SR_T)
	226	#define Q (env->sr & SR_Q ? 1 : 0)
	227	#define M (env->sr & SR_M ? 1 : 0)
	228	#define SETT env->sr \|= SR_T
	229	#define CLRT env->sr &= ~SR_T
	230	#define SETQ env->sr \|= SR_Q
	231	#define CLRQ env->sr &= ~SR_Q
	232	#define SETM env->sr \|= SR_M
	233	#define CLRM env->sr &= ~SR_M
	234
485d0035	235	uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	236	{
	237	uint32_t tmp0, tmp2;
	238	uint8_t old_q, tmp1 = 0xff;
	239
69d6275b	240	//printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
fdf9b3e8	241	old_q = Q;
69d6275b	242	if ((0x80000000 & arg1) != 0)
fdf9b3e8 FB	243	SETQ;
	244	else
	245	CLRQ;
69d6275b AJ	246	tmp2 = arg0;
	247	arg1 <<= 1;
	248	arg1 \|= T;
fdf9b3e8 FB	249	switch (old_q) {
	250	case 0:
	251	switch (M) {
	252	case 0:
69d6275b AJ	253	tmp0 = arg1;
	254	arg1 -= tmp2;
	255	tmp1 = arg1 > tmp0;
fdf9b3e8 FB	256	switch (Q) {
	257	case 0:
	258	if (tmp1)
	259	SETQ;
	260	else
	261	CLRQ;
	262	break;
	263	case 1:
	264	if (tmp1 == 0)
	265	SETQ;
	266	else
	267	CLRQ;
	268	break;
	269	}
	270	break;
	271	case 1:
69d6275b AJ	272	tmp0 = arg1;
	273	arg1 += tmp2;
	274	tmp1 = arg1 < tmp0;
fdf9b3e8 FB	275	switch (Q) {
	276	case 0:
	277	if (tmp1 == 0)
	278	SETQ;
	279	else
	280	CLRQ;
	281	break;
	282	case 1:
	283	if (tmp1)
	284	SETQ;
	285	else
	286	CLRQ;
	287	break;
	288	}
	289	break;
	290	}
	291	break;
	292	case 1:
	293	switch (M) {
	294	case 0:
69d6275b AJ	295	tmp0 = arg1;
	296	arg1 += tmp2;
	297	tmp1 = arg1 < tmp0;
fdf9b3e8 FB	298	switch (Q) {
	299	case 0:
	300	if (tmp1)
	301	SETQ;
	302	else
	303	CLRQ;
	304	break;
	305	case 1:
	306	if (tmp1 == 0)
	307	SETQ;
	308	else
	309	CLRQ;
	310	break;
	311	}
	312	break;
	313	case 1:
69d6275b AJ	314	tmp0 = arg1;
	315	arg1 -= tmp2;
	316	tmp1 = arg1 > tmp0;
fdf9b3e8 FB	317	switch (Q) {
	318	case 0:
	319	if (tmp1 == 0)
	320	SETQ;
	321	else
	322	CLRQ;
	323	break;
	324	case 1:
	325	if (tmp1)
	326	SETQ;
	327	else
	328	CLRQ;
	329	break;
	330	}
	331	break;
	332	}
	333	break;
	334	}
	335	if (Q == M)
	336	SETT;
	337	else
	338	CLRT;
69d6275b AJ	339	//printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
69d6275b AJ	340	return arg1;
fdf9b3e8 FB	341	}
fdf9b3e8 FB	342
485d0035	343	void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	344	{
	345	int64_t res;
	346
	347	res = ((uint64_t) env->mach << 32) \| env->macl;
6f06939b	348	res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
fdf9b3e8 FB	349	env->mach = (res >> 32) & 0xffffffff;
	350	env->macl = res & 0xffffffff;
	351	if (env->sr & SR_S) {
	352	if (res < 0)
	353	env->mach \|= 0xffff0000;
	354	else
	355	env->mach &= 0x00007fff;
	356	}
	357	}
	358
485d0035	359	void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	360	{
	361	int64_t res;
	362
	363	res = ((uint64_t) env->mach << 32) \| env->macl;
6f06939b	364	res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
fdf9b3e8 FB	365	env->mach = (res >> 32) & 0xffffffff;
	366	env->macl = res & 0xffffffff;
	367	if (env->sr & SR_S) {
	368	if (res < -0x80000000) {
	369	env->mach = 1;
	370	env->macl = 0x80000000;
	371	} else if (res > 0x000000007fffffff) {
	372	env->mach = 1;
	373	env->macl = 0x7fffffff;
	374	}
	375	}
	376	}
	377
485d0035	378	uint32_t helper_subc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	379	{
	380	uint32_t tmp0, tmp1;
	381
6f06939b AJ	382	tmp1 = arg1 - arg0;
	383	tmp0 = arg1;
	384	arg1 = tmp1 - (env->sr & SR_T);
fdf9b3e8 FB	385	if (tmp0 < tmp1)
	386	env->sr \|= SR_T;
	387	else
	388	env->sr &= ~SR_T;
6f06939b	389	if (tmp1 < arg1)
fdf9b3e8	390	env->sr \|= SR_T;
6f06939b	391	return arg1;
fdf9b3e8 FB	392	}
fdf9b3e8 FB	393
485d0035	394	uint32_t helper_subv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	395	{
	396	int32_t dest, src, ans;
	397
6f06939b	398	if ((int32_t) arg1 >= 0)
fdf9b3e8 FB	399	dest = 0;
	400	else
	401	dest = 1;
6f06939b	402	if ((int32_t) arg0 >= 0)
fdf9b3e8 FB	403	src = 0;
	404	else
	405	src = 1;
	406	src += dest;
6f06939b AJ	407	arg1 -= arg0;
6f06939b AJ	408	if ((int32_t) arg1 >= 0)
fdf9b3e8 FB	409	ans = 0;
	410	else
	411	ans = 1;
	412	ans += dest;
	413	if (src == 1) {
	414	if (ans == 1)
	415	env->sr \|= SR_T;
	416	else
	417	env->sr &= ~SR_T;
	418	} else
	419	env->sr &= ~SR_T;
6f06939b	420	return arg1;
fdf9b3e8 FB	421	}
fdf9b3e8 FB	422
485d0035	423	static inline void set_t(CPUSH4State *env)
cc4ba6a9 AJ	424	{
	425	env->sr \|= SR_T;
	426	}
	427
485d0035	428	static inline void clr_t(CPUSH4State *env)
cc4ba6a9 AJ	429	{
	430	env->sr &= ~SR_T;
	431	}
	432
485d0035	433	void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
390af821	434	{
26ac1ea5 AJ	435	env->fpscr = val & FPSCR_MASK;
26ac1ea5 AJ	436	if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
390af821	437	set_float_rounding_mode(float_round_to_zero, &env->fp_status);
26ac1ea5	438	} else {
390af821	439	set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
26ac1ea5	440	}
a0d4ac33	441	set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
390af821	442	}
cc4ba6a9	443
485d0035	444	static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
21829e9b AJ	445	{
	446	int xcpt, cause, enable;
	447
	448	xcpt = get_float_exception_flags(&env->fp_status);
	449
	450	/* Clear the flag entries */
	451	env->fpscr &= ~FPSCR_FLAG_MASK;
	452
	453	if (unlikely(xcpt)) {
	454	if (xcpt & float_flag_invalid) {
	455	env->fpscr \|= FPSCR_FLAG_V;
	456	}
	457	if (xcpt & float_flag_divbyzero) {
	458	env->fpscr \|= FPSCR_FLAG_Z;
	459	}
	460	if (xcpt & float_flag_overflow) {
	461	env->fpscr \|= FPSCR_FLAG_O;
	462	}
	463	if (xcpt & float_flag_underflow) {
	464	env->fpscr \|= FPSCR_FLAG_U;
	465	}
	466	if (xcpt & float_flag_inexact) {
	467	env->fpscr \|= FPSCR_FLAG_I;
	468	}
	469
	470	/* Accumulate in cause entries */
	471	env->fpscr \|= (env->fpscr & FPSCR_FLAG_MASK)
	472	<< (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
	473
	474	/* Generate an exception if enabled */
	475	cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
	476	enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
	477	if (cause & enable) {
485d0035	478	cpu_restore_state_from_retaddr(env, retaddr);
21829e9b	479	env->exception_index = 0x120;
1162c041	480	cpu_loop_exit(env);
21829e9b AJ	481	}
	482	}
	483	}
	484
d6c424c5	485	float32 helper_fabs_FT(float32 t0)
cc4ba6a9	486	{
d6c424c5	487	return float32_abs(t0);
cc4ba6a9 AJ	488	}
cc4ba6a9 AJ	489
d6c424c5	490	float64 helper_fabs_DT(float64 t0)
cc4ba6a9	491	{
d6c424c5	492	return float64_abs(t0);
cc4ba6a9 AJ	493	}
cc4ba6a9 AJ	494
485d0035	495	float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
cc4ba6a9	496	{
21829e9b	497	set_float_exception_flags(0, &env->fp_status);
d6c424c5	498	t0 = float32_add(t0, t1, &env->fp_status);
485d0035	499	update_fpscr(env, GETPC());
d6c424c5	500	return t0;
cc4ba6a9 AJ	501	}
cc4ba6a9 AJ	502
485d0035	503	float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
cc4ba6a9	504	{
21829e9b	505	set_float_exception_flags(0, &env->fp_status);
d6c424c5	506	t0 = float64_add(t0, t1, &env->fp_status);
485d0035	507	update_fpscr(env, GETPC());
d6c424c5	508	return t0;
cc4ba6a9 AJ	509	}
cc4ba6a9 AJ	510
485d0035	511	void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
cc4ba6a9	512	{
21829e9b	513	int relation;
9850d1e8	514
21829e9b	515	set_float_exception_flags(0, &env->fp_status);
d6c424c5	516	relation = float32_compare(t0, t1, &env->fp_status);
21829e9b	517	if (unlikely(relation == float_relation_unordered)) {
485d0035	518	update_fpscr(env, GETPC());
21829e9b	519	} else if (relation == float_relation_equal) {
485d0035	520	set_t(env);
21829e9b	521	} else {
485d0035	522	clr_t(env);
21829e9b	523	}
cc4ba6a9 AJ	524	}
cc4ba6a9 AJ	525
485d0035	526	void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
cc4ba6a9	527	{
21829e9b	528	int relation;
9850d1e8	529
21829e9b	530	set_float_exception_flags(0, &env->fp_status);
d6c424c5	531	relation = float64_compare(t0, t1, &env->fp_status);
21829e9b	532	if (unlikely(relation == float_relation_unordered)) {
485d0035	533	update_fpscr(env, GETPC());
21829e9b	534	} else if (relation == float_relation_equal) {
485d0035	535	set_t(env);
21829e9b	536	} else {
485d0035	537	clr_t(env);
21829e9b	538	}
cc4ba6a9 AJ	539	}
cc4ba6a9 AJ	540
485d0035	541	void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
cc4ba6a9	542	{
21829e9b	543	int relation;
9850d1e8	544
21829e9b	545	set_float_exception_flags(0, &env->fp_status);
d6c424c5	546	relation = float32_compare(t0, t1, &env->fp_status);
21829e9b	547	if (unlikely(relation == float_relation_unordered)) {
485d0035	548	update_fpscr(env, GETPC());
21829e9b	549	} else if (relation == float_relation_greater) {
485d0035	550	set_t(env);
21829e9b	551	} else {
485d0035	552	clr_t(env);
21829e9b	553	}
cc4ba6a9 AJ	554	}
cc4ba6a9 AJ	555
485d0035	556	void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
cc4ba6a9	557	{
21829e9b	558	int relation;
9850d1e8	559
21829e9b	560	set_float_exception_flags(0, &env->fp_status);
d6c424c5	561	relation = float64_compare(t0, t1, &env->fp_status);
21829e9b	562	if (unlikely(relation == float_relation_unordered)) {
485d0035	563	update_fpscr(env, GETPC());
21829e9b	564	} else if (relation == float_relation_greater) {
485d0035	565	set_t(env);
21829e9b	566	} else {
485d0035	567	clr_t(env);
21829e9b	568	}
cc4ba6a9 AJ	569	}
cc4ba6a9 AJ	570
485d0035	571	float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
cc4ba6a9	572	{
d6c424c5	573	float64 ret;
21829e9b	574	set_float_exception_flags(0, &env->fp_status);
d6c424c5	575	ret = float32_to_float64(t0, &env->fp_status);
485d0035	576	update_fpscr(env, GETPC());
d6c424c5	577	return ret;
cc4ba6a9 AJ	578	}
cc4ba6a9 AJ	579
485d0035	580	float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
cc4ba6a9	581	{
d6c424c5	582	float32 ret;
21829e9b	583	set_float_exception_flags(0, &env->fp_status);
d6c424c5	584	ret = float64_to_float32(t0, &env->fp_status);
485d0035	585	update_fpscr(env, GETPC());
d6c424c5	586	return ret;
cc4ba6a9 AJ	587	}
cc4ba6a9 AJ	588
485d0035	589	float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
cc4ba6a9	590	{
21829e9b	591	set_float_exception_flags(0, &env->fp_status);
d6c424c5	592	t0 = float32_div(t0, t1, &env->fp_status);
485d0035	593	update_fpscr(env, GETPC());
d6c424c5	594	return t0;
cc4ba6a9 AJ	595	}
cc4ba6a9 AJ	596
485d0035	597	float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
cc4ba6a9	598	{
21829e9b	599	set_float_exception_flags(0, &env->fp_status);
d6c424c5	600	t0 = float64_div(t0, t1, &env->fp_status);
485d0035	601	update_fpscr(env, GETPC());
d6c424c5	602	return t0;
cc4ba6a9 AJ	603	}
cc4ba6a9 AJ	604
485d0035	605	float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
cc4ba6a9	606	{
d6c424c5	607	float32 ret;
21829e9b	608	set_float_exception_flags(0, &env->fp_status);
d6c424c5	609	ret = int32_to_float32(t0, &env->fp_status);
485d0035	610	update_fpscr(env, GETPC());
d6c424c5	611	return ret;
cc4ba6a9 AJ	612	}
cc4ba6a9 AJ	613
485d0035	614	float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
cc4ba6a9	615	{
d6c424c5	616	float64 ret;
21829e9b	617	set_float_exception_flags(0, &env->fp_status);
d6c424c5	618	ret = int32_to_float64(t0, &env->fp_status);
485d0035	619	update_fpscr(env, GETPC());
d6c424c5	620	return ret;
cc4ba6a9 AJ	621	}
cc4ba6a9 AJ	622
485d0035	623	float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
5b7141a1	624	{
21829e9b	625	set_float_exception_flags(0, &env->fp_status);
ff2086fe	626	t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
485d0035	627	update_fpscr(env, GETPC());
d6c424c5	628	return t0;
5b7141a1 AJ	629	}
5b7141a1 AJ	630
485d0035	631	float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
cc4ba6a9	632	{
21829e9b	633	set_float_exception_flags(0, &env->fp_status);
d6c424c5	634	t0 = float32_mul(t0, t1, &env->fp_status);
485d0035	635	update_fpscr(env, GETPC());
d6c424c5	636	return t0;
cc4ba6a9 AJ	637	}
cc4ba6a9 AJ	638
485d0035	639	float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
cc4ba6a9	640	{
21829e9b	641	set_float_exception_flags(0, &env->fp_status);
d6c424c5	642	t0 = float64_mul(t0, t1, &env->fp_status);
485d0035	643	update_fpscr(env, GETPC());
d6c424c5	644	return t0;
cc4ba6a9 AJ	645	}
cc4ba6a9 AJ	646
d6c424c5	647	float32 helper_fneg_T(float32 t0)
7fdf924f	648	{
d6c424c5	649	return float32_chs(t0);
7fdf924f AJ	650	}
7fdf924f AJ	651
485d0035	652	float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
cc4ba6a9	653	{
21829e9b	654	set_float_exception_flags(0, &env->fp_status);
d6c424c5	655	t0 = float32_sqrt(t0, &env->fp_status);
485d0035	656	update_fpscr(env, GETPC());
d6c424c5	657	return t0;
cc4ba6a9 AJ	658	}
cc4ba6a9 AJ	659
485d0035	660	float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
cc4ba6a9	661	{
21829e9b	662	set_float_exception_flags(0, &env->fp_status);
d6c424c5	663	t0 = float64_sqrt(t0, &env->fp_status);
485d0035	664	update_fpscr(env, GETPC());
d6c424c5	665	return t0;
cc4ba6a9 AJ	666	}
cc4ba6a9 AJ	667
485d0035	668	float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
cc4ba6a9	669	{
21829e9b	670	set_float_exception_flags(0, &env->fp_status);
d6c424c5	671	t0 = float32_sub(t0, t1, &env->fp_status);
485d0035	672	update_fpscr(env, GETPC());
d6c424c5	673	return t0;
cc4ba6a9 AJ	674	}
cc4ba6a9 AJ	675
485d0035	676	float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
cc4ba6a9	677	{
21829e9b	678	set_float_exception_flags(0, &env->fp_status);
d6c424c5	679	t0 = float64_sub(t0, t1, &env->fp_status);
485d0035	680	update_fpscr(env, GETPC());
d6c424c5	681	return t0;
cc4ba6a9 AJ	682	}
cc4ba6a9 AJ	683
485d0035	684	uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
cc4ba6a9	685	{
21829e9b	686	uint32_t ret;
21829e9b	687	set_float_exception_flags(0, &env->fp_status);
d6c424c5	688	ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
485d0035	689	update_fpscr(env, GETPC());
21829e9b	690	return ret;
cc4ba6a9 AJ	691	}
cc4ba6a9 AJ	692
485d0035	693	uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
cc4ba6a9	694	{
21829e9b	695	uint32_t ret;
21829e9b	696	set_float_exception_flags(0, &env->fp_status);
d6c424c5	697	ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
485d0035	698	update_fpscr(env, GETPC());
21829e9b	699	return ret;
cc4ba6a9	700	}
af8c2bde	701
485d0035	702	void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
af8c2bde AJ	703	{
	704	int bank, i;
	705	float32 r, p;
	706
	707	bank = (env->sr & FPSCR_FR) ? 16 : 0;
	708	r = float32_zero;
	709	set_float_exception_flags(0, &env->fp_status);
	710
	711	for (i = 0 ; i < 4 ; i++) {
	712	p = float32_mul(env->fregs[bank + m + i],
	713	env->fregs[bank + n + i],
	714	&env->fp_status);
	715	r = float32_add(r, p, &env->fp_status);
	716	}
485d0035	717	update_fpscr(env, GETPC());
af8c2bde AJ	718
	719	env->fregs[bank + n + 3] = r;
	720	}
17075f10	721
485d0035	722	void helper_ftrv(CPUSH4State *env, uint32_t n)
17075f10 AJ	723	{
	724	int bank_matrix, bank_vector;
	725	int i, j;
	726	float32 r[4];
	727	float32 p;
	728
	729	bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
	730	bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
	731	set_float_exception_flags(0, &env->fp_status);
	732	for (i = 0 ; i < 4 ; i++) {
	733	r[i] = float32_zero;
	734	for (j = 0 ; j < 4 ; j++) {
	735	p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
	736	env->fregs[bank_vector + j],
	737	&env->fp_status);
	738	r[i] = float32_add(r[i], p, &env->fp_status);
	739	}
	740	}
485d0035	741	update_fpscr(env, GETPC());
17075f10 AJ	742
	743	for (i = 0 ; i < 4 ; i++) {
	744	env->fregs[bank_vector + i] = r[i];
	745	}
	746	}