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Commit | Line | Data |
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a9f49946 IY |
1 | /* |
2 | * pcie_host.c | |
3 | * utility functions for pci express host bridge. | |
4 | * | |
5 | * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> | |
6 | * VA Linux Systems Japan K.K. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | ||
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | ||
18 | * You should have received a copy of the GNU General Public License along | |
70539e18 | 19 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
a9f49946 IY |
20 | */ |
21 | ||
c759b24f MT |
22 | #include "hw/hw.h" |
23 | #include "hw/pci/pci.h" | |
24 | #include "hw/pci/pcie_host.h" | |
022c62cb | 25 | #include "exec/address-spaces.h" |
a9f49946 | 26 | |
a9f49946 | 27 | /* a helper function to get a PCIDevice for a given mmconfig address */ |
8d6514f8 IY |
28 | static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s, |
29 | uint32_t mmcfg_addr) | |
a9f49946 IY |
30 | { |
31 | return pci_find_device(s, PCIE_MMCFG_BUS(mmcfg_addr), | |
5256d8bf | 32 | PCIE_MMCFG_DEVFN(mmcfg_addr)); |
a9f49946 IY |
33 | } |
34 | ||
a8170e5e | 35 | static void pcie_mmcfg_data_write(void *opaque, hwaddr mmcfg_addr, |
c76f990e | 36 | uint64_t val, unsigned len) |
a9f49946 | 37 | { |
c76f990e AK |
38 | PCIExpressHost *e = opaque; |
39 | PCIBus *s = e->pci.bus; | |
8d6514f8 | 40 | PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); |
43e86c8f IY |
41 | uint32_t addr; |
42 | uint32_t limit; | |
a9f49946 | 43 | |
42e4126b | 44 | if (!pci_dev) { |
a9f49946 | 45 | return; |
42e4126b | 46 | } |
43e86c8f IY |
47 | addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr); |
48 | limit = pci_config_size(pci_dev); | |
49 | if (limit <= addr) { | |
50 | /* conventional pci device can be behind pcie-to-pci bridge. | |
51 | 256 <= addr < 4K has no effects. */ | |
52 | return; | |
53 | } | |
54 | pci_host_config_write_common(pci_dev, addr, limit, val, len); | |
a9f49946 IY |
55 | } |
56 | ||
c76f990e | 57 | static uint64_t pcie_mmcfg_data_read(void *opaque, |
a8170e5e | 58 | hwaddr mmcfg_addr, |
c76f990e | 59 | unsigned len) |
a9f49946 | 60 | { |
c76f990e AK |
61 | PCIExpressHost *e = opaque; |
62 | PCIBus *s = e->pci.bus; | |
43e86c8f IY |
63 | PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); |
64 | uint32_t addr; | |
65 | uint32_t limit; | |
a9f49946 IY |
66 | |
67 | if (!pci_dev) { | |
4677d8ed | 68 | return ~0x0; |
a9f49946 | 69 | } |
43e86c8f IY |
70 | addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr); |
71 | limit = pci_config_size(pci_dev); | |
72 | if (limit <= addr) { | |
73 | /* conventional pci device can be behind pcie-to-pci bridge. | |
74 | 256 <= addr < 4K has no effects. */ | |
75 | return ~0x0; | |
76 | } | |
77 | return pci_host_config_read_common(pci_dev, addr, limit, len); | |
a9f49946 IY |
78 | } |
79 | ||
c76f990e AK |
80 | static const MemoryRegionOps pcie_mmcfg_ops = { |
81 | .read = pcie_mmcfg_data_read, | |
82 | .write = pcie_mmcfg_data_write, | |
83 | .endianness = DEVICE_NATIVE_ENDIAN, | |
a9f49946 IY |
84 | }; |
85 | ||
c702ddb8 | 86 | int pcie_host_init(PCIExpressHost *e) |
a9f49946 IY |
87 | { |
88 | e->base_addr = PCIE_BASE_ADDR_UNMAPPED; | |
a9f49946 IY |
89 | |
90 | return 0; | |
91 | } | |
92 | ||
93 | void pcie_host_mmcfg_unmap(PCIExpressHost *e) | |
94 | { | |
95 | if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) { | |
c76f990e | 96 | memory_region_del_subregion(get_system_memory(), &e->mmio); |
c702ddb8 | 97 | memory_region_destroy(&e->mmio); |
a9f49946 IY |
98 | e->base_addr = PCIE_BASE_ADDR_UNMAPPED; |
99 | } | |
100 | } | |
101 | ||
c702ddb8 JB |
102 | void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr, |
103 | uint32_t size) | |
a9f49946 | 104 | { |
c702ddb8 JB |
105 | assert(!(size & (size - 1))); /* power of 2 */ |
106 | assert(size >= PCIE_MMCFG_SIZE_MIN); | |
107 | assert(size <= PCIE_MMCFG_SIZE_MAX); | |
108 | e->size = size; | |
40c5dce9 PB |
109 | memory_region_init_io(&e->mmio, OBJECT(e), &pcie_mmcfg_ops, e, |
110 | "pcie-mmcfg", e->size); | |
a9f49946 | 111 | e->base_addr = addr; |
c76f990e | 112 | memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio); |
a9f49946 IY |
113 | } |
114 | ||
115 | void pcie_host_mmcfg_update(PCIExpressHost *e, | |
116 | int enable, | |
c702ddb8 JB |
117 | hwaddr addr, |
118 | uint32_t size) | |
a9f49946 IY |
119 | { |
120 | pcie_host_mmcfg_unmap(e); | |
121 | if (enable) { | |
c702ddb8 | 122 | pcie_host_mmcfg_map(e, addr, size); |
a9f49946 IY |
123 | } |
124 | } | |
bc927e48 JB |
125 | |
126 | static const TypeInfo pcie_host_type_info = { | |
127 | .name = TYPE_PCIE_HOST_BRIDGE, | |
128 | .parent = TYPE_PCI_HOST_BRIDGE, | |
129 | .abstract = true, | |
130 | .instance_size = sizeof(PCIExpressHost), | |
131 | }; | |
132 | ||
133 | static void pcie_host_register_types(void) | |
134 | { | |
135 | type_register_static(&pcie_host_type_info); | |
136 | } | |
137 | ||
138 | type_init(pcie_host_register_types) |