[qemu.git] / hw / apic_common.c

/*
 *  APIC support - common bits of emulated and KVM kernel model
 *
 *  Copyright (c) 2004-2005 Fabrice Bellard
 *  Copyright (c) 2011      Jan Kiszka, Siemens AG
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>
 */
#include "apic.h"
#include "apic_internal.h"
#include "trace.h"
#include "kvm.h"

static int apic_irq_delivered;
bool apic_report_tpr_access;

void cpu_set_apic_base(DeviceState *d, uint64_t val)
{
    trace_cpu_set_apic_base(val);

    if (d) {
        APICCommonState *s = APIC_COMMON(d);
        APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
        info->set_base(s, val);
    }
}

uint64_t cpu_get_apic_base(DeviceState *d)
{
    if (d) {
        APICCommonState *s = APIC_COMMON(d);
        trace_cpu_get_apic_base((uint64_t)s->apicbase);
        return s->apicbase;
    } else {
        trace_cpu_get_apic_base(0);
        return 0;
    }
}

void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
{
    APICCommonState *s;
    APICCommonClass *info;

    if (!d) {
        return;
    }

    s = APIC_COMMON(d);
    info = APIC_COMMON_GET_CLASS(s);

    info->set_tpr(s, val);
}

uint8_t cpu_get_apic_tpr(DeviceState *d)
{
    APICCommonState *s;
    APICCommonClass *info;

    if (!d) {
        return 0;
    }

    s = APIC_COMMON(d);
    info = APIC_COMMON_GET_CLASS(s);

    return info->get_tpr(s);
}

void apic_enable_tpr_access_reporting(DeviceState *d, bool enable)
{
    APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);

    apic_report_tpr_access = enable;
    if (info->enable_tpr_reporting) {
        info->enable_tpr_reporting(s, enable);
    }
}

void apic_enable_vapic(DeviceState *d, target_phys_addr_t paddr)
{
    APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);

    s->vapic_paddr = paddr;
    info->vapic_base_update(s);
}

void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
                                   TPRAccess access)
{
    APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);

    vapic_report_tpr_access(s->vapic, s->cpu_env, ip, access);
}

void apic_report_irq_delivered(int delivered)
{
    apic_irq_delivered += delivered;

    trace_apic_report_irq_delivered(apic_irq_delivered);
}

void apic_reset_irq_delivered(void)
{
    trace_apic_reset_irq_delivered(apic_irq_delivered);

    apic_irq_delivered = 0;
}

int apic_get_irq_delivered(void)
{
    trace_apic_get_irq_delivered(apic_irq_delivered);

    return apic_irq_delivered;
}

void apic_deliver_nmi(DeviceState *d)
{
    APICCommonState *s = APIC_COMMON(d);
    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);

    info->external_nmi(s);
}

bool apic_next_timer(APICCommonState *s, int64_t current_time)
{
    int64_t d;

    /* We need to store the timer state separately to support APIC
     * implementations that maintain a non-QEMU timer, e.g. inside the
     * host kernel. This open-coded state allows us to migrate between
     * both models. */
    s->timer_expiry = -1;

    if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
        return false;
    }

    d = (current_time - s->initial_count_load_time) >> s->count_shift;

    if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
        if (!s->initial_count) {
            return false;
        }
        d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
            ((uint64_t)s->initial_count + 1);
    } else {
        if (d >= s->initial_count) {
            return false;
        }
        d = (uint64_t)s->initial_count + 1;
    }
    s->next_time = s->initial_count_load_time + (d << s->count_shift);
    s->timer_expiry = s->next_time;
    return true;
}

void apic_init_reset(DeviceState *d)
{
    APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
    int i;

    if (!s) {
        return;
    }
    s->tpr = 0;
    s->spurious_vec = 0xff;
    s->log_dest = 0;
    s->dest_mode = 0xf;
    memset(s->isr, 0, sizeof(s->isr));
    memset(s->tmr, 0, sizeof(s->tmr));
    memset(s->irr, 0, sizeof(s->irr));
    for (i = 0; i < APIC_LVT_NB; i++) {
        s->lvt[i] = APIC_LVT_MASKED;
    }
    s->esr = 0;
    memset(s->icr, 0, sizeof(s->icr));
    s->divide_conf = 0;
    s->count_shift = 0;
    s->initial_count = 0;
    s->initial_count_load_time = 0;
    s->next_time = 0;
    s->wait_for_sipi = 1;

    if (s->timer) {
        qemu_del_timer(s->timer);
    }
    s->timer_expiry = -1;
}

static void apic_reset_common(DeviceState *d)
{
    APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
    bool bsp;

    bsp = cpu_is_bsp(s->cpu_env);
    s->apicbase = 0xfee00000 |
        (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;

    s->vapic_paddr = 0;
    info->vapic_base_update(s);

    apic_init_reset(d);

    if (bsp) {
        /*
         * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
         * time typically by BIOS, so PIC interrupt can be delivered to the
         * processor when local APIC is enabled.
         */
        s->lvt[APIC_LVT_LINT0] = 0x700;
    }
}

/* This function is only used for old state version 1 and 2 */
static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
{
    APICCommonState *s = opaque;
    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
    int i;

    if (version_id > 2) {
        return -EINVAL;
    }

    /* XXX: what if the base changes? (registered memory regions) */
    qemu_get_be32s(f, &s->apicbase);
    qemu_get_8s(f, &s->id);
    qemu_get_8s(f, &s->arb_id);
    qemu_get_8s(f, &s->tpr);
    qemu_get_be32s(f, &s->spurious_vec);
    qemu_get_8s(f, &s->log_dest);
    qemu_get_8s(f, &s->dest_mode);
    for (i = 0; i < 8; i++) {
        qemu_get_be32s(f, &s->isr[i]);
        qemu_get_be32s(f, &s->tmr[i]);
        qemu_get_be32s(f, &s->irr[i]);
    }
    for (i = 0; i < APIC_LVT_NB; i++) {
        qemu_get_be32s(f, &s->lvt[i]);
    }
    qemu_get_be32s(f, &s->esr);
    qemu_get_be32s(f, &s->icr[0]);
    qemu_get_be32s(f, &s->icr[1]);
    qemu_get_be32s(f, &s->divide_conf);
    s->count_shift = qemu_get_be32(f);
    qemu_get_be32s(f, &s->initial_count);
    s->initial_count_load_time = qemu_get_be64(f);
    s->next_time = qemu_get_be64(f);

    if (version_id >= 2) {
        s->timer_expiry = qemu_get_be64(f);
    }

    if (info->post_load) {
        info->post_load(s);
    }
    return 0;
}

static int apic_init_common(SysBusDevice *dev)
{
    APICCommonState *s = APIC_COMMON(dev);
    APICCommonClass *info;
    static DeviceState *vapic;
    static int apic_no;

    if (apic_no >= MAX_APICS) {
        return -1;
    }
    s->idx = apic_no++;

    info = APIC_COMMON_GET_CLASS(s);
    info->init(s);

    sysbus_init_mmio(dev, &s->io_memory);

    if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK) {
        vapic = sysbus_create_simple("kvmvapic", -1, NULL);
    }
    s->vapic = vapic;
    if (apic_report_tpr_access && info->enable_tpr_reporting) {
        info->enable_tpr_reporting(s, true);
    }

    return 0;
}

static void apic_dispatch_pre_save(void *opaque)
{
    APICCommonState *s = APIC_COMMON(opaque);
    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);

    if (info->pre_save) {
        info->pre_save(s);
    }
}

static int apic_dispatch_post_load(void *opaque, int version_id)
{
    APICCommonState *s = APIC_COMMON(opaque);
    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);

    if (info->post_load) {
        info->post_load(s);
    }
    return 0;
}

static const VMStateDescription vmstate_apic_common = {
    .name = "apic",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 1,
    .load_state_old = apic_load_old,
    .pre_save = apic_dispatch_pre_save,
    .post_load = apic_dispatch_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(apicbase, APICCommonState),
        VMSTATE_UINT8(id, APICCommonState),
        VMSTATE_UINT8(arb_id, APICCommonState),
        VMSTATE_UINT8(tpr, APICCommonState),
        VMSTATE_UINT32(spurious_vec, APICCommonState),
        VMSTATE_UINT8(log_dest, APICCommonState),
        VMSTATE_UINT8(dest_mode, APICCommonState),
        VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
        VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
        VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
        VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
        VMSTATE_UINT32(esr, APICCommonState),
        VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
        VMSTATE_UINT32(divide_conf, APICCommonState),
        VMSTATE_INT32(count_shift, APICCommonState),
        VMSTATE_UINT32(initial_count, APICCommonState),
        VMSTATE_INT64(initial_count_load_time, APICCommonState),
        VMSTATE_INT64(next_time, APICCommonState),
        VMSTATE_INT64(timer_expiry,
                      APICCommonState), /* open-coded timer state */
        VMSTATE_END_OF_LIST()
    }
};

static Property apic_properties_common[] = {
    DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
    DEFINE_PROP_PTR("cpu_env", APICCommonState, cpu_env),
    DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
                    true),
    DEFINE_PROP_END_OF_LIST(),
};

static void apic_common_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->vmsd = &vmstate_apic_common;
    dc->reset = apic_reset_common;
    dc->no_user = 1;
    dc->props = apic_properties_common;
    sc->init = apic_init_common;
}

static TypeInfo apic_common_type = {
    .name = TYPE_APIC_COMMON,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(APICCommonState),
    .class_size = sizeof(APICCommonClass),
    .class_init = apic_common_class_init,
    .abstract = true,
};

static void register_types(void)
{
    type_register_static(&apic_common_type);
}

type_init(register_types)
Commit	Line	Data
dae01685 JK	1	/*
	2	* APIC support - common bits of emulated and KVM kernel model
	3	*
	4	* Copyright (c) 2004-2005 Fabrice Bellard
	5	* Copyright (c) 2011 Jan Kiszka, Siemens AG
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>
	19	*/
	20	#include "apic.h"
	21	#include "apic_internal.h"
	22	#include "trace.h"
e5ad936b	23	#include "kvm.h"
dae01685 JK	24
dae01685 JK	25	static int apic_irq_delivered;
e5ad936b	26	bool apic_report_tpr_access;
dae01685 JK	27
	28	void cpu_set_apic_base(DeviceState *d, uint64_t val)
	29	{
dae01685 JK	30	trace_cpu_set_apic_base(val);
dae01685 JK	31
999e12bb AL	32	if (d) {
	33	APICCommonState *s = APIC_COMMON(d);
	34	APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
dae01685 JK	35	info->set_base(s, val);
	36	}
	37	}
	38
	39	uint64_t cpu_get_apic_base(DeviceState *d)
	40	{
999e12bb AL	41	if (d) {
	42	APICCommonState *s = APIC_COMMON(d);
	43	trace_cpu_get_apic_base((uint64_t)s->apicbase);
	44	return s->apicbase;
	45	} else {
	46	trace_cpu_get_apic_base(0);
	47	return 0;
	48	}
dae01685 JK	49	}
	50
	51	void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
	52	{
999e12bb AL	53	APICCommonState *s;
999e12bb AL	54	APICCommonClass *info;
dae01685	55
999e12bb AL	56	if (!d) {
999e12bb AL	57	return;
dae01685	58	}
999e12bb AL	59
	60	s = APIC_COMMON(d);
	61	info = APIC_COMMON_GET_CLASS(s);
	62
	63	info->set_tpr(s, val);
dae01685 JK	64	}
	65
	66	uint8_t cpu_get_apic_tpr(DeviceState *d)
e5ad936b JK	67	{
	68	APICCommonState *s;
	69	APICCommonClass *info;
	70
	71	if (!d) {
	72	return 0;
	73	}
	74
	75	s = APIC_COMMON(d);
	76	info = APIC_COMMON_GET_CLASS(s);
	77
	78	return info->get_tpr(s);
	79	}
	80
	81	void apic_enable_tpr_access_reporting(DeviceState *d, bool enable)
	82	{
	83	APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
	84	APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
	85
	86	apic_report_tpr_access = enable;
	87	if (info->enable_tpr_reporting) {
	88	info->enable_tpr_reporting(s, enable);
	89	}
	90	}
	91
	92	void apic_enable_vapic(DeviceState *d, target_phys_addr_t paddr)
dae01685 JK	93	{
dae01685 JK	94	APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
e5ad936b	95	APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
dae01685	96
e5ad936b JK	97	s->vapic_paddr = paddr;
e5ad936b JK	98	info->vapic_base_update(s);
dae01685 JK	99	}
dae01685 JK	100
d362e757 JK	101	void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
	102	TPRAccess access)
	103	{
e5ad936b JK	104	APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
	105
	106	vapic_report_tpr_access(s->vapic, s->cpu_env, ip, access);
d362e757 JK	107	}
d362e757 JK	108
dae01685 JK	109	void apic_report_irq_delivered(int delivered)
	110	{
	111	apic_irq_delivered += delivered;
	112
	113	trace_apic_report_irq_delivered(apic_irq_delivered);
	114	}
	115
	116	void apic_reset_irq_delivered(void)
	117	{
	118	trace_apic_reset_irq_delivered(apic_irq_delivered);
	119
	120	apic_irq_delivered = 0;
	121	}
	122
	123	int apic_get_irq_delivered(void)
	124	{
	125	trace_apic_get_irq_delivered(apic_irq_delivered);
	126
	127	return apic_irq_delivered;
	128	}
	129
	130	void apic_deliver_nmi(DeviceState *d)
	131	{
999e12bb AL	132	APICCommonState *s = APIC_COMMON(d);
999e12bb AL	133	APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
dae01685	134
dae01685 JK	135	info->external_nmi(s);
	136	}
	137
7a380ca3 JK	138	bool apic_next_timer(APICCommonState *s, int64_t current_time)
	139	{
	140	int64_t d;
	141
	142	/* We need to store the timer state separately to support APIC
	143	* implementations that maintain a non-QEMU timer, e.g. inside the
	144	* host kernel. This open-coded state allows us to migrate between
	145	* both models. */
	146	s->timer_expiry = -1;
	147
	148	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
	149	return false;
	150	}
	151
	152	d = (current_time - s->initial_count_load_time) >> s->count_shift;
	153
	154	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
	155	if (!s->initial_count) {
	156	return false;
	157	}
	158	d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
	159	((uint64_t)s->initial_count + 1);
	160	} else {
	161	if (d >= s->initial_count) {
	162	return false;
	163	}
	164	d = (uint64_t)s->initial_count + 1;
	165	}
	166	s->next_time = s->initial_count_load_time + (d << s->count_shift);
	167	s->timer_expiry = s->next_time;
	168	return true;
	169	}
	170
dae01685 JK	171	void apic_init_reset(DeviceState *d)
	172	{
	173	APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
	174	int i;
	175
	176	if (!s) {
	177	return;
	178	}
	179	s->tpr = 0;
	180	s->spurious_vec = 0xff;
	181	s->log_dest = 0;
	182	s->dest_mode = 0xf;
	183	memset(s->isr, 0, sizeof(s->isr));
	184	memset(s->tmr, 0, sizeof(s->tmr));
	185	memset(s->irr, 0, sizeof(s->irr));
	186	for (i = 0; i < APIC_LVT_NB; i++) {
	187	s->lvt[i] = APIC_LVT_MASKED;
	188	}
	189	s->esr = 0;
	190	memset(s->icr, 0, sizeof(s->icr));
	191	s->divide_conf = 0;
	192	s->count_shift = 0;
	193	s->initial_count = 0;
	194	s->initial_count_load_time = 0;
	195	s->next_time = 0;
	196	s->wait_for_sipi = 1;
	197
7a380ca3 JK	198	if (s->timer) {
	199	qemu_del_timer(s->timer);
	200	}
	201	s->timer_expiry = -1;
dae01685 JK	202	}
	203
	204	static void apic_reset_common(DeviceState *d)
	205	{
	206	APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
e5ad936b	207	APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
dae01685 JK	208	bool bsp;
	209
	210	bsp = cpu_is_bsp(s->cpu_env);
	211	s->apicbase = 0xfee00000 \|
	212	(bsp ? MSR_IA32_APICBASE_BSP : 0) \| MSR_IA32_APICBASE_ENABLE;
	213
e5ad936b JK	214	s->vapic_paddr = 0;
	215	info->vapic_base_update(s);
	216
dae01685 JK	217	apic_init_reset(d);
	218
	219	if (bsp) {
	220	/*
	221	* LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
	222	* time typically by BIOS, so PIC interrupt can be delivered to the
	223	* processor when local APIC is enabled.
	224	*/
	225	s->lvt[APIC_LVT_LINT0] = 0x700;
	226	}
	227	}
	228
	229	/* This function is only used for old state version 1 and 2 */
	230	static int apic_load_old(QEMUFile f, void opaque, int version_id)
	231	{
	232	APICCommonState *s = opaque;
a4aecd28	233	APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
dae01685 JK	234	int i;
	235
	236	if (version_id > 2) {
	237	return -EINVAL;
	238	}
	239
	240	/* XXX: what if the base changes? (registered memory regions) */
	241	qemu_get_be32s(f, &s->apicbase);
	242	qemu_get_8s(f, &s->id);
	243	qemu_get_8s(f, &s->arb_id);
	244	qemu_get_8s(f, &s->tpr);
	245	qemu_get_be32s(f, &s->spurious_vec);
	246	qemu_get_8s(f, &s->log_dest);
	247	qemu_get_8s(f, &s->dest_mode);
	248	for (i = 0; i < 8; i++) {
	249	qemu_get_be32s(f, &s->isr[i]);
	250	qemu_get_be32s(f, &s->tmr[i]);
	251	qemu_get_be32s(f, &s->irr[i]);
	252	}
	253	for (i = 0; i < APIC_LVT_NB; i++) {
	254	qemu_get_be32s(f, &s->lvt[i]);
	255	}
	256	qemu_get_be32s(f, &s->esr);
	257	qemu_get_be32s(f, &s->icr[0]);
	258	qemu_get_be32s(f, &s->icr[1]);
	259	qemu_get_be32s(f, &s->divide_conf);
	260	s->count_shift = qemu_get_be32(f);
	261	qemu_get_be32s(f, &s->initial_count);
	262	s->initial_count_load_time = qemu_get_be64(f);
	263	s->next_time = qemu_get_be64(f);
	264
	265	if (version_id >= 2) {
a4aecd28 JK	266	s->timer_expiry = qemu_get_be64(f);
	267	}
	268
	269	if (info->post_load) {
	270	info->post_load(s);
dae01685 JK	271	}
	272	return 0;
	273	}
	274
	275	static int apic_init_common(SysBusDevice *dev)
	276	{
999e12bb AL	277	APICCommonState *s = APIC_COMMON(dev);
999e12bb AL	278	APICCommonClass *info;
e5ad936b	279	static DeviceState *vapic;
dae01685 JK	280	static int apic_no;
	281
	282	if (apic_no >= MAX_APICS) {
	283	return -1;
	284	}
	285	s->idx = apic_no++;
	286
999e12bb	287	info = APIC_COMMON_GET_CLASS(s);
dae01685 JK	288	info->init(s);
dae01685 JK	289
e5ad936b JK	290	sysbus_init_mmio(dev, &s->io_memory);
	291
	292	if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK) {
	293	vapic = sysbus_create_simple("kvmvapic", -1, NULL);
	294	}
	295	s->vapic = vapic;
	296	if (apic_report_tpr_access && info->enable_tpr_reporting) {
	297	info->enable_tpr_reporting(s, true);
	298	}
	299
dae01685 JK	300	return 0;
	301	}
	302
e5ad936b JK	303	static void apic_dispatch_pre_save(void *opaque)
	304	{
	305	APICCommonState *s = APIC_COMMON(opaque);
	306	APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
	307
	308	if (info->pre_save) {
	309	info->pre_save(s);
	310	}
	311	}
	312
7a380ca3 JK	313	static int apic_dispatch_post_load(void *opaque, int version_id)
7a380ca3 JK	314	{
999e12bb AL	315	APICCommonState *s = APIC_COMMON(opaque);
999e12bb AL	316	APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
7a380ca3 JK	317
	318	if (info->post_load) {
	319	info->post_load(s);
	320	}
	321	return 0;
	322	}
	323
dae01685 JK	324	static const VMStateDescription vmstate_apic_common = {
	325	.name = "apic",
	326	.version_id = 3,
	327	.minimum_version_id = 3,
	328	.minimum_version_id_old = 1,
	329	.load_state_old = apic_load_old,
e5ad936b	330	.pre_save = apic_dispatch_pre_save,
7a380ca3	331	.post_load = apic_dispatch_post_load,
dae01685 JK	332	.fields = (VMStateField[]) {
	333	VMSTATE_UINT32(apicbase, APICCommonState),
	334	VMSTATE_UINT8(id, APICCommonState),
	335	VMSTATE_UINT8(arb_id, APICCommonState),
	336	VMSTATE_UINT8(tpr, APICCommonState),
	337	VMSTATE_UINT32(spurious_vec, APICCommonState),
	338	VMSTATE_UINT8(log_dest, APICCommonState),
	339	VMSTATE_UINT8(dest_mode, APICCommonState),
	340	VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
	341	VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
	342	VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
	343	VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
	344	VMSTATE_UINT32(esr, APICCommonState),
	345	VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
	346	VMSTATE_UINT32(divide_conf, APICCommonState),
	347	VMSTATE_INT32(count_shift, APICCommonState),
	348	VMSTATE_UINT32(initial_count, APICCommonState),
	349	VMSTATE_INT64(initial_count_load_time, APICCommonState),
	350	VMSTATE_INT64(next_time, APICCommonState),
7a380ca3 JK	351	VMSTATE_INT64(timer_expiry,
7a380ca3 JK	352	APICCommonState), /* open-coded timer state */
dae01685 JK	353	VMSTATE_END_OF_LIST()
	354	}
	355	};
	356
	357	static Property apic_properties_common[] = {
	358	DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
	359	DEFINE_PROP_PTR("cpu_env", APICCommonState, cpu_env),
e5ad936b JK	360	DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
e5ad936b JK	361	true),
dae01685 JK	362	DEFINE_PROP_END_OF_LIST(),
	363	};
	364
999e12bb AL	365	static void apic_common_class_init(ObjectClass klass, void data)
	366	{
	367	SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
39bffca2	368	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	369
39bffca2 AL	370	dc->vmsd = &vmstate_apic_common;
	371	dc->reset = apic_reset_common;
	372	dc->no_user = 1;
	373	dc->props = apic_properties_common;
999e12bb AL	374	sc->init = apic_init_common;
999e12bb AL	375	}
dae01685	376
999e12bb AL	377	static TypeInfo apic_common_type = {
	378	.name = TYPE_APIC_COMMON,
	379	.parent = TYPE_SYS_BUS_DEVICE,
	380	.instance_size = sizeof(APICCommonState),
	381	.class_size = sizeof(APICCommonClass),
	382	.class_init = apic_common_class_init,
	383	.abstract = true,
	384	};
	385
83f7d43a	386	static void register_types(void)
999e12bb AL	387	{
	388	type_register_static(&apic_common_type);
	389	}
	390
83f7d43a	391	type_init(register_types)