[qemu.git] / hw / lm32_boards.c

/*
 *  QEMU models for LatticeMico32 uclinux and evr32 boards.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "sysbus.h"
#include "hw.h"
#include "net.h"
#include "flash.h"
#include "devices.h"
#include "boards.h"
#include "loader.h"
#include "blockdev.h"
#include "elf.h"
#include "lm32_hwsetup.h"
#include "lm32.h"

typedef struct {
    CPUState *env;
    target_phys_addr_t bootstrap_pc;
    target_phys_addr_t flash_base;
    target_phys_addr_t hwsetup_base;
    target_phys_addr_t initrd_base;
    size_t initrd_size;
    target_phys_addr_t cmdline_base;
} ResetInfo;

static void cpu_irq_handler(void *opaque, int irq, int level)
{
    CPUState *env = opaque;

    if (level) {
        cpu_interrupt(env, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
    }
}

static void main_cpu_reset(void *opaque)
{
    ResetInfo *reset_info = opaque;
    CPUState *env = reset_info->env;

    cpu_reset(env);

    /* init defaults */
    env->pc = (uint32_t)reset_info->bootstrap_pc;
    env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
    env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
    env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
    env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
        reset_info->initrd_size);
    env->eba = reset_info->flash_base;
    env->deba = reset_info->flash_base;
}

static void lm32_evr_init(ram_addr_t ram_size_not_used,
                          const char *boot_device,
                          const char *kernel_filename,
                          const char *kernel_cmdline,
                          const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    DriveInfo *dinfo;
    ram_addr_t phys_ram;
    ram_addr_t phys_flash;
    qemu_irq *cpu_irq, irq[32];
    ResetInfo *reset_info;
    int i;

    /* memory map */
    target_phys_addr_t flash_base  = 0x04000000;
    size_t flash_sector_size       = 256 * 1024;
    size_t flash_size              = 32 * 1024 * 1024;
    target_phys_addr_t ram_base    = 0x08000000;
    size_t ram_size                = 64 * 1024 * 1024;
    target_phys_addr_t timer0_base = 0x80002000;
    target_phys_addr_t uart0_base  = 0x80006000;
    target_phys_addr_t timer1_base = 0x8000a000;
    int uart0_irq                  = 0;
    int timer0_irq                 = 1;
    int timer1_irq                 = 3;

    reset_info = qemu_mallocz(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    env = cpu_init(cpu_model);
    reset_info->env = env;

    reset_info->flash_base = flash_base;

    phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size);
    cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);

    phys_flash = qemu_ram_alloc(NULL, "lm32_evr.flash", flash_size);
    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, phys_flash,
                          dinfo ? dinfo->bdrv : NULL, flash_sector_size,
                          flash_size / flash_sector_size, 1, 2,
                          0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
    env->pic_state = lm32_pic_init(*cpu_irq);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, ELF_MACHINE, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
                          const char *boot_device,
                          const char *kernel_filename,
                          const char *kernel_cmdline,
                          const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    DriveInfo *dinfo;
    ram_addr_t phys_ram;
    ram_addr_t phys_flash;
    qemu_irq *cpu_irq, irq[32];
    HWSetup *hw;
    ResetInfo *reset_info;
    int i;

    /* memory map */
    target_phys_addr_t flash_base   = 0x04000000;
    size_t flash_sector_size        = 256 * 1024;
    size_t flash_size               = 32 * 1024 * 1024;
    target_phys_addr_t ram_base     = 0x08000000;
    size_t ram_size                 = 64 * 1024 * 1024;
    target_phys_addr_t uart0_base   = 0x80000000;
    target_phys_addr_t timer0_base  = 0x80002000;
    target_phys_addr_t timer1_base  = 0x80010000;
    target_phys_addr_t timer2_base  = 0x80012000;
    int uart0_irq                   = 0;
    int timer0_irq                  = 1;
    int timer1_irq                  = 20;
    int timer2_irq                  = 21;
    target_phys_addr_t hwsetup_base = 0x0bffe000;
    target_phys_addr_t cmdline_base = 0x0bfff000;
    target_phys_addr_t initrd_base  = 0x08400000;
    size_t initrd_max               = 0x01000000;

    reset_info = qemu_mallocz(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    env = cpu_init(cpu_model);
    reset_info->env = env;

    reset_info->flash_base = flash_base;

    phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size);
    cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);

    phys_flash = qemu_ram_alloc(NULL, "lm32_uclinux.flash", flash_size);
    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, phys_flash,
                          dinfo ? dinfo->bdrv : NULL, flash_sector_size,
                          flash_size / flash_sector_size, 1, 2,
                          0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
    env->pic_state = lm32_pic_init(*cpu_irq);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
    sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, ELF_MACHINE, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    /* generate a rom with the hardware description */
    hw = hwsetup_init();
    hwsetup_add_cpu(hw, "LM32", 75000000);
    hwsetup_add_flash(hw, "flash", flash_base, flash_size);
    hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
    hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
    hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
    hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
    hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
    hwsetup_add_trailer(hw);
    hwsetup_create_rom(hw, hwsetup_base);
    hwsetup_free(hw);

    reset_info->hwsetup_base = hwsetup_base;

    if (kernel_cmdline && strlen(kernel_cmdline)) {
        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
                kernel_cmdline);
        reset_info->cmdline_base = cmdline_base;
    }

    if (initrd_filename) {
        size_t initrd_size;
        initrd_size = load_image_targphys(initrd_filename, initrd_base,
                initrd_max);
        reset_info->initrd_base = initrd_base;
        reset_info->initrd_size = initrd_size;
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static QEMUMachine lm32_evr_machine = {
    .name = "lm32-evr",
    .desc = "LatticeMico32 EVR32 eval system",
    .init = lm32_evr_init,
    .is_default = 1
};

static QEMUMachine lm32_uclinux_machine = {
    .name = "lm32-uclinux",
    .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
    .init = lm32_uclinux_init,
    .is_default = 0
};

static void lm32_machine_init(void)
{
    qemu_register_machine(&lm32_uclinux_machine);
    qemu_register_machine(&lm32_evr_machine);
}

machine_init(lm32_machine_init);
Commit	Line	Data
d821732a MW	1	/*
	2	* QEMU models for LatticeMico32 uclinux and evr32 boards.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "sysbus.h"
	21	#include "hw.h"
	22	#include "net.h"
	23	#include "flash.h"
d821732a MW	24	#include "devices.h"
	25	#include "boards.h"
	26	#include "loader.h"
	27	#include "blockdev.h"
	28	#include "elf.h"
	29	#include "lm32_hwsetup.h"
	30	#include "lm32.h"
	31
	32	typedef struct {
	33	CPUState *env;
	34	target_phys_addr_t bootstrap_pc;
	35	target_phys_addr_t flash_base;
	36	target_phys_addr_t hwsetup_base;
	37	target_phys_addr_t initrd_base;
	38	size_t initrd_size;
	39	target_phys_addr_t cmdline_base;
	40	} ResetInfo;
	41
	42	static void cpu_irq_handler(void *opaque, int irq, int level)
	43	{
	44	CPUState *env = opaque;
	45
	46	if (level) {
	47	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	48	} else {
	49	cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
	50	}
	51	}
	52
	53	static void main_cpu_reset(void *opaque)
	54	{
	55	ResetInfo *reset_info = opaque;
	56	CPUState *env = reset_info->env;
	57
	58	cpu_reset(env);
	59
	60	/* init defaults */
	61	env->pc = (uint32_t)reset_info->bootstrap_pc;
	62	env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
	63	env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
	64	env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
	65	env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
	66	reset_info->initrd_size);
	67	env->eba = reset_info->flash_base;
	68	env->deba = reset_info->flash_base;
	69	}
	70
	71	static void lm32_evr_init(ram_addr_t ram_size_not_used,
	72	const char *boot_device,
	73	const char *kernel_filename,
	74	const char *kernel_cmdline,
	75	const char initrd_filename, const char cpu_model)
	76	{
	77	CPUState *env;
	78	DriveInfo *dinfo;
	79	ram_addr_t phys_ram;
	80	ram_addr_t phys_flash;
	81	qemu_irq *cpu_irq, irq[32];
	82	ResetInfo *reset_info;
	83	int i;
	84
	85	/* memory map */
	86	target_phys_addr_t flash_base = 0x04000000;
	87	size_t flash_sector_size = 256 * 1024;
88	size_t flash_size = 32 * 1024 * 1024;
89	target_phys_addr_t ram_base = 0x08000000;
90	size_t ram_size = 64 * 1024 * 1024;
91	target_phys_addr_t timer0_base = 0x80002000;
92	target_phys_addr_t uart0_base = 0x80006000;
93	target_phys_addr_t timer1_base = 0x8000a000;
94	int uart0_irq = 0;
95	int timer0_irq = 1;
96	int timer1_irq = 3;
97
98	reset_info = qemu_mallocz(sizeof(ResetInfo));
99
100	if (cpu_model == NULL) {
101	cpu_model = "lm32-full";
102	}
103	env = cpu_init(cpu_model);
104	reset_info->env = env;
105
106	reset_info->flash_base = flash_base;
107
108	phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size);
109	cpu_register_physical_memory(ram_base, ram_size, phys_ram \| IO_MEM_RAM);
110
111	phys_flash = qemu_ram_alloc(NULL, "lm32_evr.flash", flash_size);
112	dinfo = drive_get(IF_PFLASH, 0, 0);
113	/* Spansion S29NS128P */
114	pflash_cfi02_register(flash_base, phys_flash,
115	dinfo ? dinfo->bdrv : NULL, flash_sector_size,
116	flash_size / flash_sector_size, 1, 2,
117	0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
118
119	/* create irq lines */
120	cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
121	env->pic_state = lm32_pic_init(*cpu_irq);
122	for (i = 0; i < 32; i++) {
123	irq[i] = qdev_get_gpio_in(env->pic_state, i);
124	}
125
126	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
127	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
128	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
129
130	/* make sure juart isn't the first chardev */
131	env->juart_state = lm32_juart_init();
132
133	reset_info->bootstrap_pc = flash_base;
134
135	if (kernel_filename) {
136	uint64_t entry;
137	int kernel_size;
138
139	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
140	1, ELF_MACHINE, 0);
141	reset_info->bootstrap_pc = entry;
142
143	if (kernel_size < 0) {
144	kernel_size = load_image_targphys(kernel_filename, ram_base,
145	ram_size);
146	reset_info->bootstrap_pc = ram_base;
147	}
148
149	if (kernel_size < 0) {
150	fprintf(stderr, "qemu: could not load kernel '%s'\n",
151	kernel_filename);
152	exit(1);
153	}
154	}
155
156	qemu_register_reset(main_cpu_reset, reset_info);
157	}
158
159	static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
160	const char *boot_device,
161	const char *kernel_filename,
162	const char *kernel_cmdline,
163	const char initrd_filename, const char cpu_model)
164	{
165	CPUState *env;
166	DriveInfo *dinfo;
167	ram_addr_t phys_ram;
168	ram_addr_t phys_flash;
169	qemu_irq *cpu_irq, irq[32];
170	HWSetup *hw;
171	ResetInfo *reset_info;
172	int i;
173
174	/* memory map */
175	target_phys_addr_t flash_base = 0x04000000;
176	size_t flash_sector_size = 256 * 1024;
177	size_t flash_size = 32 * 1024 * 1024;
178	target_phys_addr_t ram_base = 0x08000000;
179	size_t ram_size = 64 * 1024 * 1024;
180	target_phys_addr_t uart0_base = 0x80000000;
181	target_phys_addr_t timer0_base = 0x80002000;
182	target_phys_addr_t timer1_base = 0x80010000;
183	target_phys_addr_t timer2_base = 0x80012000;
184	int uart0_irq = 0;
185	int timer0_irq = 1;
186	int timer1_irq = 20;
187	int timer2_irq = 21;
188	target_phys_addr_t hwsetup_base = 0x0bffe000;
189	target_phys_addr_t cmdline_base = 0x0bfff000;
190	target_phys_addr_t initrd_base = 0x08400000;
191	size_t initrd_max = 0x01000000;
192
193	reset_info = qemu_mallocz(sizeof(ResetInfo));
194
195	if (cpu_model == NULL) {
196	cpu_model = "lm32-full";
197	}
198	env = cpu_init(cpu_model);
199	reset_info->env = env;
200
201	reset_info->flash_base = flash_base;
202
203	phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size);
204	cpu_register_physical_memory(ram_base, ram_size, phys_ram \| IO_MEM_RAM);
205
206	phys_flash = qemu_ram_alloc(NULL, "lm32_uclinux.flash", flash_size);
207	dinfo = drive_get(IF_PFLASH, 0, 0);
208	/* Spansion S29NS128P */
209	pflash_cfi02_register(flash_base, phys_flash,
210	dinfo ? dinfo->bdrv : NULL, flash_sector_size,
211	flash_size / flash_sector_size, 1, 2,
212	0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
213
214	/* create irq lines */
215	cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
216	env->pic_state = lm32_pic_init(*cpu_irq);
217	for (i = 0; i < 32; i++) {
218	irq[i] = qdev_get_gpio_in(env->pic_state, i);
219	}
220
221	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
222	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
223	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
224	sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
225
226	/* make sure juart isn't the first chardev */
227	env->juart_state = lm32_juart_init();
228
229	reset_info->bootstrap_pc = flash_base;
230
231	if (kernel_filename) {
232	uint64_t entry;
233	int kernel_size;
234
235	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
236	1, ELF_MACHINE, 0);
237	reset_info->bootstrap_pc = entry;
238
239	if (kernel_size < 0) {
240	kernel_size = load_image_targphys(kernel_filename, ram_base,
241	ram_size);
242	reset_info->bootstrap_pc = ram_base;
243	}
244
245	if (kernel_size < 0) {
246	fprintf(stderr, "qemu: could not load kernel '%s'\n",
247	kernel_filename);
248	exit(1);
249	}
250	}
251
252	/* generate a rom with the hardware description */
253	hw = hwsetup_init();
254	hwsetup_add_cpu(hw, "LM32", 75000000);
255	hwsetup_add_flash(hw, "flash", flash_base, flash_size);
256	hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
257	hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
258	hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
259	hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
260	hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
261	hwsetup_add_trailer(hw);
262	hwsetup_create_rom(hw, hwsetup_base);
263	hwsetup_free(hw);
264
265	reset_info->hwsetup_base = hwsetup_base;
266
267	if (kernel_cmdline && strlen(kernel_cmdline)) {
268	pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
269	kernel_cmdline);
270	reset_info->cmdline_base = cmdline_base;
271	}
272
273	if (initrd_filename) {
274	size_t initrd_size;
275	initrd_size = load_image_targphys(initrd_filename, initrd_base,
276	initrd_max);
277	reset_info->initrd_base = initrd_base;
278	reset_info->initrd_size = initrd_size;
279	}
280
281	qemu_register_reset(main_cpu_reset, reset_info);
282	}
283
284	static QEMUMachine lm32_evr_machine = {
285	.name = "lm32-evr",
286	.desc = "LatticeMico32 EVR32 eval system",
287	.init = lm32_evr_init,
288	.is_default = 1
289	};
290
291	static QEMUMachine lm32_uclinux_machine = {
292	.name = "lm32-uclinux",
293	.desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
294	.init = lm32_uclinux_init,
295	.is_default = 0
296	};
297
298	static void lm32_machine_init(void)
299	{
300	qemu_register_machine(&lm32_uclinux_machine);
301	qemu_register_machine(&lm32_evr_machine);
302	}
303
304	machine_init(lm32_machine_init);