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525bd324 AG |
1 | /* |
2 | * Moxie helper routines. | |
3 | * | |
4 | * Copyright (c) 2008, 2009, 2010, 2013 Anthony Green | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <stdio.h> | |
21 | #include <string.h> | |
22 | #include <assert.h> | |
23 | ||
24 | #include "config.h" | |
25 | #include "cpu.h" | |
26 | #include "mmu.h" | |
27 | #include "exec/exec-all.h" | |
28 | #include "qemu/host-utils.h" | |
29 | #include "helper.h" | |
30 | ||
31 | #define MMUSUFFIX _mmu | |
32 | ||
33 | #define SHIFT 0 | |
34 | #include "exec/softmmu_template.h" | |
35 | ||
36 | #define SHIFT 1 | |
37 | #include "exec/softmmu_template.h" | |
38 | ||
39 | #define SHIFT 2 | |
40 | #include "exec/softmmu_template.h" | |
41 | ||
42 | #define SHIFT 3 | |
43 | #include "exec/softmmu_template.h" | |
44 | ||
45 | /* Try to fill the TLB and return an exception if error. If retaddr is | |
46 | NULL, it means that the function was called in C code (i.e. not | |
47 | from generated code or from helper.c) */ | |
48 | void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx, | |
49 | uintptr_t retaddr) | |
50 | { | |
51 | int ret; | |
52 | ||
53 | ret = cpu_moxie_handle_mmu_fault(env, addr, is_write, mmu_idx); | |
54 | if (unlikely(ret)) { | |
55 | if (retaddr) { | |
56 | cpu_restore_state(env, retaddr); | |
57 | } | |
58 | } | |
59 | cpu_loop_exit(env); | |
60 | } | |
61 | ||
62 | void helper_raise_exception(CPUMoxieState *env, int ex) | |
63 | { | |
64 | env->exception_index = ex; | |
65 | /* Stash the exception type. */ | |
66 | env->sregs[2] = ex; | |
67 | /* Stash the address where the exception occurred. */ | |
68 | cpu_restore_state(env, GETPC()); | |
69 | env->sregs[5] = env->pc; | |
70 | /* Jump the the exception handline routine. */ | |
71 | env->pc = env->sregs[1]; | |
72 | cpu_loop_exit(env); | |
73 | } | |
74 | ||
75 | uint32_t helper_div(CPUMoxieState *env, uint32_t a, uint32_t b) | |
76 | { | |
77 | if (unlikely(b == 0)) { | |
78 | helper_raise_exception(env, MOXIE_EX_DIV0); | |
79 | return 0; | |
80 | } | |
81 | if (unlikely(a == INT_MIN && b == -1)) { | |
82 | return INT_MIN; | |
83 | } | |
84 | ||
85 | return (int32_t)a / (int32_t)b; | |
86 | } | |
87 | ||
88 | uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b) | |
89 | { | |
90 | if (unlikely(b == 0)) { | |
91 | helper_raise_exception(env, MOXIE_EX_DIV0); | |
92 | return 0; | |
93 | } | |
94 | return a / b; | |
95 | } | |
96 | ||
97 | void helper_debug(CPUMoxieState *env) | |
98 | { | |
99 | env->exception_index = EXCP_DEBUG; | |
100 | cpu_loop_exit(env); | |
101 | } | |
102 | ||
103 | #if defined(CONFIG_USER_ONLY) | |
104 | ||
53574064 | 105 | void moxie_cpu_do_interrupt(CPUState *env) |
525bd324 AG |
106 | { |
107 | env->exception_index = -1; | |
108 | } | |
109 | ||
110 | int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address, | |
111 | int rw, int mmu_idx) | |
112 | { | |
113 | env->exception_index = 0xaa; | |
114 | env->debug1 = address; | |
115 | cpu_dump_state(env, stderr, fprintf, 0); | |
116 | return 1; | |
117 | } | |
118 | ||
d2ad5021 | 119 | hwaddr cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
525bd324 AG |
120 | { |
121 | return addr; | |
122 | } | |
123 | ||
124 | #else /* !CONFIG_USER_ONLY */ | |
125 | ||
126 | int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address, | |
127 | int rw, int mmu_idx) | |
128 | { | |
129 | MoxieMMUResult res; | |
130 | int prot, miss; | |
131 | target_ulong phy; | |
132 | int r = 1; | |
133 | ||
134 | address &= TARGET_PAGE_MASK; | |
135 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
136 | miss = moxie_mmu_translate(&res, env, address, rw, mmu_idx); | |
137 | if (miss) { | |
138 | /* handle the miss. */ | |
139 | phy = 0; | |
140 | env->exception_index = MOXIE_EX_MMU_MISS; | |
141 | } else { | |
142 | phy = res.phy; | |
143 | r = 0; | |
144 | } | |
145 | tlb_set_page(env, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); | |
146 | return r; | |
147 | } | |
148 | ||
149 | ||
53574064 | 150 | void moxie_cpu_do_interrupt(CPUState *cs) |
525bd324 | 151 | { |
53574064 DH |
152 | MoxieCPU *cpu = MOXIE_CPU(cs); |
153 | CPUMoxieState *env = &cpu->env; | |
154 | ||
525bd324 AG |
155 | switch (env->exception_index) { |
156 | case MOXIE_EX_BREAK: | |
157 | break; | |
158 | default: | |
159 | break; | |
160 | } | |
161 | } | |
162 | ||
163 | hwaddr cpu_get_phys_page_debug(CPUMoxieState *env, target_ulong addr) | |
164 | { | |
165 | uint32_t phy = addr; | |
166 | MoxieMMUResult res; | |
167 | int miss; | |
168 | miss = moxie_mmu_translate(&res, env, addr, 0, 0); | |
169 | if (!miss) { | |
170 | phy = res.phy; | |
171 | } | |
172 | return phy; | |
173 | } | |
174 | #endif |