[qemu.git] / hw / sh4 / r2d.c

/*
 * Renesas SH7751R R2D-PLUS emulation
 *
 * Copyright (c) 2007 Magnus Damm
 * Copyright (c) 2008 Paul Mundt
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/sh4/sh.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/pci/pci.h"
#include "hw/qdev-properties.h"
#include "net/net.h"
#include "sh7750_regs.h"
#include "hw/ide.h"
#include "hw/irq.h"
#include "hw/loader.h"
#include "hw/usb.h"
#include "hw/block/flash.h"
#include "exec/address-spaces.h"

#define FLASH_BASE 0x00000000
#define FLASH_SIZE (16 * MiB)

#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
#define SDRAM_SIZE 0x04000000

#define SM501_VRAM_SIZE 0x800000

#define BOOT_PARAMS_OFFSET 0x0010000
/* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
#define LINUX_LOAD_OFFSET  0x0800000
#define INITRD_LOAD_OFFSET 0x1800000

#define PA_IRLMSK	0x00
#define PA_POWOFF	0x30
#define PA_VERREG	0x32
#define PA_OUTPORT	0x36

typedef struct {
    uint16_t bcr;
    uint16_t irlmsk;
    uint16_t irlmon;
    uint16_t cfctl;
    uint16_t cfpow;
    uint16_t dispctl;
    uint16_t sdmpow;
    uint16_t rtcce;
    uint16_t pcicd;
    uint16_t voyagerrts;
    uint16_t cfrst;
    uint16_t admrts;
    uint16_t extrst;
    uint16_t cfcdintclr;
    uint16_t keyctlclr;
    uint16_t pad0;
    uint16_t pad1;
    uint16_t verreg;
    uint16_t inport;
    uint16_t outport;
    uint16_t bverreg;

/* output pin */
    qemu_irq irl;
    MemoryRegion iomem;
} r2d_fpga_t;

enum r2d_fpga_irq {
    PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
    SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
    NR_IRQS
};

static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
    [CF_IDE]	= {  1, 1<<9 },
    [CF_CD]	= {  2, 1<<8 },
    [PCI_INTA]	= {  9, 1<<14 },
    [PCI_INTB]	= { 10, 1<<13 },
    [PCI_INTC]	= {  3, 1<<12 },
    [PCI_INTD]	= {  0, 1<<11 },
    [SM501]	= {  4, 1<<10 },
    [KEY]	= {  5, 1<<6 },
    [RTC_A]	= {  6, 1<<5 },
    [RTC_T]	= {  7, 1<<4 },
    [SDCARD]	= {  8, 1<<7 },
    [EXT]	= { 11, 1<<0 },
    [TP]	= { 12, 1<<15 },
};

static void update_irl(r2d_fpga_t *fpga)
{
    int i, irl = 15;
    for (i = 0; i < NR_IRQS; i++)
        if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
            if (irqtab[i].irl < irl)
                irl = irqtab[i].irl;
    qemu_set_irq(fpga->irl, irl ^ 15);
}

static void r2d_fpga_irq_set(void *opaque, int n, int level)
{
    r2d_fpga_t *fpga = opaque;
    if (level)
        fpga->irlmon |= irqtab[n].msk;
    else
        fpga->irlmon &= ~irqtab[n].msk;
    update_irl(fpga);
}

static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size)
{
    r2d_fpga_t *s = opaque;

    switch (addr) {
    case PA_IRLMSK:
        return s->irlmsk;
    case PA_OUTPORT:
        return s->outport;
    case PA_POWOFF:
        return 0x00;
    case PA_VERREG:
        return 0x10;
    }

    return 0;
}

static void
r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size)
{
    r2d_fpga_t *s = opaque;

    switch (addr) {
    case PA_IRLMSK:
        s->irlmsk = value;
        update_irl(s);
        break;
    case PA_OUTPORT:
        s->outport = value;
        break;
    case PA_POWOFF:
        if (value & 1) {
            qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
        }
        break;
    case PA_VERREG:
        /* Discard writes */
        break;
    }
}

static const MemoryRegionOps r2d_fpga_ops = {
    .read = r2d_fpga_read,
    .write = r2d_fpga_write,
    .impl.min_access_size = 2,
    .impl.max_access_size = 2,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
                               hwaddr base, qemu_irq irl)
{
    r2d_fpga_t *s;

    s = g_malloc0(sizeof(r2d_fpga_t));

    s->irl = irl;

    memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
    memory_region_add_subregion(sysmem, base, &s->iomem);
    return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
}

typedef struct ResetData {
    SuperHCPU *cpu;
    uint32_t vector;
} ResetData;

static void main_cpu_reset(void *opaque)
{
    ResetData *s = (ResetData *)opaque;
    CPUSH4State *env = &s->cpu->env;

    cpu_reset(CPU(s->cpu));
    env->pc = s->vector;
}

static struct QEMU_PACKED
{
    int mount_root_rdonly;
    int ramdisk_flags;
    int orig_root_dev;
    int loader_type;
    int initrd_start;
    int initrd_size;

    char pad[232];

    char kernel_cmdline[256] QEMU_NONSTRING;
} boot_params;

static void r2d_init(MachineState *machine)
{
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    const char *initrd_filename = machine->initrd_filename;
    SuperHCPU *cpu;
    CPUSH4State *env;
    ResetData *reset_info;
    struct SH7750State *s;
    MemoryRegion *sdram = g_new(MemoryRegion, 1);
    qemu_irq *irq;
    DriveInfo *dinfo;
    int i;
    DeviceState *dev;
    SysBusDevice *busdev;
    MemoryRegion *address_space_mem = get_system_memory();
    PCIBus *pci_bus;

    cpu = SUPERH_CPU(cpu_create(machine->cpu_type));
    env = &cpu->env;

    reset_info = g_malloc0(sizeof(ResetData));
    reset_info->cpu = cpu;
    reset_info->vector = env->pc;
    qemu_register_reset(main_cpu_reset, reset_info);

    /* Allocate memory space */
    memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_fatal);
    memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
    /* Register peripherals */
    s = sh7750_init(cpu, address_space_mem);
    irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));

    dev = qdev_create(NULL, "sh_pci");
    busdev = SYS_BUS_DEVICE(dev);
    qdev_init_nofail(dev);
    pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
    sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
    sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
    sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
    sysbus_connect_irq(busdev, 1, irq[PCI_INTB]);
    sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
    sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);

    dev = qdev_create(NULL, "sysbus-sm501");
    busdev = SYS_BUS_DEVICE(dev);
    qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
    qdev_prop_set_uint32(dev, "base", 0x10000000);
    qdev_prop_set_chr(dev, "chardev", serial_hd(2));
    qdev_init_nofail(dev);
    sysbus_mmio_map(busdev, 0, 0x10000000);
    sysbus_mmio_map(busdev, 1, 0x13e00000);
    sysbus_connect_irq(busdev, 0, irq[SM501]);

    /* onboard CF (True IDE mode, Master only). */
    dinfo = drive_get(IF_IDE, 0, 0);
    dev = qdev_create(NULL, "mmio-ide");
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
    qdev_prop_set_uint32(dev, "shift", 1);
    qdev_init_nofail(dev);
    sysbus_mmio_map(busdev, 0, 0x14001000);
    sysbus_mmio_map(busdev, 1, 0x1400080c);
    mmio_ide_init_drives(dev, dinfo, NULL);

    /*
     * Onboard flash memory
     * According to the old board user document in Japanese (under
     * NDA) what is referred to as FROM (Area0) is connected via a
     * 32-bit bus and CS0 to CN8. The docs mention a Cypress
     * S29PL127J60TFI130 chipsset.  Per the 'S29PL-J 002-00615
     * Rev. *E' datasheet, it is a 128Mbit NOR parallel flash
     * addressable in words of 16bit.
     */
    dinfo = drive_get(IF_PFLASH, 0, 0);
    pflash_cfi02_register(0x0, "r2d.flash", FLASH_SIZE,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200,
                          0x555, 0x2aa, 0);

    /* NIC: rtl8139 on-board, and 2 slots. */
    for (i = 0; i < nb_nics; i++)
        pci_nic_init_nofail(&nd_table[i], pci_bus,
                            "rtl8139", i==0 ? "2" : NULL);

    /* USB keyboard */
    usb_create_simple(usb_bus_find(-1), "usb-kbd");

    /* Todo: register on board registers */
    memset(&boot_params, 0, sizeof(boot_params));

    if (kernel_filename) {
        int kernel_size;

        kernel_size = load_image_targphys(kernel_filename,
                                          SDRAM_BASE + LINUX_LOAD_OFFSET,
                                          INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
        if (kernel_size < 0) {
          fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
          exit(1);
        }

        /* initialization which should be done by firmware */
        address_space_stl(&address_space_memory, SH7750_BCR1, 1 << 3,
                          MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */
        address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2),
                          MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */
        reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
    }

    if (initrd_filename) {
        int initrd_size;

        initrd_size = load_image_targphys(initrd_filename,
                                          SDRAM_BASE + INITRD_LOAD_OFFSET,
                                          SDRAM_SIZE - INITRD_LOAD_OFFSET);

        if (initrd_size < 0) {
          fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
          exit(1);
        }

        /* initialization which should be done by firmware */
        boot_params.loader_type = tswap32(1);
        boot_params.initrd_start = tswap32(INITRD_LOAD_OFFSET);
        boot_params.initrd_size = tswap32(initrd_size);
    }

    if (kernel_cmdline) {
        /* I see no evidence that this .kernel_cmdline buffer requires
           NUL-termination, so using strncpy should be ok. */
        strncpy(boot_params.kernel_cmdline, kernel_cmdline,
                sizeof(boot_params.kernel_cmdline));
    }

    rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
                       SDRAM_BASE + BOOT_PARAMS_OFFSET);
}

static void r2d_machine_init(MachineClass *mc)
{
    mc->desc = "r2d-plus board";
    mc->init = r2d_init;
    mc->block_default_type = IF_IDE;
    mc->default_cpu_type = TYPE_SH7751R_CPU;
}

DEFINE_MACHINE("r2d", r2d_machine_init)
Commit	Line	Data
0d78f544 TS	1	/*
	2	* Renesas SH7751R R2D-PLUS emulation
	3	*
	4	* Copyright (c) 2007 Magnus Damm
b319feb7	5	* Copyright (c) 2008 Paul Mundt
0d78f544 TS	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
9d4c9946	26	#include "qemu/osdep.h"
e7dd191c	27	#include "qemu/units.h"
da34e65c	28	#include "qapi/error.h"
4771d756	29	#include "cpu.h"
83c9f4ca	30	#include "hw/sysbus.h"
0d09e41a	31	#include "hw/sh4/sh.h"
71e8a915	32	#include "sysemu/reset.h"
54d31236	33	#include "sysemu/runstate.h"
9c17d615	34	#include "sysemu/sysemu.h"
83c9f4ca PB	35	#include "hw/boards.h"
83c9f4ca PB	36	#include "hw/pci/pci.h"
a27bd6c7	37	#include "hw/qdev-properties.h"
1422e32d	38	#include "net/net.h"
47b43a1f	39	#include "sh7750_regs.h"
83c9f4ca	40	#include "hw/ide.h"
64552b6b	41	#include "hw/irq.h"
83c9f4ca PB	42	#include "hw/loader.h"
83c9f4ca PB	43	#include "hw/usb.h"
0d09e41a	44	#include "hw/block/flash.h"
022c62cb	45	#include "exec/address-spaces.h"
56839a19 AJ	46
56839a19 AJ	47	#define FLASH_BASE 0x00000000
84687134	48	#define FLASH_SIZE (16 * MiB)
0d78f544 TS	49
	50	#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
	51	#define SDRAM_SIZE 0x04000000
	52
ffd39257 BS	53	#define SM501_VRAM_SIZE 0x800000
ffd39257 BS	54
73f19035	55	#define BOOT_PARAMS_OFFSET 0x0010000
e8afa065	56	/* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
73f19035 AJ	57	#define LINUX_LOAD_OFFSET 0x0800000
73f19035 AJ	58	#define INITRD_LOAD_OFFSET 0x1800000
e8afa065	59
d47ede60	60	#define PA_IRLMSK 0x00
b319feb7 AJ	61	#define PA_POWOFF 0x30
	62	#define PA_VERREG 0x32
	63	#define PA_OUTPORT 0x36
	64
	65	typedef struct {
b319feb7	66	uint16_t bcr;
d47ede60	67	uint16_t irlmsk;
b319feb7 AJ	68	uint16_t irlmon;
	69	uint16_t cfctl;
	70	uint16_t cfpow;
	71	uint16_t dispctl;
	72	uint16_t sdmpow;
	73	uint16_t rtcce;
	74	uint16_t pcicd;
	75	uint16_t voyagerrts;
	76	uint16_t cfrst;
	77	uint16_t admrts;
	78	uint16_t extrst;
	79	uint16_t cfcdintclr;
	80	uint16_t keyctlclr;
	81	uint16_t pad0;
	82	uint16_t pad1;
b319feb7 AJ	83	uint16_t verreg;
	84	uint16_t inport;
	85	uint16_t outport;
	86	uint16_t bverreg;
d47ede60 AZ	87
	88	/* output pin */
	89	qemu_irq irl;
5dea2efb	90	MemoryRegion iomem;
c227f099	91	} r2d_fpga_t;
b319feb7	92
d47ede60 AZ	93	enum r2d_fpga_irq {
	94	PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
	95	SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
	96	NR_IRQS
	97	};
	98
	99	static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
	100	[CF_IDE] = { 1, 1<<9 },
	101	[CF_CD] = { 2, 1<<8 },
	102	[PCI_INTA] = { 9, 1<<14 },
	103	[PCI_INTB] = { 10, 1<<13 },
	104	[PCI_INTC] = { 3, 1<<12 },
	105	[PCI_INTD] = { 0, 1<<11 },
	106	[SM501] = { 4, 1<<10 },
	107	[KEY] = { 5, 1<<6 },
	108	[RTC_A] = { 6, 1<<5 },
	109	[RTC_T] = { 7, 1<<4 },
	110	[SDCARD] = { 8, 1<<7 },
	111	[EXT] = { 11, 1<<0 },
	112	[TP] = { 12, 1<<15 },
	113	};
	114
c227f099	115	static void update_irl(r2d_fpga_t *fpga)
d47ede60 AZ	116	{
	117	int i, irl = 15;
	118	for (i = 0; i < NR_IRQS; i++)
	119	if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
	120	if (irqtab[i].irl < irl)
	121	irl = irqtab[i].irl;
	122	qemu_set_irq(fpga->irl, irl ^ 15);
	123	}
	124
	125	static void r2d_fpga_irq_set(void *opaque, int n, int level)
	126	{
c227f099	127	r2d_fpga_t *fpga = opaque;
d47ede60 AZ	128	if (level)
	129	fpga->irlmon \|= irqtab[n].msk;
	130	else
	131	fpga->irlmon &= ~irqtab[n].msk;
	132	update_irl(fpga);
	133	}
	134
56380752	135	static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size)
b319feb7	136	{
c227f099	137	r2d_fpga_t *s = opaque;
b319feb7	138
b319feb7	139	switch (addr) {
d47ede60 AZ	140	case PA_IRLMSK:
d47ede60 AZ	141	return s->irlmsk;
b319feb7	142	case PA_OUTPORT:
7d37435b	143	return s->outport;
b319feb7	144	case PA_POWOFF:
7d37435b	145	return 0x00;
b319feb7	146	case PA_VERREG:
7d37435b	147	return 0x10;
b319feb7 AJ	148	}
	149
	150	return 0;
	151	}
	152
	153	static void
56380752	154	r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size)
b319feb7	155	{
c227f099	156	r2d_fpga_t *s = opaque;
b319feb7	157
b319feb7	158	switch (addr) {
d47ede60 AZ	159	case PA_IRLMSK:
	160	s->irlmsk = value;
	161	update_irl(s);
7d37435b	162	break;
b319feb7	163	case PA_OUTPORT:
7d37435b PB	164	s->outport = value;
7d37435b PB	165	break;
b319feb7	166	case PA_POWOFF:
37cc0b44	167	if (value & 1) {
cf83f140	168	qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
37cc0b44 AJ	169	}
37cc0b44 AJ	170	break;
b319feb7	171	case PA_VERREG:
7d37435b PB	172	/* Discard writes */
7d37435b PB	173	break;
b319feb7 AJ	174	}
	175	}
	176
5dea2efb	177	static const MemoryRegionOps r2d_fpga_ops = {
56380752 AJ	178	.read = r2d_fpga_read,
	179	.write = r2d_fpga_write,
	180	.impl.min_access_size = 2,
	181	.impl.max_access_size = 2,
5dea2efb	182	.endianness = DEVICE_NATIVE_ENDIAN,
b319feb7 AJ	183	};
b319feb7 AJ	184
5dea2efb	185	static qemu_irq r2d_fpga_init(MemoryRegion sysmem,
a8170e5e	186	hwaddr base, qemu_irq irl)
b319feb7	187	{
c227f099	188	r2d_fpga_t *s;
b319feb7	189
7267c094	190	s = g_malloc0(sizeof(r2d_fpga_t));
d47ede60 AZ	191
d47ede60 AZ	192	s->irl = irl;
b319feb7	193
2c9b15ca	194	memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
5dea2efb	195	memory_region_add_subregion(sysmem, base, &s->iomem);
d47ede60	196	return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
b319feb7 AJ	197	}
b319feb7 AJ	198
4f6493ff	199	typedef struct ResetData {
868bac81	200	SuperHCPU *cpu;
4f6493ff AJ	201	uint32_t vector;
	202	} ResetData;
	203
	204	static void main_cpu_reset(void *opaque)
	205	{
	206	ResetData s = (ResetData )opaque;
868bac81	207	CPUSH4State *env = &s->cpu->env;
4f6493ff	208
868bac81	209	cpu_reset(CPU(s->cpu));
4f6493ff AJ	210	env->pc = s->vector;
	211	}
	212
541dc0d4	213	static struct QEMU_PACKED
73f19035 AJ	214	{
	215	int mount_root_rdonly;
	216	int ramdisk_flags;
	217	int orig_root_dev;
	218	int loader_type;
	219	int initrd_start;
	220	int initrd_size;
	221
	222	char pad[232];
	223
7de7b608	224	char kernel_cmdline[256] QEMU_NONSTRING;
73f19035 AJ	225	} boot_params;
73f19035 AJ	226
3ef96221	227	static void r2d_init(MachineState *machine)
0d78f544	228	{
3ef96221 MA	229	const char *kernel_filename = machine->kernel_filename;
	230	const char *kernel_cmdline = machine->kernel_cmdline;
	231	const char *initrd_filename = machine->initrd_filename;
fd2f410b	232	SuperHCPU *cpu;
0b7ade1d	233	CPUSH4State *env;
4f6493ff	234	ResetData *reset_info;
0d78f544	235	struct SH7750State *s;
5dea2efb	236	MemoryRegion *sdram = g_new(MemoryRegion, 1);
d47ede60	237	qemu_irq *irq;
751c6a17	238	DriveInfo *dinfo;
c2f01775	239	int i;
8c106233 BC	240	DeviceState *dev;
8c106233 BC	241	SysBusDevice *busdev;
27a9d2ea	242	MemoryRegion *address_space_mem = get_system_memory();
29b358f9	243	PCIBus *pci_bus;
0d78f544	244
78f60b82	245	cpu = SUPERH_CPU(cpu_create(machine->cpu_type));
fd2f410b AF	246	env = &cpu->env;
fd2f410b AF	247
7267c094	248	reset_info = g_malloc0(sizeof(ResetData));
868bac81	249	reset_info->cpu = cpu;
4f6493ff AJ	250	reset_info->vector = env->pc;
4f6493ff AJ	251	qemu_register_reset(main_cpu_reset, reset_info);
0d78f544 TS	252
0d78f544 TS	253	/* Allocate memory space */
98a99ce0	254	memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_fatal);
5dea2efb	255	memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
0d78f544	256	/* Register peripherals */
2f493fee	257	s = sh7750_init(cpu, address_space_mem);
5dea2efb	258	irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
8c106233 BC	259
8c106233 BC	260	dev = qdev_create(NULL, "sh_pci");
1356b98d	261	busdev = SYS_BUS_DEVICE(dev);
8c106233	262	qdev_init_nofail(dev);
29b358f9	263	pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
8c106233 BC	264	sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
	265	sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
	266	sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
	267	sysbus_connect_irq(busdev, 1, irq[PCI_INTB]);
	268	sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
	269	sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
d47ede60	270
ca8a1104 BZ	271	dev = qdev_create(NULL, "sysbus-sm501");
	272	busdev = SYS_BUS_DEVICE(dev);
	273	qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
	274	qdev_prop_set_uint32(dev, "base", 0x10000000);
0ed40f16	275	qdev_prop_set_chr(dev, "chardev", serial_hd(2));
ca8a1104 BZ	276	qdev_init_nofail(dev);
	277	sysbus_mmio_map(busdev, 0, 0x10000000);
	278	sysbus_mmio_map(busdev, 1, 0x13e00000);
	279	sysbus_connect_irq(busdev, 0, irq[SM501]);
a4a771c0 AZ	280
a4a771c0 AZ	281	/* onboard CF (True IDE mode, Master only). */
612b2bd0	282	dinfo = drive_get(IF_IDE, 0, 0);
6b2578d6 AF	283	dev = qdev_create(NULL, "mmio-ide");
	284	busdev = SYS_BUS_DEVICE(dev);
	285	sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
	286	qdev_prop_set_uint32(dev, "shift", 1);
	287	qdev_init_nofail(dev);
	288	sysbus_mmio_map(busdev, 0, 0x14001000);
	289	sysbus_mmio_map(busdev, 1, 0x1400080c);
	290	mmio_ide_init_drives(dev, dinfo, NULL);
a4a771c0	291
84687134 MA	292	/*
	293	* Onboard flash memory
	294	* According to the old board user document in Japanese (under
	295	* NDA) what is referred to as FROM (Area0) is connected via a
	296	* 32-bit bus and CS0 to CN8. The docs mention a Cypress
	297	* S29PL127J60TFI130 chipsset. Per the 'S29PL-J 002-00615
	298	* Rev. *E' datasheet, it is a 128Mbit NOR parallel flash
	299	* addressable in words of 16bit.
	300	*/
45e7e4bc	301	dinfo = drive_get(IF_PFLASH, 0, 0);
940d5b13	302	pflash_cfi02_register(0x0, "r2d.flash", FLASH_SIZE,
4be74634	303	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
ce14710f	304	64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200,
01e0451a	305	0x555, 0x2aa, 0);
56839a19	306
c2f01775	307	/* NIC: rtl8139 on-board, and 2 slots. */
ab2da564	308	for (i = 0; i < nb_nics; i++)
29b358f9 DG	309	pci_nic_init_nofail(&nd_table[i], pci_bus,
29b358f9 DG	310	"rtl8139", i==0 ? "2" : NULL);
c2f01775	311
9caa3ec1	312	/* USB keyboard */
456dcd8a	313	usb_create_simple(usb_bus_find(-1), "usb-kbd");
9caa3ec1	314
0d78f544	315	/* Todo: register on board registers */
73f19035 AJ	316	memset(&boot_params, 0, sizeof(boot_params));
73f19035 AJ	317
e8afa065	318	if (kernel_filename) {
73f19035 AJ	319	int kernel_size;
	320
	321	kernel_size = load_image_targphys(kernel_filename,
	322	SDRAM_BASE + LINUX_LOAD_OFFSET,
	323	INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
	324	if (kernel_size < 0) {
	325	fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
	326	exit(1);
	327	}
	328
	329	/* initialization which should be done by firmware */
42874d3a PM	330	address_space_stl(&address_space_memory, SH7750_BCR1, 1 << 3,
	331	MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */
	332	address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2),
	333	MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */
4f6493ff	334	reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) \| 0xa0000000; /* Start from P2 area */
0d78f544	335	}
73f19035 AJ	336
	337	if (initrd_filename) {
	338	int initrd_size;
	339
	340	initrd_size = load_image_targphys(initrd_filename,
	341	SDRAM_BASE + INITRD_LOAD_OFFSET,
	342	SDRAM_SIZE - INITRD_LOAD_OFFSET);
	343
	344	if (initrd_size < 0) {
	345	fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
	346	exit(1);
	347	}
	348
	349	/* initialization which should be done by firmware */
cdd14a8c GR	350	boot_params.loader_type = tswap32(1);
	351	boot_params.initrd_start = tswap32(INITRD_LOAD_OFFSET);
	352	boot_params.initrd_size = tswap32(initrd_size);
73f19035 AJ	353	}
	354
	355	if (kernel_cmdline) {
9310b9be JM	356	/* I see no evidence that this .kernel_cmdline buffer requires
9310b9be JM	357	NUL-termination, so using strncpy should be ok. */
73f19035 AJ	358	strncpy(boot_params.kernel_cmdline, kernel_cmdline,
	359	sizeof(boot_params.kernel_cmdline));
	360	}
	361
	362	rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
	363	SDRAM_BASE + BOOT_PARAMS_OFFSET);
0d78f544 TS	364	}
0d78f544 TS	365
e264d29d	366	static void r2d_machine_init(MachineClass *mc)
f80f9ec9	367	{
e264d29d EH	368	mc->desc = "r2d-plus board";
e264d29d EH	369	mc->init = r2d_init;
2059839b	370	mc->block_default_type = IF_IDE;
78f60b82	371	mc->default_cpu_type = TYPE_SH7751R_CPU;
f80f9ec9 AL	372	}
f80f9ec9 AL	373
e264d29d	374	DEFINE_MACHINE("r2d", r2d_machine_init)