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target-tricore: Add instructions of BRC opcode format
[qemu.git] / target-tricore / translate.c
CommitLineData
48e06fe0
BK		 1/*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21#include "cpu.h"
22#include "disas/disas.h"
23#include "tcg-op.h"
24#include "exec/cpu_ldst.h"
25
26#include "exec/helper-proto.h"
27#include "exec/helper-gen.h"
28
7c87d074 29#include "tricore-opcodes.h"
0707ec1b 30
0aaeb118
BK		 31/*
32 * TCG registers
33 */
34static TCGv cpu_PC;
35static TCGv cpu_PCXI;
36static TCGv cpu_PSW;
37static TCGv cpu_ICR;
38/* GPR registers */
39static TCGv cpu_gpr_a[16];
40static TCGv cpu_gpr_d[16];
41/* PSW Flag cache */
42static TCGv cpu_PSW_C;
43static TCGv cpu_PSW_V;
44static TCGv cpu_PSW_SV;
45static TCGv cpu_PSW_AV;
46static TCGv cpu_PSW_SAV;
47/* CPU env */
48static TCGv_ptr cpu_env;
49
50#include "exec/gen-icount.h"
48e06fe0
BK		 51
52static const char *regnames_a[] = {
53 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
54 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
55 "a12" , "a13" , "a14" , "a15",
56 };
57
58static const char *regnames_d[] = {
59 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
60 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
61 "d12" , "d13" , "d14" , "d15",
62 };
63
0aaeb118
BK		 64typedef struct DisasContext {
65 struct TranslationBlock *tb;
66 target_ulong pc, saved_pc, next_pc;
67 uint32_t opcode;
68 int singlestep_enabled;
69 /* Routine used to access memory */
70 int mem_idx;
71 uint32_t hflags, saved_hflags;
72 int bstate;
73} DisasContext;
74
75enum {
76
77 BS_NONE = 0,
78 BS_STOP = 1,
79 BS_BRANCH = 2,
80 BS_EXCP = 3,
81};
82
48e06fe0
BK		 83void tricore_cpu_dump_state(CPUState *cs, FILE *f,
84 fprintf_function cpu_fprintf, int flags)
85{
86 TriCoreCPU *cpu = TRICORE_CPU(cs);
87 CPUTriCoreState *env = &cpu->env;
88 int i;
89
90 cpu_fprintf(f, "PC=%08x\n", env->PC);
91 for (i = 0; i < 16; ++i) {
92 if ((i & 3) == 0) {
93 cpu_fprintf(f, "GPR A%02d:", i);
94 }
95 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_a[i], env->gpr_a[i]);
96 }
97 for (i = 0; i < 16; ++i) {
98 if ((i & 3) == 0) {
99 cpu_fprintf(f, "GPR D%02d:", i);
100 }
101 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_d[i], env->gpr_d[i]);
102 }
103
104}
105
0707ec1b
BK		 106/*
107 * Functions to generate micro-ops
108 */
109
9a31922b
BK		 110/* Makros for generating helpers */
111
112#define gen_helper_1arg(name, arg) do { \
113 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
114 gen_helper_##name(cpu_env, helper_tmp); \
115 tcg_temp_free_i32(helper_tmp); \
116 } while (0)
117
59543d4e 118#define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
f718b0bb
BK		 119#define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
120 ((offset & 0x0fffff) << 1))
59543d4e 121
d2798210
BK		 122/* Functions for load/save to/from memory */
123
124static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
125 int16_t con, TCGMemOp mop)
126{
127 TCGv temp = tcg_temp_new();
128 tcg_gen_addi_tl(temp, r2, con);
129 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
130 tcg_temp_free(temp);
131}
132
133static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
134 int16_t con, TCGMemOp mop)
135{
136 TCGv temp = tcg_temp_new();
137 tcg_gen_addi_tl(temp, r2, con);
138 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
139 tcg_temp_free(temp);
140}
141
59543d4e
BK		 142static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
143{
144 TCGv_i64 temp = tcg_temp_new_i64();
145
146 tcg_gen_concat_i32_i64(temp, rl, rh);
147 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
148
149 tcg_temp_free_i64(temp);
150}
151
3a16ecb0
BK		 152static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
153 DisasContext *ctx)
154{
155 TCGv temp = tcg_temp_new();
156 tcg_gen_addi_tl(temp, base, con);
157 gen_st_2regs_64(rh, rl, temp, ctx);
158 tcg_temp_free(temp);
159}
160
59543d4e
BK		 161static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
162{
163 TCGv_i64 temp = tcg_temp_new_i64();
164
165 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
166 /* write back to two 32 bit regs */
167 tcg_gen_extr_i64_i32(rl, rh, temp);
168
169 tcg_temp_free_i64(temp);
170}
171
3a16ecb0
BK		 172static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
173 DisasContext *ctx)
174{
175 TCGv temp = tcg_temp_new();
176 tcg_gen_addi_tl(temp, base, con);
177 gen_ld_2regs_64(rh, rl, temp, ctx);
178 tcg_temp_free(temp);
179}
180
181static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
182 TCGMemOp mop)
183{
184 TCGv temp = tcg_temp_new();
185 tcg_gen_addi_tl(temp, r2, off);
186 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
187 tcg_gen_mov_tl(r2, temp);
188 tcg_temp_free(temp);
189}
190
191static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
192 TCGMemOp mop)
193{
194 TCGv temp = tcg_temp_new();
195 tcg_gen_addi_tl(temp, r2, off);
196 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
197 tcg_gen_mov_tl(r2, temp);
198 tcg_temp_free(temp);
199}
200
59543d4e
BK		 201/* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
202static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
203{
204 TCGv temp = tcg_temp_new();
205 TCGv temp2 = tcg_temp_new();
206
207 /* temp = (M(EA, word) */
208 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
209 /* temp = temp & ~E[a][63:32]) */
210 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
211 /* temp2 = (E[a][31:0] & E[a][63:32]); */
212 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
213 /* temp = temp | temp2; */
214 tcg_gen_or_tl(temp, temp, temp2);
215 /* M(EA, word) = temp; */
216 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
217
218 tcg_temp_free(temp);
219 tcg_temp_free(temp2);
220}
221
222/* tmp = M(EA, word);
223 M(EA, word) = D[a];
224 D[a] = tmp[31:0];*/
225static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
226{
227 TCGv temp = tcg_temp_new();
228
229 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
230 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
231 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
232
233 tcg_temp_free(temp);
234}
235
0707ec1b
BK		 236/* Functions for arithmetic instructions */
237
238static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
239{
240 TCGv t0 = tcg_temp_new_i32();
241 TCGv result = tcg_temp_new_i32();
242 /* Addition and set V/SV bits */
243 tcg_gen_add_tl(result, r1, r2);
244 /* calc V bit */
245 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
246 tcg_gen_xor_tl(t0, r1, r2);
247 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
248 /* Calc SV bit */
249 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
250 /* Calc AV/SAV bits */
251 tcg_gen_add_tl(cpu_PSW_AV, result, result);
252 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
253 /* calc SAV */
254 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
255 /* write back result */
256 tcg_gen_mov_tl(ret, result);
257
258 tcg_temp_free(result);
259 tcg_temp_free(t0);
260}
261
262static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
263{
264 TCGv temp = tcg_const_i32(r2);
265 gen_add_d(ret, r1, temp);
266 tcg_temp_free(temp);
267}
268
269static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
270 TCGv r4)
271{
272 TCGv temp = tcg_temp_new();
273 TCGv temp2 = tcg_temp_new();
274 TCGv result = tcg_temp_new();
275 TCGv mask = tcg_temp_new();
276 TCGv t0 = tcg_const_i32(0);
277
278 /* create mask for sticky bits */
279 tcg_gen_setcond_tl(cond, mask, r4, t0);
280 tcg_gen_shli_tl(mask, mask, 31);
281
282 tcg_gen_add_tl(result, r1, r2);
283 /* Calc PSW_V */
284 tcg_gen_xor_tl(temp, result, r1);
285 tcg_gen_xor_tl(temp2, r1, r2);
286 tcg_gen_andc_tl(temp, temp, temp2);
287 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
288 /* Set PSW_SV */
289 tcg_gen_and_tl(temp, temp, mask);
290 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
291 /* calc AV bit */
292 tcg_gen_add_tl(temp, result, result);
293 tcg_gen_xor_tl(temp, temp, result);
294 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
295 /* calc SAV bit */
296 tcg_gen_and_tl(temp, temp, mask);
297 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
298 /* write back result */
299 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r3);
300
301 tcg_temp_free(t0);
302 tcg_temp_free(temp);
303 tcg_temp_free(temp2);
304 tcg_temp_free(result);
305 tcg_temp_free(mask);
306}
307
308static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
309 TCGv r3, TCGv r4)
310{
311 TCGv temp = tcg_const_i32(r2);
312 gen_cond_add(cond, r1, temp, r3, r4);
313 tcg_temp_free(temp);
314}
315
2692802a
BK		 316static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
317{
318 TCGv temp = tcg_temp_new_i32();
319 TCGv result = tcg_temp_new_i32();
320
321 tcg_gen_sub_tl(result, r1, r2);
322 /* calc V bit */
323 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
324 tcg_gen_xor_tl(temp, r1, r2);
325 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
326 /* calc SV bit */
327 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
328 /* Calc AV bit */
329 tcg_gen_add_tl(cpu_PSW_AV, result, result);
330 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
331 /* calc SAV bit */
332 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
333 /* write back result */
334 tcg_gen_mov_tl(ret, result);
335
336 tcg_temp_free(temp);
337 tcg_temp_free(result);
338}
339
340static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
341{
342 TCGv high = tcg_temp_new();
343 TCGv low = tcg_temp_new();
344
345 tcg_gen_muls2_tl(low, high, r1, r2);
346 tcg_gen_mov_tl(ret, low);
347 /* calc V bit */
348 tcg_gen_sari_tl(low, low, 31);
349 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
350 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
351 /* calc SV bit */
352 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
353 /* Calc AV bit */
354 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
355 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
356 /* calc SAV bit */
357 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
358
359 tcg_temp_free(high);
360 tcg_temp_free(low);
361}
362
44ea3430
BK		 363static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
364{
365 TCGv sat_neg = tcg_const_i32(low);
366 TCGv temp = tcg_const_i32(up);
367
368 /* sat_neg = (arg < low ) ? low : arg; */
369 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
370
371 /* ret = (sat_neg > up ) ? up : sat_neg; */
372 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
373
374 tcg_temp_free(sat_neg);
375 tcg_temp_free(temp);
376}
377
378static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
379{
380 TCGv temp = tcg_const_i32(up);
381 /* sat_neg = (arg > up ) ? up : arg; */
382 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
383 tcg_temp_free(temp);
384}
385
0707ec1b
BK		 386static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
387{
388 if (shift_count == -32) {
389 tcg_gen_movi_tl(ret, 0);
390 } else if (shift_count >= 0) {
391 tcg_gen_shli_tl(ret, r1, shift_count);
392 } else {
393 tcg_gen_shri_tl(ret, r1, -shift_count);
394 }
395}
396
397static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
398{
399 uint32_t msk, msk_start;
400 TCGv temp = tcg_temp_new();
401 TCGv temp2 = tcg_temp_new();
402 TCGv t_0 = tcg_const_i32(0);
403
404 if (shift_count == 0) {
405 /* Clear PSW.C and PSW.V */
406 tcg_gen_movi_tl(cpu_PSW_C, 0);
407 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
408 tcg_gen_mov_tl(ret, r1);
409 } else if (shift_count == -32) {
410 /* set PSW.C */
411 tcg_gen_mov_tl(cpu_PSW_C, r1);
412 /* fill ret completly with sign bit */
413 tcg_gen_sari_tl(ret, r1, 31);
414 /* clear PSW.V */
415 tcg_gen_movi_tl(cpu_PSW_V, 0);
416 } else if (shift_count > 0) {
417 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
418 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
419
420 /* calc carry */
421 msk_start = 32 - shift_count;
422 msk = ((1 << shift_count) - 1) << msk_start;
423 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
424 /* calc v/sv bits */
425 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
426 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
427 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
428 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
429 /* calc sv */
430 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
431 /* do shift */
432 tcg_gen_shli_tl(ret, r1, shift_count);
433
434 tcg_temp_free(t_max);
435 tcg_temp_free(t_min);
436 } else {
437 /* clear PSW.V */
438 tcg_gen_movi_tl(cpu_PSW_V, 0);
439 /* calc carry */
440 msk = (1 << -shift_count) - 1;
441 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
442 /* do shift */
443 tcg_gen_sari_tl(ret, r1, -shift_count);
444 }
445 /* calc av overflow bit */
446 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
447 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
448 /* calc sav overflow bit */
449 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
450
451 tcg_temp_free(temp);
452 tcg_temp_free(temp2);
453 tcg_temp_free(t_0);
454}
455
2692802a
BK		 456static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
457{
458 gen_helper_add_ssov(ret, cpu_env, r1, r2);
459}
460
461static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
462{
463 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
464}
465
b74f2b5b
BK		 466static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
467 int pos1, int pos2,
468 void(*op1)(TCGv, TCGv, TCGv),
469 void(*op2)(TCGv, TCGv, TCGv))
470{
471 TCGv temp1, temp2;
472
473 temp1 = tcg_temp_new();
474 temp2 = tcg_temp_new();
475
476 tcg_gen_shri_tl(temp2, r2, pos2);
477 tcg_gen_shri_tl(temp1, r1, pos1);
478
479 (*op1)(temp1, temp1, temp2);
480 (*op2)(temp1 , ret, temp1);
481
482 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
483
484 tcg_temp_free(temp1);
485 tcg_temp_free(temp2);
486}
487
488/* ret = r1[pos1] op1 r2[pos2]; */
489static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
490 int pos1, int pos2,
491 void(*op1)(TCGv, TCGv, TCGv))
492{
493 TCGv temp1, temp2;
494
495 temp1 = tcg_temp_new();
496 temp2 = tcg_temp_new();
497
498 tcg_gen_shri_tl(temp2, r2, pos2);
499 tcg_gen_shri_tl(temp1, r1, pos1);
500
501 (*op1)(ret, temp1, temp2);
502
503 tcg_gen_andi_tl(ret, ret, 0x1);
504
505 tcg_temp_free(temp1);
506 tcg_temp_free(temp2);
507}
508
9a31922b
BK		 509/* helpers for generating program flow micro-ops */
510
511static inline void gen_save_pc(target_ulong pc)
512{
513 tcg_gen_movi_tl(cpu_PC, pc);
514}
515
516static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
517{
518 TranslationBlock *tb;
519 tb = ctx->tb;
520 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
521 likely(!ctx->singlestep_enabled)) {
522 tcg_gen_goto_tb(n);
523 gen_save_pc(dest);
524 tcg_gen_exit_tb((uintptr_t)tb + n);
525 } else {
526 gen_save_pc(dest);
527 if (ctx->singlestep_enabled) {
528 /* raise exception debug */
529 }
530 tcg_gen_exit_tb(0);
531 }
532}
533
534static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
535 TCGv r2, int16_t address)
536{
537 int jumpLabel;
538 jumpLabel = gen_new_label();
539 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
540
541 gen_goto_tb(ctx, 1, ctx->next_pc);
542
543 gen_set_label(jumpLabel);
544 gen_goto_tb(ctx, 0, ctx->pc + address * 2);
545}
546
547static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
548 int r2, int16_t address)
549{
550 TCGv temp = tcg_const_i32(r2);
551 gen_branch_cond(ctx, cond, r1, temp, address);
552 tcg_temp_free(temp);
553}
554
a47b50db
BK		 555static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
556{
557 int l1;
558 l1 = gen_new_label();
559
560 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
561 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
562 gen_goto_tb(ctx, 1, ctx->pc + offset);
563 gen_set_label(l1);
564 gen_goto_tb(ctx, 0, ctx->next_pc);
565}
566
9a31922b
BK		 567static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
568 int r2 , int32_t constant , int32_t offset)
569{
70b02262
BK		 570 TCGv temp;
571
9a31922b
BK		 572 switch (opc) {
573/* SB-format jumps */
574 case OPC1_16_SB_J:
575 case OPC1_32_B_J:
576 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
577 break;
f718b0bb 578 case OPC1_32_B_CALL:
9a31922b
BK		 579 case OPC1_16_SB_CALL:
580 gen_helper_1arg(call, ctx->next_pc);
581 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
582 break;
583 case OPC1_16_SB_JZ:
584 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
585 break;
586 case OPC1_16_SB_JNZ:
587 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
588 break;
70b02262
BK		 589/* SBC-format jumps */
590 case OPC1_16_SBC_JEQ:
591 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
592 break;
593 case OPC1_16_SBC_JNE:
594 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
595 break;
596/* SBRN-format jumps */
597 case OPC1_16_SBRN_JZ_T:
598 temp = tcg_temp_new();
599 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
600 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
601 tcg_temp_free(temp);
602 break;
603 case OPC1_16_SBRN_JNZ_T:
604 temp = tcg_temp_new();
605 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
606 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
607 tcg_temp_free(temp);
608 break;
a47b50db
BK		 609/* SBR-format jumps */
610 case OPC1_16_SBR_JEQ:
611 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
612 offset);
613 break;
614 case OPC1_16_SBR_JNE:
615 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
616 offset);
617 break;
618 case OPC1_16_SBR_JNZ:
619 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
620 break;
621 case OPC1_16_SBR_JNZ_A:
622 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
623 break;
624 case OPC1_16_SBR_JGEZ:
625 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
626 break;
627 case OPC1_16_SBR_JGTZ:
628 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
629 break;
630 case OPC1_16_SBR_JLEZ:
631 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
632 break;
633 case OPC1_16_SBR_JLTZ:
634 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
635 break;
636 case OPC1_16_SBR_JZ:
637 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
638 break;
639 case OPC1_16_SBR_JZ_A:
640 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
641 break;
642 case OPC1_16_SBR_LOOP:
643 gen_loop(ctx, r1, offset * 2 - 32);
644 break;
44ea3430
BK		 645/* SR-format jumps */
646 case OPC1_16_SR_JI:
647 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
648 tcg_gen_exit_tb(0);
649 break;
650 case OPC2_16_SR_RET:
651 gen_helper_ret(cpu_env);
652 tcg_gen_exit_tb(0);
653 break;
f718b0bb
BK		 654/* B-format */
655 case OPC1_32_B_CALLA:
656 gen_helper_1arg(call, ctx->next_pc);
657 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
658 break;
659 case OPC1_32_B_JLA:
660 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
661 case OPC1_32_B_JA:
662 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
663 break;
664 case OPC1_32_B_JL:
665 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
666 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
667 break;
fc2ef4a3
BK		 668/* BOL format */
669 case OPCM_32_BRC_EQ_NEQ:
670 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
671 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
672 } else {
673 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
674 }
675 break;
676 case OPCM_32_BRC_GE:
677 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
678 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
679 } else {
680 constant = MASK_OP_BRC_CONST4(ctx->opcode);
681 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
682 offset);
683 }
684 break;
685 case OPCM_32_BRC_JLT:
686 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
687 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
688 } else {
689 constant = MASK_OP_BRC_CONST4(ctx->opcode);
690 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
691 offset);
692 }
693 break;
694 case OPCM_32_BRC_JNE:
695 temp = tcg_temp_new();
696 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
697 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
698 /* subi is unconditional */
699 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
700 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
701 } else {
702 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
703 /* addi is unconditional */
704 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
705 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
706 }
707 tcg_temp_free(temp);
708 break;
9a31922b 709 default:
a47b50db 710 printf("Branch Error at %x\n", ctx->pc);
9a31922b
BK		 711 }
712 ctx->bstate = BS_BRANCH;
713}
714
715
0707ec1b
BK		 716/*
717 * Functions for decoding instructions
718 */
719
720static void decode_src_opc(DisasContext *ctx, int op1)
721{
722 int r1;
723 int32_t const4;
724 TCGv temp, temp2;
725
726 r1 = MASK_OP_SRC_S1D(ctx->opcode);
727 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
728
729 switch (op1) {
730 case OPC1_16_SRC_ADD:
731 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
732 break;
733 case OPC1_16_SRC_ADD_A15:
734 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
735 break;
736 case OPC1_16_SRC_ADD_15A:
737 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
738 break;
739 case OPC1_16_SRC_ADD_A:
740 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
741 break;
742 case OPC1_16_SRC_CADD:
743 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
744 cpu_gpr_d[15]);
745 break;
746 case OPC1_16_SRC_CADDN:
747 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
748 cpu_gpr_d[15]);
749 break;
750 case OPC1_16_SRC_CMOV:
751 temp = tcg_const_tl(0);
752 temp2 = tcg_const_tl(const4);
753 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
754 temp2, cpu_gpr_d[r1]);
755 tcg_temp_free(temp);
756 tcg_temp_free(temp2);
757 break;
758 case OPC1_16_SRC_CMOVN:
759 temp = tcg_const_tl(0);
760 temp2 = tcg_const_tl(const4);
761 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
762 temp2, cpu_gpr_d[r1]);
763 tcg_temp_free(temp);
764 tcg_temp_free(temp2);
765 break;
766 case OPC1_16_SRC_EQ:
767 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
768 const4);
769 break;
770 case OPC1_16_SRC_LT:
771 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
772 const4);
773 break;
774 case OPC1_16_SRC_MOV:
775 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
776 break;
777 case OPC1_16_SRC_MOV_A:
778 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
779 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
780 break;
781 case OPC1_16_SRC_SH:
782 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
783 break;
784 case OPC1_16_SRC_SHA:
785 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
786 break;
787 }
788}
789
2692802a
BK		 790static void decode_srr_opc(DisasContext *ctx, int op1)
791{
792 int r1, r2;
793 TCGv temp;
794
795 r1 = MASK_OP_SRR_S1D(ctx->opcode);
796 r2 = MASK_OP_SRR_S2(ctx->opcode);
797
798 switch (op1) {
799 case OPC1_16_SRR_ADD:
800 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
801 break;
802 case OPC1_16_SRR_ADD_A15:
803 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
804 break;
805 case OPC1_16_SRR_ADD_15A:
806 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
807 break;
808 case OPC1_16_SRR_ADD_A:
809 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
810 break;
811 case OPC1_16_SRR_ADDS:
812 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
813 break;
814 case OPC1_16_SRR_AND:
815 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
816 break;
817 case OPC1_16_SRR_CMOV:
818 temp = tcg_const_tl(0);
819 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
820 cpu_gpr_d[r2], cpu_gpr_d[r1]);
821 tcg_temp_free(temp);
822 break;
823 case OPC1_16_SRR_CMOVN:
824 temp = tcg_const_tl(0);
825 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
826 cpu_gpr_d[r2], cpu_gpr_d[r1]);
827 tcg_temp_free(temp);
828 break;
829 case OPC1_16_SRR_EQ:
830 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
831 cpu_gpr_d[r2]);
832 break;
833 case OPC1_16_SRR_LT:
834 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
835 cpu_gpr_d[r2]);
836 break;
837 case OPC1_16_SRR_MOV:
838 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
839 break;
840 case OPC1_16_SRR_MOV_A:
841 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
842 break;
843 case OPC1_16_SRR_MOV_AA:
844 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
845 break;
846 case OPC1_16_SRR_MOV_D:
847 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
848 break;
849 case OPC1_16_SRR_MUL:
850 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
851 break;
852 case OPC1_16_SRR_OR:
853 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
854 break;
855 case OPC1_16_SRR_SUB:
856 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
857 break;
858 case OPC1_16_SRR_SUB_A15B:
859 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
860 break;
861 case OPC1_16_SRR_SUB_15AB:
862 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
863 break;
864 case OPC1_16_SRR_SUBS:
865 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
866 break;
867 case OPC1_16_SRR_XOR:
868 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
869 break;
870 }
871}
872
46aa848f
BK		 873static void decode_ssr_opc(DisasContext *ctx, int op1)
874{
875 int r1, r2;
876
877 r1 = MASK_OP_SSR_S1(ctx->opcode);
878 r2 = MASK_OP_SSR_S2(ctx->opcode);
879
880 switch (op1) {
881 case OPC1_16_SSR_ST_A:
882 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
883 break;
884 case OPC1_16_SSR_ST_A_POSTINC:
885 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
886 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
887 break;
888 case OPC1_16_SSR_ST_B:
889 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
890 break;
891 case OPC1_16_SSR_ST_B_POSTINC:
892 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
893 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
894 break;
895 case OPC1_16_SSR_ST_H:
896 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
897 break;
898 case OPC1_16_SSR_ST_H_POSTINC:
899 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
900 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
901 break;
902 case OPC1_16_SSR_ST_W:
903 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
904 break;
905 case OPC1_16_SSR_ST_W_POSTINC:
906 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
907 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
908 break;
909 }
910}
911
5de93515
BK		 912static void decode_sc_opc(DisasContext *ctx, int op1)
913{
914 int32_t const16;
915
916 const16 = MASK_OP_SC_CONST8(ctx->opcode);
917
918 switch (op1) {
919 case OPC1_16_SC_AND:
920 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
921 break;
922 case OPC1_16_SC_BISR:
923 gen_helper_1arg(bisr, const16 & 0xff);
924 break;
925 case OPC1_16_SC_LD_A:
926 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
927 break;
928 case OPC1_16_SC_LD_W:
929 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
930 break;
931 case OPC1_16_SC_MOV:
932 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
933 break;
934 case OPC1_16_SC_OR:
935 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
936 break;
937 case OPC1_16_SC_ST_A:
938 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
939 break;
940 case OPC1_16_SC_ST_W:
941 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
942 break;
943 case OPC1_16_SC_SUB_A:
944 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
945 break;
946 }
947}
5a7634a2
BK		 948
949static void decode_slr_opc(DisasContext *ctx, int op1)
950{
951 int r1, r2;
952
953 r1 = MASK_OP_SLR_D(ctx->opcode);
954 r2 = MASK_OP_SLR_S2(ctx->opcode);
955
956 switch (op1) {
957/* SLR-format */
958 case OPC1_16_SLR_LD_A:
959 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
960 break;
961 case OPC1_16_SLR_LD_A_POSTINC:
962 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
963 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
964 break;
965 case OPC1_16_SLR_LD_BU:
966 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
967 break;
968 case OPC1_16_SLR_LD_BU_POSTINC:
969 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
970 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
971 break;
972 case OPC1_16_SLR_LD_H:
973 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
974 break;
975 case OPC1_16_SLR_LD_H_POSTINC:
976 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
977 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
978 break;
979 case OPC1_16_SLR_LD_W:
980 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
981 break;
982 case OPC1_16_SLR_LD_W_POSTINC:
983 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
984 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
985 break;
986 }
987}
988
989static void decode_sro_opc(DisasContext *ctx, int op1)
990{
991 int r2;
992 int32_t address;
993
994 r2 = MASK_OP_SRO_S2(ctx->opcode);
995 address = MASK_OP_SRO_OFF4(ctx->opcode);
996
997/* SRO-format */
998 switch (op1) {
999 case OPC1_16_SRO_LD_A:
1000 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
1001 break;
1002 case OPC1_16_SRO_LD_BU:
1003 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
1004 break;
1005 case OPC1_16_SRO_LD_H:
1006 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
1007 break;
1008 case OPC1_16_SRO_LD_W:
1009 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
1010 break;
1011 case OPC1_16_SRO_ST_A:
1012 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
1013 break;
1014 case OPC1_16_SRO_ST_B:
1015 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
1016 break;
1017 case OPC1_16_SRO_ST_H:
1018 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
1019 break;
1020 case OPC1_16_SRO_ST_W:
1021 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
1022 break;
1023 }
1024}
1025
44ea3430
BK		 1026static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
1027{
1028 uint32_t op2;
1029 op2 = MASK_OP_SR_OP2(ctx->opcode);
1030
1031 switch (op2) {
1032 case OPC2_16_SR_NOP:
1033 break;
1034 case OPC2_16_SR_RET:
1035 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
1036 break;
1037 case OPC2_16_SR_RFE:
1038 gen_helper_rfe(cpu_env);
1039 tcg_gen_exit_tb(0);
1040 ctx->bstate = BS_BRANCH;
1041 break;
1042 case OPC2_16_SR_DEBUG:
1043 /* raise EXCP_DEBUG */
1044 break;
1045 }
1046}
1047
1048static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
1049{
1050 uint32_t op2;
1051 uint32_t r1;
1052 TCGv temp;
1053
1054 r1 = MASK_OP_SR_S1D(ctx->opcode);
1055 op2 = MASK_OP_SR_OP2(ctx->opcode);
1056
1057 switch (op2) {
1058 case OPC2_16_SR_RSUB:
1059 /* overflow only if r1 = -0x80000000 */
1060 temp = tcg_const_i32(-0x80000000);
1061 /* calc V bit */
1062 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
1063 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1064 /* calc SV bit */
1065 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1066 /* sub */
1067 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
1068 /* calc av */
1069 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
1070 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
1071 /* calc sav */
1072 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1073 tcg_temp_free(temp);
1074 break;
1075 case OPC2_16_SR_SAT_B:
1076 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
1077 break;
1078 case OPC2_16_SR_SAT_BU:
1079 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
1080 break;
1081 case OPC2_16_SR_SAT_H:
1082 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
1083 break;
1084 case OPC2_16_SR_SAT_HU:
1085 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
1086 break;
1087 }
1088}
1089
0aaeb118
BK		 1090static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
1091{
0707ec1b 1092 int op1;
d2798210
BK		 1093 int r1, r2;
1094 int32_t const16;
9a31922b 1095 int32_t address;
d2798210 1096 TCGv temp;
0707ec1b
BK		 1097
1098 op1 = MASK_OP_MAJOR(ctx->opcode);
1099
d2798210
BK		 1100 /* handle ADDSC.A opcode only being 6 bit long */
1101 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
1102 op1 = OPC1_16_SRRS_ADDSC_A;
1103 }
1104
0707ec1b
BK		 1105 switch (op1) {
1106 case OPC1_16_SRC_ADD:
1107 case OPC1_16_SRC_ADD_A15:
1108 case OPC1_16_SRC_ADD_15A:
1109 case OPC1_16_SRC_ADD_A:
1110 case OPC1_16_SRC_CADD:
1111 case OPC1_16_SRC_CADDN:
1112 case OPC1_16_SRC_CMOV:
1113 case OPC1_16_SRC_CMOVN:
1114 case OPC1_16_SRC_EQ:
1115 case OPC1_16_SRC_LT:
1116 case OPC1_16_SRC_MOV:
1117 case OPC1_16_SRC_MOV_A:
1118 case OPC1_16_SRC_SH:
1119 case OPC1_16_SRC_SHA:
1120 decode_src_opc(ctx, op1);
1121 break;
2692802a
BK		 1122/* SRR-format */
1123 case OPC1_16_SRR_ADD:
1124 case OPC1_16_SRR_ADD_A15:
1125 case OPC1_16_SRR_ADD_15A:
1126 case OPC1_16_SRR_ADD_A:
1127 case OPC1_16_SRR_ADDS:
1128 case OPC1_16_SRR_AND:
1129 case OPC1_16_SRR_CMOV:
1130 case OPC1_16_SRR_CMOVN:
1131 case OPC1_16_SRR_EQ:
1132 case OPC1_16_SRR_LT:
1133 case OPC1_16_SRR_MOV:
1134 case OPC1_16_SRR_MOV_A:
1135 case OPC1_16_SRR_MOV_AA:
1136 case OPC1_16_SRR_MOV_D:
1137 case OPC1_16_SRR_MUL:
1138 case OPC1_16_SRR_OR:
1139 case OPC1_16_SRR_SUB:
1140 case OPC1_16_SRR_SUB_A15B:
1141 case OPC1_16_SRR_SUB_15AB:
1142 case OPC1_16_SRR_SUBS:
1143 case OPC1_16_SRR_XOR:
1144 decode_srr_opc(ctx, op1);
1145 break;
46aa848f
BK		 1146/* SSR-format */
1147 case OPC1_16_SSR_ST_A:
1148 case OPC1_16_SSR_ST_A_POSTINC:
1149 case OPC1_16_SSR_ST_B:
1150 case OPC1_16_SSR_ST_B_POSTINC:
1151 case OPC1_16_SSR_ST_H:
1152 case OPC1_16_SSR_ST_H_POSTINC:
1153 case OPC1_16_SSR_ST_W:
1154 case OPC1_16_SSR_ST_W_POSTINC:
1155 decode_ssr_opc(ctx, op1);
1156 break;
d2798210
BK		 1157/* SRRS-format */
1158 case OPC1_16_SRRS_ADDSC_A:
1159 r2 = MASK_OP_SRRS_S2(ctx->opcode);
1160 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
1161 const16 = MASK_OP_SRRS_N(ctx->opcode);
1162 temp = tcg_temp_new();
1163 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
1164 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
1165 tcg_temp_free(temp);
1166 break;
1167/* SLRO-format */
1168 case OPC1_16_SLRO_LD_A:
1169 r1 = MASK_OP_SLRO_D(ctx->opcode);
1170 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1171 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1172 break;
1173 case OPC1_16_SLRO_LD_BU:
1174 r1 = MASK_OP_SLRO_D(ctx->opcode);
1175 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1176 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
1177 break;
1178 case OPC1_16_SLRO_LD_H:
1179 r1 = MASK_OP_SLRO_D(ctx->opcode);
1180 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1181 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
1182 break;
1183 case OPC1_16_SLRO_LD_W:
1184 r1 = MASK_OP_SLRO_D(ctx->opcode);
1185 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1186 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1187 break;
9a31922b
BK		 1188/* SB-format */
1189 case OPC1_16_SB_CALL:
1190 case OPC1_16_SB_J:
1191 case OPC1_16_SB_JNZ:
1192 case OPC1_16_SB_JZ:
1193 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
1194 gen_compute_branch(ctx, op1, 0, 0, 0, address);
1195 break;
70b02262
BK		 1196/* SBC-format */
1197 case OPC1_16_SBC_JEQ:
1198 case OPC1_16_SBC_JNE:
1199 address = MASK_OP_SBC_DISP4(ctx->opcode);
1200 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
1201 gen_compute_branch(ctx, op1, 0, 0, const16, address);
1202 break;
1203/* SBRN-format */
1204 case OPC1_16_SBRN_JNZ_T:
1205 case OPC1_16_SBRN_JZ_T:
1206 address = MASK_OP_SBRN_DISP4(ctx->opcode);
1207 const16 = MASK_OP_SBRN_N(ctx->opcode);
1208 gen_compute_branch(ctx, op1, 0, 0, const16, address);
1209 break;
a47b50db
BK		 1210/* SBR-format */
1211 case OPC1_16_SBR_JEQ:
1212 case OPC1_16_SBR_JGEZ:
1213 case OPC1_16_SBR_JGTZ:
1214 case OPC1_16_SBR_JLEZ:
1215 case OPC1_16_SBR_JLTZ:
1216 case OPC1_16_SBR_JNE:
1217 case OPC1_16_SBR_JNZ:
1218 case OPC1_16_SBR_JNZ_A:
1219 case OPC1_16_SBR_JZ:
1220 case OPC1_16_SBR_JZ_A:
1221 case OPC1_16_SBR_LOOP:
1222 r1 = MASK_OP_SBR_S2(ctx->opcode);
1223 address = MASK_OP_SBR_DISP4(ctx->opcode);
1224 gen_compute_branch(ctx, op1, r1, 0, 0, address);
1225 break;
5de93515
BK		 1226/* SC-format */
1227 case OPC1_16_SC_AND:
1228 case OPC1_16_SC_BISR:
1229 case OPC1_16_SC_LD_A:
1230 case OPC1_16_SC_LD_W:
1231 case OPC1_16_SC_MOV:
1232 case OPC1_16_SC_OR:
1233 case OPC1_16_SC_ST_A:
1234 case OPC1_16_SC_ST_W:
1235 case OPC1_16_SC_SUB_A:
1236 decode_sc_opc(ctx, op1);
1237 break;
5a7634a2
BK		 1238/* SLR-format */
1239 case OPC1_16_SLR_LD_A:
1240 case OPC1_16_SLR_LD_A_POSTINC:
1241 case OPC1_16_SLR_LD_BU:
1242 case OPC1_16_SLR_LD_BU_POSTINC:
1243 case OPC1_16_SLR_LD_H:
1244 case OPC1_16_SLR_LD_H_POSTINC:
1245 case OPC1_16_SLR_LD_W:
1246 case OPC1_16_SLR_LD_W_POSTINC:
1247 decode_slr_opc(ctx, op1);
1248 break;
1249/* SRO-format */
1250 case OPC1_16_SRO_LD_A:
1251 case OPC1_16_SRO_LD_BU:
1252 case OPC1_16_SRO_LD_H:
1253 case OPC1_16_SRO_LD_W:
1254 case OPC1_16_SRO_ST_A:
1255 case OPC1_16_SRO_ST_B:
1256 case OPC1_16_SRO_ST_H:
1257 case OPC1_16_SRO_ST_W:
1258 decode_sro_opc(ctx, op1);
1259 break;
1260/* SSRO-format */
1261 case OPC1_16_SSRO_ST_A:
1262 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1263 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1264 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1265 break;
1266 case OPC1_16_SSRO_ST_B:
1267 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1268 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1269 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
1270 break;
1271 case OPC1_16_SSRO_ST_H:
1272 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1273 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1274 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
1275 break;
1276 case OPC1_16_SSRO_ST_W:
1277 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1278 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1279 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1280 break;
44ea3430
BK		 1281/* SR-format */
1282 case OPCM_16_SR_SYSTEM:
1283 decode_sr_system(env, ctx);
1284 break;
1285 case OPCM_16_SR_ACCU:
1286 decode_sr_accu(env, ctx);
1287 break;
1288 case OPC1_16_SR_JI:
1289 r1 = MASK_OP_SR_S1D(ctx->opcode);
1290 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
1291 break;
1292 case OPC1_16_SR_NOT:
1293 r1 = MASK_OP_SR_S1D(ctx->opcode);
1294 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
1295 break;
0707ec1b 1296 }
0aaeb118
BK		 1297}
1298
59543d4e
BK		 1299/*
1300 * 32 bit instructions
1301 */
1302
1303/* ABS-format */
1304static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
1305{
1306 int32_t op2;
1307 int32_t r1;
1308 uint32_t address;
1309 TCGv temp;
1310
1311 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1312 address = MASK_OP_ABS_OFF18(ctx->opcode);
1313 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1314
1315 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1316
1317 switch (op2) {
1318 case OPC2_32_ABS_LD_A:
1319 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
1320 break;
1321 case OPC2_32_ABS_LD_D:
1322 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
1323 break;
1324 case OPC2_32_ABS_LD_DA:
1325 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
1326 break;
1327 case OPC2_32_ABS_LD_W:
1328 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
1329 break;
1330 }
1331
1332 tcg_temp_free(temp);
1333}
1334
1335static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
1336{
1337 int32_t op2;
1338 int32_t r1;
1339 uint32_t address;
1340 TCGv temp;
1341
1342 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1343 address = MASK_OP_ABS_OFF18(ctx->opcode);
1344 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1345
1346 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1347
1348 switch (op2) {
1349 case OPC2_32_ABS_LD_B:
1350 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
1351 break;
1352 case OPC2_32_ABS_LD_BU:
1353 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
1354 break;
1355 case OPC2_32_ABS_LD_H:
1356 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
1357 break;
1358 case OPC2_32_ABS_LD_HU:
1359 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
1360 break;
1361 }
1362
1363 tcg_temp_free(temp);
1364}
1365
1366static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
1367{
1368 int32_t op2;
1369 int32_t r1;
1370 uint32_t address;
1371 TCGv temp;
1372
1373 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1374 address = MASK_OP_ABS_OFF18(ctx->opcode);
1375 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1376
1377 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1378
1379 switch (op2) {
1380 case OPC2_32_ABS_LDMST:
1381 gen_ldmst(ctx, r1, temp);
1382 break;
1383 case OPC2_32_ABS_SWAP_W:
1384 gen_swap(ctx, r1, temp);
1385 break;
1386 }
1387
1388 tcg_temp_free(temp);
1389}
1390
1391static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
1392{
1393 uint32_t op2;
1394 int32_t off18;
1395
1396 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
1397 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1398
1399 switch (op2) {
1400 case OPC2_32_ABS_LDLCX:
1401 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
1402 break;
1403 case OPC2_32_ABS_LDUCX:
1404 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
1405 break;
1406 case OPC2_32_ABS_STLCX:
1407 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
1408 break;
1409 case OPC2_32_ABS_STUCX:
1410 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
1411 break;
1412 }
1413}
1414
1415static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
1416{
1417 int32_t op2;
1418 int32_t r1;
1419 uint32_t address;
1420 TCGv temp;
1421
1422 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1423 address = MASK_OP_ABS_OFF18(ctx->opcode);
1424 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1425
1426 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1427
1428 switch (op2) {
1429 case OPC2_32_ABS_ST_A:
1430 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
1431 break;
1432 case OPC2_32_ABS_ST_D:
1433 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
1434 break;
1435 case OPC2_32_ABS_ST_DA:
1436 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
1437 break;
1438 case OPC2_32_ABS_ST_W:
1439 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
1440 break;
1441
1442 }
1443 tcg_temp_free(temp);
1444}
1445
1446static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
1447{
1448 int32_t op2;
1449 int32_t r1;
1450 uint32_t address;
1451 TCGv temp;
1452
1453 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1454 address = MASK_OP_ABS_OFF18(ctx->opcode);
1455 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1456
1457 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1458
1459 switch (op2) {
1460 case OPC2_32_ABS_ST_B:
1461 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
1462 break;
1463 case OPC2_32_ABS_ST_H:
1464 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
1465 break;
1466 }
1467 tcg_temp_free(temp);
1468}
1469
b74f2b5b
BK		 1470/* Bit-format */
1471
1472static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
1473{
1474 uint32_t op2;
1475 int r1, r2, r3;
1476 int pos1, pos2;
1477
1478 r1 = MASK_OP_BIT_S1(ctx->opcode);
1479 r2 = MASK_OP_BIT_S2(ctx->opcode);
1480 r3 = MASK_OP_BIT_D(ctx->opcode);
1481 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1482 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1483 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1484
1485
1486 switch (op2) {
1487 case OPC2_32_BIT_AND_AND_T:
1488 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1489 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
1490 break;
1491 case OPC2_32_BIT_AND_ANDN_T:
1492 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1493 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
1494 break;
1495 case OPC2_32_BIT_AND_NOR_T:
1496 if (TCG_TARGET_HAS_andc_i32) {
1497 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1498 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
1499 } else {
1500 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1501 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
1502 }
1503 break;
1504 case OPC2_32_BIT_AND_OR_T:
1505 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1506 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
1507 break;
1508 }
1509}
1510
1511static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
1512{
1513 uint32_t op2;
1514 int r1, r2, r3;
1515 int pos1, pos2;
1516 r1 = MASK_OP_BIT_S1(ctx->opcode);
1517 r2 = MASK_OP_BIT_S2(ctx->opcode);
1518 r3 = MASK_OP_BIT_D(ctx->opcode);
1519 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1520 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1521 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1522
1523 switch (op2) {
1524 case OPC2_32_BIT_AND_T:
1525 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1526 pos1, pos2, &tcg_gen_and_tl);
1527 break;
1528 case OPC2_32_BIT_ANDN_T:
1529 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1530 pos1, pos2, &tcg_gen_andc_tl);
1531 break;
1532 case OPC2_32_BIT_NOR_T:
1533 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1534 pos1, pos2, &tcg_gen_nor_tl);
1535 break;
1536 case OPC2_32_BIT_OR_T:
1537 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1538 pos1, pos2, &tcg_gen_or_tl);
1539 break;
1540 }
1541}
1542
1543static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
1544{
1545 uint32_t op2;
1546 int r1, r2, r3;
1547 int pos1, pos2;
1548 TCGv temp;
1549 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1550 r1 = MASK_OP_BIT_S1(ctx->opcode);
1551 r2 = MASK_OP_BIT_S2(ctx->opcode);
1552 r3 = MASK_OP_BIT_D(ctx->opcode);
1553 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1554 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1555
1556 temp = tcg_temp_new();
1557
1558 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
1559 if (op2 == OPC2_32_BIT_INSN_T) {
1560 tcg_gen_not_tl(temp, temp);
1561 }
1562 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
1563 tcg_temp_free(temp);
1564}
1565
1566static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
1567{
1568 uint32_t op2;
1569
1570 int r1, r2, r3;
1571 int pos1, pos2;
1572
1573 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1574 r1 = MASK_OP_BIT_S1(ctx->opcode);
1575 r2 = MASK_OP_BIT_S2(ctx->opcode);
1576 r3 = MASK_OP_BIT_D(ctx->opcode);
1577 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1578 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1579
1580 switch (op2) {
1581 case OPC2_32_BIT_NAND_T:
1582 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1583 pos1, pos2, &tcg_gen_nand_tl);
1584 break;
1585 case OPC2_32_BIT_ORN_T:
1586 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1587 pos1, pos2, &tcg_gen_orc_tl);
1588 break;
1589 case OPC2_32_BIT_XNOR_T:
1590 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1591 pos1, pos2, &tcg_gen_eqv_tl);
1592 break;
1593 case OPC2_32_BIT_XOR_T:
1594 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1595 pos1, pos2, &tcg_gen_xor_tl);
1596 break;
1597 }
1598}
1599
1600static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
1601{
1602 uint32_t op2;
1603
1604 int r1, r2, r3;
1605 int pos1, pos2;
1606
1607 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1608 r1 = MASK_OP_BIT_S1(ctx->opcode);
1609 r2 = MASK_OP_BIT_S2(ctx->opcode);
1610 r3 = MASK_OP_BIT_D(ctx->opcode);
1611 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1612 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1613
1614 switch (op2) {
1615 case OPC2_32_BIT_OR_AND_T:
1616 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1617 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
1618 break;
1619 case OPC2_32_BIT_OR_ANDN_T:
1620 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1621 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
1622 break;
1623 case OPC2_32_BIT_OR_NOR_T:
1624 if (TCG_TARGET_HAS_orc_i32) {
1625 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1626 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
1627 } else {
1628 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1629 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
1630 }
1631 break;
1632 case OPC2_32_BIT_OR_OR_T:
1633 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1634 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
1635 break;
1636 }
1637}
1638
1639static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
1640{
1641 uint32_t op2;
1642 int r1, r2, r3;
1643 int pos1, pos2;
1644 TCGv temp;
1645
1646 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1647 r1 = MASK_OP_BIT_S1(ctx->opcode);
1648 r2 = MASK_OP_BIT_S2(ctx->opcode);
1649 r3 = MASK_OP_BIT_D(ctx->opcode);
1650 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1651 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1652
1653 temp = tcg_temp_new();
1654
1655 switch (op2) {
1656 case OPC2_32_BIT_SH_AND_T:
1657 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1658 pos1, pos2, &tcg_gen_and_tl);
1659 break;
1660 case OPC2_32_BIT_SH_ANDN_T:
1661 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1662 pos1, pos2, &tcg_gen_andc_tl);
1663 break;
1664 case OPC2_32_BIT_SH_NOR_T:
1665 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1666 pos1, pos2, &tcg_gen_nor_tl);
1667 break;
1668 case OPC2_32_BIT_SH_OR_T:
1669 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1670 pos1, pos2, &tcg_gen_or_tl);
1671 break;
1672 }
1673 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
1674 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
1675 tcg_temp_free(temp);
1676}
1677
1678static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
1679{
1680 uint32_t op2;
1681 int r1, r2, r3;
1682 int pos1, pos2;
1683 TCGv temp;
1684
1685 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1686 r1 = MASK_OP_BIT_S1(ctx->opcode);
1687 r2 = MASK_OP_BIT_S2(ctx->opcode);
1688 r3 = MASK_OP_BIT_D(ctx->opcode);
1689 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1690 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1691
1692 temp = tcg_temp_new();
1693
1694 switch (op2) {
1695 case OPC2_32_BIT_SH_NAND_T:
1696 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
1697 pos1, pos2, &tcg_gen_nand_tl);
1698 break;
1699 case OPC2_32_BIT_SH_ORN_T:
1700 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1701 pos1, pos2, &tcg_gen_orc_tl);
1702 break;
1703 case OPC2_32_BIT_SH_XNOR_T:
1704 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1705 pos1, pos2, &tcg_gen_eqv_tl);
1706 break;
1707 case OPC2_32_BIT_SH_XOR_T:
1708 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1709 pos1, pos2, &tcg_gen_xor_tl);
1710 break;
1711 }
1712 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
1713 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
1714 tcg_temp_free(temp);
1715}
1716
3a16ecb0
BK		 1717/* BO-format */
1718
1719
1720static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
1721 DisasContext *ctx)
1722{
1723 uint32_t op2;
1724 uint32_t off10;
1725 int32_t r1, r2;
1726 TCGv temp;
1727
1728 r1 = MASK_OP_BO_S1D(ctx->opcode);
1729 r2 = MASK_OP_BO_S2(ctx->opcode);
1730 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
1731 op2 = MASK_OP_BO_OP2(ctx->opcode);
1732
1733 switch (op2) {
1734 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
1735 case OPC2_32_BO_CACHEA_W_SHORTOFF:
1736 case OPC2_32_BO_CACHEA_I_SHORTOFF:
1737 /* instruction to access the cache */
1738 break;
1739 case OPC2_32_BO_CACHEA_WI_POSTINC:
1740 case OPC2_32_BO_CACHEA_W_POSTINC:
1741 case OPC2_32_BO_CACHEA_I_POSTINC:
1742 /* instruction to access the cache, but we still need to handle
1743 the addressing mode */
1744 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
1745 break;
1746 case OPC2_32_BO_CACHEA_WI_PREINC:
1747 case OPC2_32_BO_CACHEA_W_PREINC:
1748 case OPC2_32_BO_CACHEA_I_PREINC:
1749 /* instruction to access the cache, but we still need to handle
1750 the addressing mode */
1751 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
1752 break;
1753 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
1754 case OPC2_32_BO_CACHEI_W_SHORTOFF:
1755 /* TODO: Raise illegal opcode trap,
1756 if tricore_feature(TRICORE_FEATURE_13) */
1757 break;
1758 case OPC2_32_BO_CACHEI_W_POSTINC:
1759 case OPC2_32_BO_CACHEI_WI_POSTINC:
1760 if (!tricore_feature(env, TRICORE_FEATURE_13)) {
1761 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
1762 } /* TODO: else raise illegal opcode trap */
1763 break;
1764 case OPC2_32_BO_CACHEI_W_PREINC:
1765 case OPC2_32_BO_CACHEI_WI_PREINC:
1766 if (!tricore_feature(env, TRICORE_FEATURE_13)) {
1767 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
1768 } /* TODO: else raise illegal opcode trap */
1769 break;
1770 case OPC2_32_BO_ST_A_SHORTOFF:
1771 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
1772 break;
1773 case OPC2_32_BO_ST_A_POSTINC:
1774 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
1775 MO_LESL);
1776 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
1777 break;
1778 case OPC2_32_BO_ST_A_PREINC:
1779 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
1780 break;
1781 case OPC2_32_BO_ST_B_SHORTOFF:
1782 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
1783 break;
1784 case OPC2_32_BO_ST_B_POSTINC:
1785 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
1786 MO_UB);
1787 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
1788 break;
1789 case OPC2_32_BO_ST_B_PREINC:
1790 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
1791 break;
1792 case OPC2_32_BO_ST_D_SHORTOFF:
1793 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
1794 off10, ctx);
1795 break;
1796 case OPC2_32_BO_ST_D_POSTINC:
1797 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
1798 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
1799 break;
1800 case OPC2_32_BO_ST_D_PREINC:
1801 temp = tcg_temp_new();
1802 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
1803 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
1804 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
1805 tcg_temp_free(temp);
1806 break;
1807 case OPC2_32_BO_ST_DA_SHORTOFF:
1808 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
1809 off10, ctx);
1810 break;
1811 case OPC2_32_BO_ST_DA_POSTINC:
1812 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
1813 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
1814 break;
1815 case OPC2_32_BO_ST_DA_PREINC:
1816 temp = tcg_temp_new();
1817 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
1818 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
1819 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
1820 tcg_temp_free(temp);
1821 break;
1822 case OPC2_32_BO_ST_H_SHORTOFF:
1823 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
1824 break;
1825 case OPC2_32_BO_ST_H_POSTINC:
1826 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
1827 MO_LEUW);
1828 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
1829 break;
1830 case OPC2_32_BO_ST_H_PREINC:
1831 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
1832 break;
1833 case OPC2_32_BO_ST_Q_SHORTOFF:
1834 temp = tcg_temp_new();
1835 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
1836 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
1837 tcg_temp_free(temp);
1838 break;
1839 case OPC2_32_BO_ST_Q_POSTINC:
1840 temp = tcg_temp_new();
1841 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
1842 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
1843 MO_LEUW);
1844 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
1845 tcg_temp_free(temp);
1846 break;
1847 case OPC2_32_BO_ST_Q_PREINC:
1848 temp = tcg_temp_new();
1849 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
1850 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
1851 tcg_temp_free(temp);
1852 break;
1853 case OPC2_32_BO_ST_W_SHORTOFF:
1854 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
1855 break;
1856 case OPC2_32_BO_ST_W_POSTINC:
1857 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
1858 MO_LEUL);
1859 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
1860 break;
1861 case OPC2_32_BO_ST_W_PREINC:
1862 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
1863 break;
1864 }
1865}
1866
1867static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
1868 DisasContext *ctx)
1869{
1870 uint32_t op2;
1871 uint32_t off10;
1872 int32_t r1, r2;
1873 TCGv temp, temp2, temp3;
1874
1875 r1 = MASK_OP_BO_S1D(ctx->opcode);
1876 r2 = MASK_OP_BO_S2(ctx->opcode);
1877 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
1878 op2 = MASK_OP_BO_OP2(ctx->opcode);
1879
1880 temp = tcg_temp_new();
1881 temp2 = tcg_temp_new();
1882 temp3 = tcg_const_i32(off10);
1883
1884 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
1885 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
1886
1887 switch (op2) {
1888 case OPC2_32_BO_CACHEA_WI_BR:
1889 case OPC2_32_BO_CACHEA_W_BR:
1890 case OPC2_32_BO_CACHEA_I_BR:
1891 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
1892 break;
1893 case OPC2_32_BO_CACHEA_WI_CIRC:
1894 case OPC2_32_BO_CACHEA_W_CIRC:
1895 case OPC2_32_BO_CACHEA_I_CIRC:
1896 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
1897 break;
1898 case OPC2_32_BO_ST_A_BR:
1899 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
1900 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
1901 break;
1902 case OPC2_32_BO_ST_A_CIRC:
1903 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
1904 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
1905 break;
1906 case OPC2_32_BO_ST_B_BR:
1907 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
1908 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
1909 break;
1910 case OPC2_32_BO_ST_B_CIRC:
1911 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
1912 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
1913 break;
1914 case OPC2_32_BO_ST_D_BR:
1915 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
1916 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
1917 break;
1918 case OPC2_32_BO_ST_D_CIRC:
1919 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
1920 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
1921 tcg_gen_addi_tl(temp, temp, 4);
1922 tcg_gen_rem_tl(temp, temp, temp2);
1923 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
1924 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
1925 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
1926 break;
1927 case OPC2_32_BO_ST_DA_BR:
1928 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
1929 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
1930 break;
1931 case OPC2_32_BO_ST_DA_CIRC:
1932 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
1933 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
1934 tcg_gen_addi_tl(temp, temp, 4);
1935 tcg_gen_rem_tl(temp, temp, temp2);
1936 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
1937 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
1938 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
1939 break;
1940 case OPC2_32_BO_ST_H_BR:
1941 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
1942 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
1943 break;
1944 case OPC2_32_BO_ST_H_CIRC:
1945 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
1946 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
1947 break;
1948 case OPC2_32_BO_ST_Q_BR:
1949 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
1950 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
1951 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
1952 break;
1953 case OPC2_32_BO_ST_Q_CIRC:
1954 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
1955 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
1956 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
1957 break;
1958 case OPC2_32_BO_ST_W_BR:
1959 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
1960 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
1961 break;
1962 case OPC2_32_BO_ST_W_CIRC:
1963 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
1964 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
1965 break;
1966 }
1967 tcg_temp_free(temp);
1968 tcg_temp_free(temp2);
1969 tcg_temp_free(temp3);
1970}
1971
1972static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env,
1973 DisasContext *ctx)
1974{
1975 uint32_t op2;
1976 uint32_t off10;
1977 int32_t r1, r2;
1978 TCGv temp;
1979
1980 r1 = MASK_OP_BO_S1D(ctx->opcode);
1981 r2 = MASK_OP_BO_S2(ctx->opcode);
1982 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
1983 op2 = MASK_OP_BO_OP2(ctx->opcode);
1984
1985 switch (op2) {
1986 case OPC2_32_BO_LD_A_SHORTOFF:
1987 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
1988 break;
1989 case OPC2_32_BO_LD_A_POSTINC:
1990 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
1991 MO_LEUL);
1992 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
1993 break;
1994 case OPC2_32_BO_LD_A_PREINC:
1995 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
1996 break;
1997 case OPC2_32_BO_LD_B_SHORTOFF:
1998 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
1999 break;
2000 case OPC2_32_BO_LD_B_POSTINC:
2001 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2002 MO_SB);
2003 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2004 break;
2005 case OPC2_32_BO_LD_B_PREINC:
2006 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
2007 break;
2008 case OPC2_32_BO_LD_BU_SHORTOFF:
2009 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
2010 break;
2011 case OPC2_32_BO_LD_BU_POSTINC:
2012 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2013 MO_UB);
2014 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2015 break;
2016 case OPC2_32_BO_LD_BU_PREINC:
2017 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
2018 break;
2019 case OPC2_32_BO_LD_D_SHORTOFF:
2020 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
2021 off10, ctx);
2022 break;
2023 case OPC2_32_BO_LD_D_POSTINC:
2024 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
2025 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2026 break;
2027 case OPC2_32_BO_LD_D_PREINC:
2028 temp = tcg_temp_new();
2029 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2030 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
2031 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
2032 tcg_temp_free(temp);
2033 break;
2034 case OPC2_32_BO_LD_DA_SHORTOFF:
2035 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
2036 off10, ctx);
2037 break;
2038 case OPC2_32_BO_LD_DA_POSTINC:
2039 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
2040 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2041 break;
2042 case OPC2_32_BO_LD_DA_PREINC:
2043 temp = tcg_temp_new();
2044 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2045 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
2046 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
2047 tcg_temp_free(temp);
2048 break;
2049 case OPC2_32_BO_LD_H_SHORTOFF:
2050 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
2051 break;
2052 case OPC2_32_BO_LD_H_POSTINC:
2053 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2054 MO_LESW);
2055 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2056 break;
2057 case OPC2_32_BO_LD_H_PREINC:
2058 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
2059 break;
2060 case OPC2_32_BO_LD_HU_SHORTOFF:
2061 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2062 break;
2063 case OPC2_32_BO_LD_HU_POSTINC:
2064 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2065 MO_LEUW);
2066 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2067 break;
2068 case OPC2_32_BO_LD_HU_PREINC:
2069 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2070 break;
2071 case OPC2_32_BO_LD_Q_SHORTOFF:
2072 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2073 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2074 break;
2075 case OPC2_32_BO_LD_Q_POSTINC:
2076 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2077 MO_LEUW);
2078 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2079 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2080 break;
2081 case OPC2_32_BO_LD_Q_PREINC:
2082 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2083 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2084 break;
2085 case OPC2_32_BO_LD_W_SHORTOFF:
2086 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2087 break;
2088 case OPC2_32_BO_LD_W_POSTINC:
2089 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2090 MO_LEUL);
2091 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2092 break;
2093 case OPC2_32_BO_LD_W_PREINC:
2094 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2095 break;
2096 }
2097}
2098
2099static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env,
2100 DisasContext *ctx)
2101{
2102 uint32_t op2;
2103 uint32_t off10;
2104 int r1, r2;
2105
2106 TCGv temp, temp2, temp3;
2107
2108 r1 = MASK_OP_BO_S1D(ctx->opcode);
2109 r2 = MASK_OP_BO_S2(ctx->opcode);
2110 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2111 op2 = MASK_OP_BO_OP2(ctx->opcode);
2112
2113 temp = tcg_temp_new();
2114 temp2 = tcg_temp_new();
2115 temp3 = tcg_const_i32(off10);
2116
2117 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
2118 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2119
2120
2121 switch (op2) {
2122 case OPC2_32_BO_LD_A_BR:
2123 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2124 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2125 break;
2126 case OPC2_32_BO_LD_A_CIRC:
2127 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2128 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2129 break;
2130 case OPC2_32_BO_LD_B_BR:
2131 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
2132 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2133 break;
2134 case OPC2_32_BO_LD_B_CIRC:
2135 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
2136 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2137 break;
2138 case OPC2_32_BO_LD_BU_BR:
2139 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
2140 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2141 break;
2142 case OPC2_32_BO_LD_BU_CIRC:
2143 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
2144 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2145 break;
2146 case OPC2_32_BO_LD_D_BR:
2147 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
2148 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2149 break;
2150 case OPC2_32_BO_LD_D_CIRC:
2151 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2152 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
2153 tcg_gen_addi_tl(temp, temp, 4);
2154 tcg_gen_rem_tl(temp, temp, temp2);
2155 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2156 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
2157 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2158 break;
2159 case OPC2_32_BO_LD_DA_BR:
2160 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
2161 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2162 break;
2163 case OPC2_32_BO_LD_DA_CIRC:
2164 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2165 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
2166 tcg_gen_addi_tl(temp, temp, 4);
2167 tcg_gen_rem_tl(temp, temp, temp2);
2168 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2169 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
2170 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2171 break;
2172 case OPC2_32_BO_LD_H_BR:
2173 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
2174 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2175 break;
2176 case OPC2_32_BO_LD_H_CIRC:
2177 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
2178 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2179 break;
2180 case OPC2_32_BO_LD_HU_BR:
2181 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2182 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2183 break;
2184 case OPC2_32_BO_LD_HU_CIRC:
2185 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2186 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2187 break;
2188 case OPC2_32_BO_LD_Q_BR:
2189 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2190 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2191 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2192 break;
2193 case OPC2_32_BO_LD_Q_CIRC:
2194 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2195 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2196 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2197 break;
2198 case OPC2_32_BO_LD_W_BR:
2199 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2200 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2201 break;
2202 case OPC2_32_BO_LD_W_CIRC:
2203 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2204 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2205 break;
2206 }
2207 tcg_temp_free(temp);
2208 tcg_temp_free(temp2);
2209 tcg_temp_free(temp3);
2210}
2211
2212static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
2213 DisasContext *ctx)
2214{
2215 uint32_t op2;
2216 uint32_t off10;
2217 int r1, r2;
2218
2219 TCGv temp, temp2;
2220
2221 r1 = MASK_OP_BO_S1D(ctx->opcode);
2222 r2 = MASK_OP_BO_S2(ctx->opcode);
2223 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2224 op2 = MASK_OP_BO_OP2(ctx->opcode);
2225
2226
2227 temp = tcg_temp_new();
2228 temp2 = tcg_temp_new();
2229
2230 switch (op2) {
2231 case OPC2_32_BO_LDLCX_SHORTOFF:
2232 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2233 gen_helper_ldlcx(cpu_env, temp);
2234 break;
2235 case OPC2_32_BO_LDMST_SHORTOFF:
2236 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2237 gen_ldmst(ctx, r1, temp);
2238 break;
2239 case OPC2_32_BO_LDMST_POSTINC:
2240 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
2241 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2242 break;
2243 case OPC2_32_BO_LDMST_PREINC:
2244 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2245 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
2246 break;
2247 case OPC2_32_BO_LDUCX_SHORTOFF:
2248 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2249 gen_helper_lducx(cpu_env, temp);
2250 break;
2251 case OPC2_32_BO_LEA_SHORTOFF:
2252 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
2253 break;
2254 case OPC2_32_BO_STLCX_SHORTOFF:
2255 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2256 gen_helper_stlcx(cpu_env, temp);
2257 break;
2258 case OPC2_32_BO_STUCX_SHORTOFF:
2259 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2260 gen_helper_stucx(cpu_env, temp);
2261 break;
2262 case OPC2_32_BO_SWAP_W_SHORTOFF:
2263 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2264 gen_swap(ctx, r1, temp);
2265 break;
2266 case OPC2_32_BO_SWAP_W_POSTINC:
2267 gen_swap(ctx, r1, cpu_gpr_a[r2]);
2268 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2269 break;
2270 case OPC2_32_BO_SWAP_W_PREINC:
2271 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2272 gen_swap(ctx, r1, cpu_gpr_a[r2]);
2273 break;
2274 }
2275 tcg_temp_free(temp);
2276 tcg_temp_free(temp2);
2277}
2278
2279static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
2280 DisasContext *ctx)
2281{
2282 uint32_t op2;
2283 uint32_t off10;
2284 int r1, r2;
2285
2286 TCGv temp, temp2, temp3;
2287
2288 r1 = MASK_OP_BO_S1D(ctx->opcode);
2289 r2 = MASK_OP_BO_S2(ctx->opcode);
2290 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2291 op2 = MASK_OP_BO_OP2(ctx->opcode);
2292
2293 temp = tcg_temp_new();
2294 temp2 = tcg_temp_new();
2295 temp3 = tcg_const_i32(off10);
2296
2297 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
2298 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2299
2300 switch (op2) {
2301 case OPC2_32_BO_LDMST_BR:
2302 gen_ldmst(ctx, r1, temp2);
2303 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2304 break;
2305 case OPC2_32_BO_LDMST_CIRC:
2306 gen_ldmst(ctx, r1, temp2);
2307 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2308 break;
2309 case OPC2_32_BO_SWAP_W_BR:
2310 gen_swap(ctx, r1, temp2);
2311 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2312 break;
2313 case OPC2_32_BO_SWAP_W_CIRC:
2314 gen_swap(ctx, r1, temp2);
2315 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2316 break;
2317 }
2318 tcg_temp_free(temp);
2319 tcg_temp_free(temp2);
2320 tcg_temp_free(temp3);
2321}
2322
3fb763cb
BK		 2323static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
2324{
2325 int r1, r2;
2326 int32_t address;
2327 TCGv temp;
2328
2329 r1 = MASK_OP_BOL_S1D(ctx->opcode);
2330 r2 = MASK_OP_BOL_S2(ctx->opcode);
2331 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
2332
2333 switch (op1) {
2334 case OPC1_32_BOL_LD_A_LONGOFF:
2335 temp = tcg_temp_new();
2336 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
2337 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
2338 tcg_temp_free(temp);
2339 break;
2340 case OPC1_32_BOL_LD_W_LONFOFF:
2341 temp = tcg_temp_new();
2342 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
2343 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
2344 tcg_temp_free(temp);
2345 break;
2346 case OPC1_32_BOL_LEA_LONGOFF:
2347 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
2348 break;
2349 case OPC1_32_BOL_ST_A_LONGOFF:
2350 if (tricore_feature(env, TRICORE_FEATURE_16)) {
2351 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
2352 } else {
2353 /* raise illegal opcode trap */
2354 }
2355 break;
2356 case OPC1_32_BOL_ST_W_LONGOFF:
2357 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
2358 break;
2359 }
2360
2361}
2362
0aaeb118
BK		 2363static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
2364{
59543d4e
BK		 2365 int op1;
2366 int32_t r1;
2367 int32_t address;
fc2ef4a3 2368 int8_t b, const4;
59543d4e
BK		 2369 int32_t bpos;
2370 TCGv temp, temp2;
2371
2372 op1 = MASK_OP_MAJOR(ctx->opcode);
2373
2374 switch (op1) {
2375/* ABS-format */
2376 case OPCM_32_ABS_LDW:
2377 decode_abs_ldw(env, ctx);
2378 break;
2379 case OPCM_32_ABS_LDB:
2380 decode_abs_ldb(env, ctx);
2381 break;
2382 case OPCM_32_ABS_LDMST_SWAP:
2383 decode_abs_ldst_swap(env, ctx);
2384 break;
2385 case OPCM_32_ABS_LDST_CONTEXT:
2386 decode_abs_ldst_context(env, ctx);
2387 break;
2388 case OPCM_32_ABS_STORE:
2389 decode_abs_store(env, ctx);
2390 break;
2391 case OPCM_32_ABS_STOREB_H:
2392 decode_abs_storeb_h(env, ctx);
2393 break;
2394 case OPC1_32_ABS_STOREQ:
2395 address = MASK_OP_ABS_OFF18(ctx->opcode);
2396 r1 = MASK_OP_ABS_S1D(ctx->opcode);
2397 temp = tcg_const_i32(EA_ABS_FORMAT(address));
2398 temp2 = tcg_temp_new();
2399
2400 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
2401 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
2402
2403 tcg_temp_free(temp2);
2404 tcg_temp_free(temp);
2405 break;
2406 case OPC1_32_ABS_LD_Q:
2407 address = MASK_OP_ABS_OFF18(ctx->opcode);
2408 r1 = MASK_OP_ABS_S1D(ctx->opcode);
2409 temp = tcg_const_i32(EA_ABS_FORMAT(address));
2410
2411 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
2412 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2413
2414 tcg_temp_free(temp);
2415 break;
2416 case OPC1_32_ABS_LEA:
2417 address = MASK_OP_ABS_OFF18(ctx->opcode);
2418 r1 = MASK_OP_ABS_S1D(ctx->opcode);
2419 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
2420 break;
2421/* ABSB-format */
2422 case OPC1_32_ABSB_ST_T:
2423 address = MASK_OP_ABS_OFF18(ctx->opcode);
2424 b = MASK_OP_ABSB_B(ctx->opcode);
2425 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
2426
2427 temp = tcg_const_i32(EA_ABS_FORMAT(address));
2428 temp2 = tcg_temp_new();
2429
2430 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
2431 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
2432 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
2433 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
2434
2435 tcg_temp_free(temp);
2436 tcg_temp_free(temp2);
2437 break;
f718b0bb
BK		 2438/* B-format */
2439 case OPC1_32_B_CALL:
2440 case OPC1_32_B_CALLA:
2441 case OPC1_32_B_J:
2442 case OPC1_32_B_JA:
2443 case OPC1_32_B_JL:
2444 case OPC1_32_B_JLA:
2445 address = MASK_OP_B_DISP24(ctx->opcode);
2446 gen_compute_branch(ctx, op1, 0, 0, 0, address);
2447 break;
b74f2b5b
BK		 2448/* Bit-format */
2449 case OPCM_32_BIT_ANDACC:
2450 decode_bit_andacc(env, ctx);
2451 break;
2452 case OPCM_32_BIT_LOGICAL_T1:
2453 decode_bit_logical_t(env, ctx);
2454 break;
2455 case OPCM_32_BIT_INSERT:
2456 decode_bit_insert(env, ctx);
2457 break;
2458 case OPCM_32_BIT_LOGICAL_T2:
2459 decode_bit_logical_t2(env, ctx);
2460 break;
2461 case OPCM_32_BIT_ORAND:
2462 decode_bit_orand(env, ctx);
2463 break;
2464 case OPCM_32_BIT_SH_LOGIC1:
2465 decode_bit_sh_logic1(env, ctx);
2466 break;
2467 case OPCM_32_BIT_SH_LOGIC2:
2468 decode_bit_sh_logic2(env, ctx);
2469 break;
3a16ecb0
BK		 2470 /* BO Format */
2471 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
2472 decode_bo_addrmode_post_pre_base(env, ctx);
2473 break;
2474 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
2475 decode_bo_addrmode_bitreverse_circular(env, ctx);
2476 break;
2477 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
2478 decode_bo_addrmode_ld_post_pre_base(env, ctx);
2479 break;
2480 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
2481 decode_bo_addrmode_ld_bitreverse_circular(env, ctx);
2482 break;
2483 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
2484 decode_bo_addrmode_stctx_post_pre_base(env, ctx);
2485 break;
2486 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
2487 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx);
2488 break;
3fb763cb
BK		 2489/* BOL-format */
2490 case OPC1_32_BOL_LD_A_LONGOFF:
2491 case OPC1_32_BOL_LD_W_LONFOFF:
2492 case OPC1_32_BOL_LEA_LONGOFF:
2493 case OPC1_32_BOL_ST_W_LONGOFF:
2494 case OPC1_32_BOL_ST_A_LONGOFF:
2495 decode_bol_opc(env, ctx, op1);
2496 break;
fc2ef4a3
BK		 2497/* BRC Format */
2498 case OPCM_32_BRC_EQ_NEQ:
2499 case OPCM_32_BRC_GE:
2500 case OPCM_32_BRC_JLT:
2501 case OPCM_32_BRC_JNE:
2502 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
2503 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
2504 r1 = MASK_OP_BRC_S1(ctx->opcode);
2505 gen_compute_branch(ctx, op1, r1, 0, const4, address);
2506 break;
59543d4e 2507 }
0aaeb118
BK		 2508}
2509
2510static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
2511{
2512 /* 16-Bit Instruction */
2513 if ((ctx->opcode & 0x1) == 0) {
2514 ctx->next_pc = ctx->pc + 2;
2515 decode_16Bit_opc(env, ctx);
2516 /* 32-Bit Instruction */
2517 } else {
2518 ctx->next_pc = ctx->pc + 4;
2519 decode_32Bit_opc(env, ctx);
2520 }
2521}
2522
48e06fe0
BK		 2523static inline void
2524gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
2525 int search_pc)
2526{
0aaeb118
BK		 2527 CPUState *cs = CPU(cpu);
2528 CPUTriCoreState *env = &cpu->env;
2529 DisasContext ctx;
2530 target_ulong pc_start;
2531 int num_insns;
2532 uint16_t *gen_opc_end;
2533
2534 if (search_pc) {
2535 qemu_log("search pc %d\n", search_pc);
2536 }
2537
2538 num_insns = 0;
2539 pc_start = tb->pc;
2540 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
2541 ctx.pc = pc_start;
2542 ctx.saved_pc = -1;
2543 ctx.tb = tb;
2544 ctx.singlestep_enabled = cs->singlestep_enabled;
2545 ctx.bstate = BS_NONE;
2546 ctx.mem_idx = cpu_mmu_index(env);
2547
2548 tcg_clear_temp_count();
2549 gen_tb_start();
2550 while (ctx.bstate == BS_NONE) {
2551 ctx.opcode = cpu_ldl_code(env, ctx.pc);
2552 decode_opc(env, &ctx, 0);
2553
2554 num_insns++;
2555
2556 if (tcg_ctx.gen_opc_ptr >= gen_opc_end) {
9a31922b
BK		 2557 gen_save_pc(ctx.next_pc);
2558 tcg_gen_exit_tb(0);
0aaeb118
BK		 2559 break;
2560 }
2561 if (singlestep) {
9a31922b
BK		 2562 gen_save_pc(ctx.next_pc);
2563 tcg_gen_exit_tb(0);
0aaeb118
BK		 2564 break;
2565 }
2566 ctx.pc = ctx.next_pc;
2567 }
2568
2569 gen_tb_end(tb, num_insns);
2570 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
2571 if (search_pc) {
2572 printf("done_generating search pc\n");
2573 } else {
2574 tb->size = ctx.pc - pc_start;
2575 tb->icount = num_insns;
2576 }
2577 if (tcg_check_temp_count()) {
2578 printf("LEAK at %08x\n", env->PC);
2579 }
2580
2581#ifdef DEBUG_DISAS
2582 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
2583 qemu_log("IN: %s\n", lookup_symbol(pc_start));
2584 log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
2585 qemu_log("\n");
2586 }
2587#endif
48e06fe0
BK		 2588}
2589
2590void
2591gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
2592{
2593 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
2594}
2595
2596void
2597gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb)
2598{
2599 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
2600}
2601
2602void
2603restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos)
2604{
2605 env->PC = tcg_ctx.gen_opc_pc[pc_pos];
2606}
2607/*
2608 *
2609 * Initialization
2610 *
2611 */
2612
2613void cpu_state_reset(CPUTriCoreState *env)
2614{
0aaeb118
BK		 2615 /* Reset Regs to Default Value */
2616 env->PSW = 0xb80;
2617}
2618
2619static void tricore_tcg_init_csfr(void)
2620{
2621 cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
2622 offsetof(CPUTriCoreState, PCXI), "PCXI");
2623 cpu_PSW = tcg_global_mem_new(TCG_AREG0,
2624 offsetof(CPUTriCoreState, PSW), "PSW");
2625 cpu_PC = tcg_global_mem_new(TCG_AREG0,
2626 offsetof(CPUTriCoreState, PC), "PC");
2627 cpu_ICR = tcg_global_mem_new(TCG_AREG0,
2628 offsetof(CPUTriCoreState, ICR), "ICR");
48e06fe0
BK		 2629}
2630
2631void tricore_tcg_init(void)
2632{
0aaeb118
BK		 2633 int i;
2634 static int inited;
2635 if (inited) {
2636 return;
2637 }
2638 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
2639 /* reg init */
2640 for (i = 0 ; i < 16 ; i++) {
2641 cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
2642 offsetof(CPUTriCoreState, gpr_a[i]),
2643 regnames_a[i]);
2644 }
2645 for (i = 0 ; i < 16 ; i++) {
2646 cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
2647 offsetof(CPUTriCoreState, gpr_d[i]),
2648 regnames_d[i]);
2649 }
2650 tricore_tcg_init_csfr();
2651 /* init PSW flag cache */
2652 cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
2653 offsetof(CPUTriCoreState, PSW_USB_C),
2654 "PSW_C");
2655 cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
2656 offsetof(CPUTriCoreState, PSW_USB_V),
2657 "PSW_V");
2658 cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
2659 offsetof(CPUTriCoreState, PSW_USB_SV),
2660 "PSW_SV");
2661 cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
2662 offsetof(CPUTriCoreState, PSW_USB_AV),
2663 "PSW_AV");
2664 cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
2665 offsetof(CPUTriCoreState, PSW_USB_SAV),
2666 "PSW_SAV");
48e06fe0 2667}
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