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ab93bbe2 FB |
1 | /* |
2 | * common defines for all CPUs | |
5fafdf24 | 3 | * |
ab93bbe2 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
ab93bbe2 FB |
18 | */ |
19 | #ifndef CPU_DEFS_H | |
20 | #define CPU_DEFS_H | |
21 | ||
87ecb68b PB |
22 | #ifndef NEED_CPU_H |
23 | #error cpu.h included from common code | |
24 | #endif | |
25 | ||
ab93bbe2 FB |
26 | #include "config.h" |
27 | #include <setjmp.h> | |
ed1c0bcb | 28 | #include <inttypes.h> |
be214e6c | 29 | #include <signal.h> |
ed1c0bcb | 30 | #include "osdep.h" |
72cf2d4f | 31 | #include "qemu-queue.h" |
1ad2134f | 32 | #include "targphys.h" |
ab93bbe2 | 33 | |
35b66fc4 FB |
34 | #ifndef TARGET_LONG_BITS |
35 | #error TARGET_LONG_BITS must be defined before including this header | |
36 | #endif | |
37 | ||
38 | #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) | |
39 | ||
ab6d960f | 40 | /* target_ulong is the type of a virtual address */ |
35b66fc4 FB |
41 | #if TARGET_LONG_SIZE == 4 |
42 | typedef int32_t target_long; | |
43 | typedef uint32_t target_ulong; | |
c27004ec | 44 | #define TARGET_FMT_lx "%08x" |
b62b461b | 45 | #define TARGET_FMT_ld "%d" |
71c8b8fd | 46 | #define TARGET_FMT_lu "%u" |
35b66fc4 FB |
47 | #elif TARGET_LONG_SIZE == 8 |
48 | typedef int64_t target_long; | |
49 | typedef uint64_t target_ulong; | |
26a76461 | 50 | #define TARGET_FMT_lx "%016" PRIx64 |
b62b461b | 51 | #define TARGET_FMT_ld "%" PRId64 |
71c8b8fd | 52 | #define TARGET_FMT_lu "%" PRIu64 |
35b66fc4 FB |
53 | #else |
54 | #error TARGET_LONG_SIZE undefined | |
55 | #endif | |
56 | ||
f193c797 FB |
57 | #define HOST_LONG_SIZE (HOST_LONG_BITS / 8) |
58 | ||
2be0071f FB |
59 | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
60 | #define EXCP_HLT 0x10001 /* hlt instruction reached */ | |
61 | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ | |
5a1e3cfc | 62 | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ |
ab93bbe2 | 63 | |
a316d335 FB |
64 | #define TB_JMP_CACHE_BITS 12 |
65 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
66 | ||
b362e5e0 PB |
67 | /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for |
68 | addresses on the same page. The top bits are the same. This allows | |
69 | TLB invalidation to quickly clear a subset of the hash table. */ | |
70 | #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) | |
71 | #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) | |
72 | #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) | |
73 | #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) | |
74 | ||
20cb400d | 75 | #if !defined(CONFIG_USER_ONLY) |
84b7b8e7 FB |
76 | #define CPU_TLB_BITS 8 |
77 | #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) | |
ab93bbe2 | 78 | |
355b1943 | 79 | #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 |
d656469f FB |
80 | #define CPU_TLB_ENTRY_BITS 4 |
81 | #else | |
82 | #define CPU_TLB_ENTRY_BITS 5 | |
83 | #endif | |
84 | ||
ab93bbe2 | 85 | typedef struct CPUTLBEntry { |
0f459d16 PB |
86 | /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address |
87 | bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not | |
88 | go directly to ram. | |
db8d7466 FB |
89 | bit 3 : indicates that the entry is invalid |
90 | bit 2..0 : zero | |
91 | */ | |
5fafdf24 TS |
92 | target_ulong addr_read; |
93 | target_ulong addr_write; | |
94 | target_ulong addr_code; | |
355b1943 | 95 | /* Addend to virtual address to get host address. IO accesses |
ee50add9 | 96 | use the corresponding iotlb value. */ |
355b1943 | 97 | unsigned long addend; |
d656469f FB |
98 | /* padding to get a power of two size */ |
99 | uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - | |
100 | (sizeof(target_ulong) * 3 + | |
355b1943 PB |
101 | ((-sizeof(target_ulong) * 3) & (sizeof(unsigned long) - 1)) + |
102 | sizeof(unsigned long))]; | |
ab93bbe2 FB |
103 | } CPUTLBEntry; |
104 | ||
355b1943 PB |
105 | extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BITS) ? 1 : -1]; |
106 | ||
20cb400d PB |
107 | #define CPU_COMMON_TLB \ |
108 | /* The meaning of the MMU modes is defined in the target code. */ \ | |
109 | CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ | |
110 | target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ | |
d4c430a8 PB |
111 | target_ulong tlb_flush_addr; \ |
112 | target_ulong tlb_flush_mask; | |
20cb400d PB |
113 | |
114 | #else | |
115 | ||
116 | #define CPU_COMMON_TLB | |
117 | ||
118 | #endif | |
119 | ||
120 | ||
e2542fe2 | 121 | #ifdef HOST_WORDS_BIGENDIAN |
2e70f6ef PB |
122 | typedef struct icount_decr_u16 { |
123 | uint16_t high; | |
124 | uint16_t low; | |
125 | } icount_decr_u16; | |
126 | #else | |
127 | typedef struct icount_decr_u16 { | |
128 | uint16_t low; | |
129 | uint16_t high; | |
130 | } icount_decr_u16; | |
131 | #endif | |
132 | ||
7ba1e619 AL |
133 | struct kvm_run; |
134 | struct KVMState; | |
e82bcec2 | 135 | struct qemu_work_item; |
7ba1e619 | 136 | |
a1d1bb31 AL |
137 | typedef struct CPUBreakpoint { |
138 | target_ulong pc; | |
139 | int flags; /* BP_* */ | |
72cf2d4f | 140 | QTAILQ_ENTRY(CPUBreakpoint) entry; |
a1d1bb31 AL |
141 | } CPUBreakpoint; |
142 | ||
143 | typedef struct CPUWatchpoint { | |
144 | target_ulong vaddr; | |
145 | target_ulong len_mask; | |
146 | int flags; /* BP_* */ | |
72cf2d4f | 147 | QTAILQ_ENTRY(CPUWatchpoint) entry; |
a1d1bb31 AL |
148 | } CPUWatchpoint; |
149 | ||
a20e31dc | 150 | #define CPU_TEMP_BUF_NLONGS 128 |
a316d335 FB |
151 | #define CPU_COMMON \ |
152 | struct TranslationBlock *current_tb; /* currently executing TB */ \ | |
153 | /* soft mmu support */ \ | |
2e70f6ef PB |
154 | /* in order to avoid passing too many arguments to the MMIO \ |
155 | helpers, we store some rarely used information in the CPU \ | |
a316d335 | 156 | context) */ \ |
2e70f6ef PB |
157 | unsigned long mem_io_pc; /* host pc at which the memory was \ |
158 | accessed */ \ | |
159 | target_ulong mem_io_vaddr; /* target virtual addr at which the \ | |
160 | memory was accessed */ \ | |
9656f324 PB |
161 | uint32_t halted; /* Nonzero if the CPU is in suspend state */ \ |
162 | uint32_t interrupt_request; \ | |
be214e6c | 163 | volatile sig_atomic_t exit_request; \ |
20cb400d | 164 | CPU_COMMON_TLB \ |
a316d335 | 165 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ |
a20e31dc BS |
166 | /* buffer for temporaries in the code generator */ \ |
167 | long temp_buf[CPU_TEMP_BUF_NLONGS]; \ | |
a316d335 | 168 | \ |
2e70f6ef PB |
169 | int64_t icount_extra; /* Instructions until next timer event. */ \ |
170 | /* Number of cycles left, with interrupt flag in high bit. \ | |
171 | This allows a single read-compare-cbranch-write sequence to test \ | |
172 | for both decrementer underflow and exceptions. */ \ | |
173 | union { \ | |
174 | uint32_t u32; \ | |
175 | icount_decr_u16 u16; \ | |
176 | } icount_decr; \ | |
177 | uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ | |
178 | \ | |
a316d335 FB |
179 | /* from this point: preserved by CPU reset */ \ |
180 | /* ice debug support */ \ | |
72cf2d4f | 181 | QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ |
a316d335 FB |
182 | int singlestep_enabled; \ |
183 | \ | |
72cf2d4f | 184 | QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ |
a1d1bb31 | 185 | CPUWatchpoint *watchpoint_hit; \ |
56aebc89 PB |
186 | \ |
187 | struct GDBRegisterState *gdb_regs; \ | |
6658ffb8 | 188 | \ |
9133e39b FB |
189 | /* Core interrupt code */ \ |
190 | jmp_buf jmp_env; \ | |
acb6685f | 191 | int exception_index; \ |
9133e39b | 192 | \ |
c2764719 | 193 | CPUState *next_cpu; /* next CPU sharing TB cache */ \ |
6a00d601 | 194 | int cpu_index; /* CPU index (informative) */ \ |
1e9fa730 | 195 | uint32_t host_tid; /* host thread ID */ \ |
268a362c | 196 | int numa_node; /* NUMA node this cpu is belonging to */ \ |
dc6b1c09 AP |
197 | int nr_cores; /* number of cores within this CPU package */ \ |
198 | int nr_threads;/* number of threads within this CPU */ \ | |
d5975363 | 199 | int running; /* Nonzero if cpu is currently running(usermode). */ \ |
a316d335 | 200 | /* user data */ \ |
01ba9816 TS |
201 | void *opaque; \ |
202 | \ | |
d6dc3d42 | 203 | uint32_t created; \ |
ced6c051 MT |
204 | uint32_t stop; /* Stop request */ \ |
205 | uint32_t stopped; /* Artificially stopped */ \ | |
d6dc3d42 AL |
206 | struct QemuThread *thread; \ |
207 | struct QemuCond *halt_cond; \ | |
e82bcec2 | 208 | struct qemu_work_item *queued_work_first, *queued_work_last; \ |
7ba1e619 AL |
209 | const char *cpu_model_str; \ |
210 | struct KVMState *kvm_state; \ | |
211 | struct kvm_run *kvm_run; \ | |
9ded2744 JK |
212 | int kvm_fd; \ |
213 | int kvm_vcpu_dirty; | |
a316d335 | 214 | |
ab93bbe2 | 215 | #endif |