[qemu.git] / tests / fdc-test.c

/*
 * Floppy test cases.
 *
 * Copyright (c) 2012 Kevin Wolf <[email protected]>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <stdint.h>
#include <string.h>
#include <stdio.h>

#include <glib.h>

#include "libqtest.h"
#include "qemu-common.h"

#define TEST_IMAGE_SIZE 1440 * 1024

#define FLOPPY_BASE 0x3f0
#define FLOPPY_IRQ 6

enum {
    reg_sra         = 0x0,
    reg_srb         = 0x1,
    reg_dor         = 0x2,
    reg_msr         = 0x4,
    reg_dsr         = 0x4,
    reg_fifo        = 0x5,
    reg_dir         = 0x7,
};

enum {
    CMD_SENSE_INT           = 0x08,
    CMD_READ_ID             = 0x0a,
    CMD_SEEK                = 0x0f,
    CMD_VERIFY              = 0x16,
    CMD_READ                = 0xe6,
    CMD_RELATIVE_SEEK_OUT   = 0x8f,
    CMD_RELATIVE_SEEK_IN    = 0xcf,
};

enum {
    BUSY    = 0x10,
    NONDMA  = 0x20,
    RQM     = 0x80,
    DIO     = 0x40,

    DSKCHG  = 0x80,
};

static char test_image[] = "/tmp/qtest.XXXXXX";

#define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
#define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)

static uint8_t base = 0x70;

enum {
    CMOS_FLOPPY     = 0x10,
};

static void floppy_send(uint8_t byte)
{
    uint8_t msr;

    msr = inb(FLOPPY_BASE + reg_msr);
    assert_bit_set(msr, RQM);
    assert_bit_clear(msr, DIO);

    outb(FLOPPY_BASE + reg_fifo, byte);
}

static uint8_t floppy_recv(void)
{
    uint8_t msr;

    msr = inb(FLOPPY_BASE + reg_msr);
    assert_bit_set(msr, RQM | DIO);

    return inb(FLOPPY_BASE + reg_fifo);
}

/* pcn: Present Cylinder Number */
static void ack_irq(uint8_t *pcn)
{
    uint8_t ret;

    g_assert(get_irq(FLOPPY_IRQ));
    floppy_send(CMD_SENSE_INT);
    floppy_recv();

    ret = floppy_recv();
    if (pcn != NULL) {
        *pcn = ret;
    }

    g_assert(!get_irq(FLOPPY_IRQ));
}

static uint8_t send_read_command(uint8_t cmd)
{
    uint8_t drive = 0;
    uint8_t head = 0;
    uint8_t cyl = 0;
    uint8_t sect_addr = 1;
    uint8_t sect_size = 2;
    uint8_t eot = 1;
    uint8_t gap = 0x1b;
    uint8_t gpl = 0xff;

    uint8_t msr = 0;
    uint8_t st0;

    uint8_t ret = 0;

    floppy_send(cmd);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);
    floppy_send(head);
    floppy_send(sect_addr);
    floppy_send(sect_size);
    floppy_send(eot);
    floppy_send(gap);
    floppy_send(gpl);

    uint8_t i = 0;
    uint8_t n = 2;
    for (; i < n; i++) {
        msr = inb(FLOPPY_BASE + reg_msr);
        if (msr == 0xd0) {
            break;
        }
        sleep(1);
    }

    if (i >= n) {
        return 1;
    }

    st0 = floppy_recv();
    if (st0 != 0x40) {
        ret = 1;
    }

    floppy_recv();
    floppy_recv();
    floppy_recv();
    floppy_recv();
    floppy_recv();
    floppy_recv();

    return ret;
}

static uint8_t send_read_no_dma_command(int nb_sect, uint8_t expected_st0)
{
    uint8_t drive = 0;
    uint8_t head = 0;
    uint8_t cyl = 0;
    uint8_t sect_addr = 1;
    uint8_t sect_size = 2;
    uint8_t eot = nb_sect;
    uint8_t gap = 0x1b;
    uint8_t gpl = 0xff;

    uint8_t msr = 0;
    uint8_t st0;

    uint8_t ret = 0;

    floppy_send(CMD_READ);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);
    floppy_send(head);
    floppy_send(sect_addr);
    floppy_send(sect_size);
    floppy_send(eot);
    floppy_send(gap);
    floppy_send(gpl);

    uint16_t i = 0;
    uint8_t n = 2;
    for (; i < n; i++) {
        msr = inb(FLOPPY_BASE + reg_msr);
        if (msr == (BUSY | NONDMA | DIO | RQM)) {
            break;
        }
        sleep(1);
    }

    if (i >= n) {
        return 1;
    }

    /* Non-DMA mode */
    for (i = 0; i < 512 * 2 * nb_sect; i++) {
        msr = inb(FLOPPY_BASE + reg_msr);
        assert_bit_set(msr, BUSY | RQM | DIO);
        inb(FLOPPY_BASE + reg_fifo);
    }

    msr = inb(FLOPPY_BASE + reg_msr);
    assert_bit_set(msr, BUSY | RQM | DIO);
    g_assert(get_irq(FLOPPY_IRQ));

    st0 = floppy_recv();
    if (st0 != expected_st0) {
        ret = 1;
    }

    floppy_recv();
    floppy_recv();
    floppy_recv();
    floppy_recv();
    floppy_recv();
    g_assert(get_irq(FLOPPY_IRQ));
    floppy_recv();

    /* Check that we're back in command phase */
    msr = inb(FLOPPY_BASE + reg_msr);
    assert_bit_clear(msr, BUSY | DIO);
    assert_bit_set(msr, RQM);
    g_assert(!get_irq(FLOPPY_IRQ));

    return ret;
}

static void send_seek(int cyl)
{
    int drive = 0;
    int head = 0;

    floppy_send(CMD_SEEK);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);
    ack_irq(NULL);
}

static uint8_t cmos_read(uint8_t reg)
{
    outb(base + 0, reg);
    return inb(base + 1);
}

static void test_cmos(void)
{
    uint8_t cmos;

    cmos = cmos_read(CMOS_FLOPPY);
    g_assert(cmos == 0x40);
}

static void test_no_media_on_start(void)
{
    uint8_t dir;

    /* Media changed bit must be set all time after start if there is
     * no media in drive. */
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    send_seek(1);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
}

static void test_read_without_media(void)
{
    uint8_t ret;

    ret = send_read_command(CMD_READ);
    g_assert(ret == 0);
}

static void test_media_insert(void)
{
    uint8_t dir;

    /* Insert media in drive. DSKCHK should not be reset until a step pulse
     * is sent. */
    qmp_discard_response("{'execute':'change', 'arguments':{"
                         " 'device':'floppy0', 'target': %s, 'arg': 'raw' }}",
                         test_image);
    qmp_discard_response(""); /* ignore event
                                 (FIXME open -> open transition?!) */
    qmp_discard_response(""); /* ignore event */

    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);

    send_seek(0);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);

    /* Step to next track should clear DSKCHG bit. */
    send_seek(1);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_clear(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_clear(dir, DSKCHG);
}

static void test_media_change(void)
{
    uint8_t dir;

    test_media_insert();

    /* Eject the floppy and check that DSKCHG is set. Reading it out doesn't
     * reset the bit. */
    qmp_discard_response("{'execute':'eject', 'arguments':{"
                         " 'device':'floppy0' }}");
    qmp_discard_response(""); /* ignore event */

    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);

    send_seek(0);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);

    send_seek(1);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
}

static void test_sense_interrupt(void)
{
    int drive = 0;
    int head = 0;
    int cyl = 0;
    int ret = 0;

    floppy_send(CMD_SENSE_INT);
    ret = floppy_recv();
    g_assert(ret == 0x80);

    floppy_send(CMD_SEEK);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);

    floppy_send(CMD_SENSE_INT);
    ret = floppy_recv();
    g_assert(ret == 0x20);
    floppy_recv();
}

static void test_relative_seek(void)
{
    uint8_t drive = 0;
    uint8_t head = 0;
    uint8_t cyl = 1;
    uint8_t pcn;

    /* Send seek to track 0 */
    send_seek(0);

    /* Send relative seek to increase track by 1 */
    floppy_send(CMD_RELATIVE_SEEK_IN);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);

    ack_irq(&pcn);
    g_assert(pcn == 1);

    /* Send relative seek to decrease track by 1 */
    floppy_send(CMD_RELATIVE_SEEK_OUT);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);

    ack_irq(&pcn);
    g_assert(pcn == 0);
}

static void test_read_id(void)
{
    uint8_t drive = 0;
    uint8_t head = 0;
    uint8_t cyl;
    uint8_t st0;
    uint8_t msr;

    /* Seek to track 0 and check with READ ID */
    send_seek(0);

    floppy_send(CMD_READ_ID);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(head << 2 | drive);

    msr = inb(FLOPPY_BASE + reg_msr);
    if (!get_irq(FLOPPY_IRQ)) {
        assert_bit_set(msr, BUSY);
        assert_bit_clear(msr, RQM);
    }

    while (!get_irq(FLOPPY_IRQ)) {
        /* qemu involves a timer with READ ID... */
        clock_step(1000000000LL / 50);
    }

    msr = inb(FLOPPY_BASE + reg_msr);
    assert_bit_set(msr, BUSY | RQM | DIO);

    st0 = floppy_recv();
    floppy_recv();
    floppy_recv();
    cyl = floppy_recv();
    head = floppy_recv();
    floppy_recv();
    g_assert(get_irq(FLOPPY_IRQ));
    floppy_recv();
    g_assert(!get_irq(FLOPPY_IRQ));

    g_assert_cmpint(cyl, ==, 0);
    g_assert_cmpint(head, ==, 0);
    g_assert_cmpint(st0, ==, head << 2);

    /* Seek to track 8 on head 1 and check with READ ID */
    head = 1;
    cyl = 8;

    floppy_send(CMD_SEEK);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);
    g_assert(get_irq(FLOPPY_IRQ));
    ack_irq(NULL);

    floppy_send(CMD_READ_ID);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(head << 2 | drive);

    msr = inb(FLOPPY_BASE + reg_msr);
    if (!get_irq(FLOPPY_IRQ)) {
        assert_bit_set(msr, BUSY);
        assert_bit_clear(msr, RQM);
    }

    while (!get_irq(FLOPPY_IRQ)) {
        /* qemu involves a timer with READ ID... */
        clock_step(1000000000LL / 50);
    }

    msr = inb(FLOPPY_BASE + reg_msr);
    assert_bit_set(msr, BUSY | RQM | DIO);

    st0 = floppy_recv();
    floppy_recv();
    floppy_recv();
    cyl = floppy_recv();
    head = floppy_recv();
    floppy_recv();
    g_assert(get_irq(FLOPPY_IRQ));
    floppy_recv();
    g_assert(!get_irq(FLOPPY_IRQ));

    g_assert_cmpint(cyl, ==, 8);
    g_assert_cmpint(head, ==, 1);
    g_assert_cmpint(st0, ==, head << 2);
}

static void test_read_no_dma_1(void)
{
    uint8_t ret;

    outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
    send_seek(0);
    ret = send_read_no_dma_command(1, 0x04);
    g_assert(ret == 0);
}

static void test_read_no_dma_18(void)
{
    uint8_t ret;

    outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
    send_seek(0);
    ret = send_read_no_dma_command(18, 0x04);
    g_assert(ret == 0);
}

static void test_read_no_dma_19(void)
{
    uint8_t ret;

    outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
    send_seek(0);
    ret = send_read_no_dma_command(19, 0x20);
    g_assert(ret == 0);
}

static void test_verify(void)
{
    uint8_t ret;

    ret = send_read_command(CMD_VERIFY);
    g_assert(ret == 0);
}

/* success if no crash or abort */
static void fuzz_registers(void)
{
    unsigned int i;

    for (i = 0; i < 1000; i++) {
        uint8_t reg, val;

        reg = (uint8_t)g_test_rand_int_range(0, 8);
        val = (uint8_t)g_test_rand_int_range(0, 256);

        outb(FLOPPY_BASE + reg, val);
        inb(FLOPPY_BASE + reg);
    }
}

int main(int argc, char **argv)
{
    const char *arch = qtest_get_arch();
    int fd;
    int ret;

    /* Check architecture */
    if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
        g_test_message("Skipping test for non-x86\n");
        return 0;
    }

    /* Create a temporary raw image */
    fd = mkstemp(test_image);
    g_assert(fd >= 0);
    ret = ftruncate(fd, TEST_IMAGE_SIZE);
    g_assert(ret == 0);
    close(fd);

    /* Run the tests */
    g_test_init(&argc, &argv, NULL);

    qtest_start(NULL);
    qtest_irq_intercept_in(global_qtest, "ioapic");
    qtest_add_func("/fdc/cmos", test_cmos);
    qtest_add_func("/fdc/no_media_on_start", test_no_media_on_start);
    qtest_add_func("/fdc/read_without_media", test_read_without_media);
    qtest_add_func("/fdc/media_change", test_media_change);
    qtest_add_func("/fdc/sense_interrupt", test_sense_interrupt);
    qtest_add_func("/fdc/relative_seek", test_relative_seek);
    qtest_add_func("/fdc/read_id", test_read_id);
    qtest_add_func("/fdc/verify", test_verify);
    qtest_add_func("/fdc/media_insert", test_media_insert);
    qtest_add_func("/fdc/read_no_dma_1", test_read_no_dma_1);
    qtest_add_func("/fdc/read_no_dma_18", test_read_no_dma_18);
    qtest_add_func("/fdc/read_no_dma_19", test_read_no_dma_19);
    qtest_add_func("/fdc/fuzz-registers", fuzz_registers);

    ret = g_test_run();

    /* Cleanup */
    qtest_end();
    unlink(test_image);

    return ret;
}
Commit	Line	Data
93e9eb68 KW	1	/*
	2	* Floppy test cases.
	3	*
	4	* Copyright (c) 2012 Kevin Wolf <[email protected]>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include <stdint.h>
	26	#include <string.h>
	27	#include <stdio.h>
	28
	29	#include <glib.h>
	30
	31	#include "libqtest.h"
	32	#include "qemu-common.h"
	33
	34	#define TEST_IMAGE_SIZE 1440 * 1024
	35
	36	#define FLOPPY_BASE 0x3f0
	37	#define FLOPPY_IRQ 6
	38
	39	enum {
	40	reg_sra = 0x0,
	41	reg_srb = 0x1,
	42	reg_dor = 0x2,
	43	reg_msr = 0x4,
	44	reg_dsr = 0x4,
	45	reg_fifo = 0x5,
	46	reg_dir = 0x7,
	47	};
	48
	49	enum {
98272dbb	50	CMD_SENSE_INT = 0x08,
67f194bd	51	CMD_READ_ID = 0x0a,
98272dbb	52	CMD_SEEK = 0x0f,
6f442fe8	53	CMD_VERIFY = 0x16,
98272dbb PH	54	CMD_READ = 0xe6,
	55	CMD_RELATIVE_SEEK_OUT = 0x8f,
	56	CMD_RELATIVE_SEEK_IN = 0xcf,
93e9eb68 KW	57	};
	58
	59	enum {
5f8ae8e2 HP	60	BUSY = 0x10,
5f8ae8e2 HP	61	NONDMA = 0x20,
93e9eb68 KW	62	RQM = 0x80,
	63	DIO = 0x40,
	64
	65	DSKCHG = 0x80,
	66	};
	67
748bfb4e	68	static char test_image[] = "/tmp/qtest.XXXXXX";
93e9eb68 KW	69
	70	#define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
	71	#define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
	72
7cd33161 PH	73	static uint8_t base = 0x70;
	74
	75	enum {
	76	CMOS_FLOPPY = 0x10,
	77	};
	78
93e9eb68 KW	79	static void floppy_send(uint8_t byte)
	80	{
	81	uint8_t msr;
	82
	83	msr = inb(FLOPPY_BASE + reg_msr);
	84	assert_bit_set(msr, RQM);
	85	assert_bit_clear(msr, DIO);
	86
	87	outb(FLOPPY_BASE + reg_fifo, byte);
	88	}
	89
	90	static uint8_t floppy_recv(void)
	91	{
	92	uint8_t msr;
	93
	94	msr = inb(FLOPPY_BASE + reg_msr);
	95	assert_bit_set(msr, RQM \| DIO);
	96
	97	return inb(FLOPPY_BASE + reg_fifo);
	98	}
	99
c3cdc1b0 KW	100	/* pcn: Present Cylinder Number */
c3cdc1b0 KW	101	static void ack_irq(uint8_t *pcn)
93e9eb68	102	{
98272dbb PH	103	uint8_t ret;
98272dbb PH	104
93e9eb68 KW	105	g_assert(get_irq(FLOPPY_IRQ));
	106	floppy_send(CMD_SENSE_INT);
	107	floppy_recv();
c3cdc1b0	108
98272dbb	109	ret = floppy_recv();
c3cdc1b0 KW	110	if (pcn != NULL) {
	111	*pcn = ret;
	112	}
98272dbb	113
c3cdc1b0	114	g_assert(!get_irq(FLOPPY_IRQ));
93e9eb68 KW	115	}
93e9eb68 KW	116
6f442fe8	117	static uint8_t send_read_command(uint8_t cmd)
8b9ef60d PH	118	{
	119	uint8_t drive = 0;
	120	uint8_t head = 0;
	121	uint8_t cyl = 0;
	122	uint8_t sect_addr = 1;
	123	uint8_t sect_size = 2;
	124	uint8_t eot = 1;
	125	uint8_t gap = 0x1b;
	126	uint8_t gpl = 0xff;
	127
	128	uint8_t msr = 0;
	129	uint8_t st0;
	130
	131	uint8_t ret = 0;
	132
6f442fe8	133	floppy_send(cmd);
8b9ef60d PH	134	floppy_send(head << 2 \| drive);
	135	g_assert(!get_irq(FLOPPY_IRQ));
	136	floppy_send(cyl);
	137	floppy_send(head);
	138	floppy_send(sect_addr);
	139	floppy_send(sect_size);
	140	floppy_send(eot);
	141	floppy_send(gap);
	142	floppy_send(gpl);
	143
	144	uint8_t i = 0;
	145	uint8_t n = 2;
	146	for (; i < n; i++) {
	147	msr = inb(FLOPPY_BASE + reg_msr);
	148	if (msr == 0xd0) {
	149	break;
	150	}
	151	sleep(1);
	152	}
	153
	154	if (i >= n) {
	155	return 1;
	156	}
	157
	158	st0 = floppy_recv();
075f5532	159	if (st0 != 0x40) {
8b9ef60d PH	160	ret = 1;
	161	}
	162
	163	floppy_recv();
	164	floppy_recv();
	165	floppy_recv();
	166	floppy_recv();
	167	floppy_recv();
	168	floppy_recv();
	169
	170	return ret;
	171	}
	172
5f8ae8e2 HP	173	static uint8_t send_read_no_dma_command(int nb_sect, uint8_t expected_st0)
	174	{
	175	uint8_t drive = 0;
	176	uint8_t head = 0;
	177	uint8_t cyl = 0;
	178	uint8_t sect_addr = 1;
	179	uint8_t sect_size = 2;
	180	uint8_t eot = nb_sect;
	181	uint8_t gap = 0x1b;
	182	uint8_t gpl = 0xff;
	183
	184	uint8_t msr = 0;
	185	uint8_t st0;
	186
	187	uint8_t ret = 0;
	188
	189	floppy_send(CMD_READ);
	190	floppy_send(head << 2 \| drive);
	191	g_assert(!get_irq(FLOPPY_IRQ));
	192	floppy_send(cyl);
	193	floppy_send(head);
	194	floppy_send(sect_addr);
	195	floppy_send(sect_size);
	196	floppy_send(eot);
	197	floppy_send(gap);
	198	floppy_send(gpl);
	199
	200	uint16_t i = 0;
	201	uint8_t n = 2;
	202	for (; i < n; i++) {
	203	msr = inb(FLOPPY_BASE + reg_msr);
	204	if (msr == (BUSY \| NONDMA \| DIO \| RQM)) {
	205	break;
	206	}
	207	sleep(1);
	208	}
	209
	210	if (i >= n) {
	211	return 1;
	212	}
	213
	214	/* Non-DMA mode */
	215	for (i = 0; i < 512 * 2 * nb_sect; i++) {
	216	msr = inb(FLOPPY_BASE + reg_msr);
	217	assert_bit_set(msr, BUSY \| RQM \| DIO);
	218	inb(FLOPPY_BASE + reg_fifo);
	219	}
	220
4964e18e KW	221	msr = inb(FLOPPY_BASE + reg_msr);
	222	assert_bit_set(msr, BUSY \| RQM \| DIO);
	223	g_assert(get_irq(FLOPPY_IRQ));
	224
5f8ae8e2 HP	225	st0 = floppy_recv();
	226	if (st0 != expected_st0) {
	227	ret = 1;
	228	}
	229
	230	floppy_recv();
	231	floppy_recv();
	232	floppy_recv();
	233	floppy_recv();
	234	floppy_recv();
4964e18e	235	g_assert(get_irq(FLOPPY_IRQ));
5f8ae8e2 HP	236	floppy_recv();
5f8ae8e2 HP	237
4964e18e KW	238	/* Check that we're back in command phase */
	239	msr = inb(FLOPPY_BASE + reg_msr);
	240	assert_bit_clear(msr, BUSY \| DIO);
	241	assert_bit_set(msr, RQM);
	242	g_assert(!get_irq(FLOPPY_IRQ));
	243
5f8ae8e2 HP	244	return ret;
	245	}
	246
c3cdc1b0	247	static void send_seek(int cyl)
93e9eb68 KW	248	{
	249	int drive = 0;
	250	int head = 0;
93e9eb68 KW	251
	252	floppy_send(CMD_SEEK);
	253	floppy_send(head << 2 \| drive);
	254	g_assert(!get_irq(FLOPPY_IRQ));
	255	floppy_send(cyl);
c3cdc1b0	256	ack_irq(NULL);
93e9eb68 KW	257	}
93e9eb68 KW	258
7cd33161	259	static uint8_t cmos_read(uint8_t reg)
93e9eb68	260	{
7cd33161 PH	261	outb(base + 0, reg);
	262	return inb(base + 1);
	263	}
93e9eb68	264
7cd33161 PH	265	static void test_cmos(void)
	266	{
	267	uint8_t cmos;
93e9eb68	268
7cd33161 PH	269	cmos = cmos_read(CMOS_FLOPPY);
	270	g_assert(cmos == 0x40);
	271	}
93e9eb68	272
7cd33161 PH	273	static void test_no_media_on_start(void)
	274	{
	275	uint8_t dir;
	276
	277	/* Media changed bit must be set all time after start if there is
	278	* no media in drive. */
93e9eb68 KW	279	dir = inb(FLOPPY_BASE + reg_dir);
	280	assert_bit_set(dir, DSKCHG);
	281	dir = inb(FLOPPY_BASE + reg_dir);
	282	assert_bit_set(dir, DSKCHG);
c3cdc1b0	283	send_seek(1);
93e9eb68 KW	284	dir = inb(FLOPPY_BASE + reg_dir);
	285	assert_bit_set(dir, DSKCHG);
	286	dir = inb(FLOPPY_BASE + reg_dir);
	287	assert_bit_set(dir, DSKCHG);
7cd33161 PH	288	}
7cd33161 PH	289
8b9ef60d PH	290	static void test_read_without_media(void)
	291	{
	292	uint8_t ret;
	293
6f442fe8	294	ret = send_read_command(CMD_READ);
8b9ef60d PH	295	g_assert(ret == 0);
	296	}
	297
1f507913	298	static void test_media_insert(void)
7cd33161 PH	299	{
7cd33161 PH	300	uint8_t dir;
93e9eb68	301
7cd33161	302	/* Insert media in drive. DSKCHK should not be reset until a step pulse
93e9eb68	303	* is sent. */
0d1aa05e	304	qmp_discard_response("{'execute':'change', 'arguments':{"
b8e665e4	305	" 'device':'floppy0', 'target': %s, 'arg': 'raw' }}",
0d1aa05e SH	306	test_image);
	307	qmp_discard_response(""); /* ignore event
	308	(FIXME open -> open transition?!) */
	309	qmp_discard_response(""); /* ignore event */
93e9eb68 KW	310
	311	dir = inb(FLOPPY_BASE + reg_dir);
	312	assert_bit_set(dir, DSKCHG);
	313	dir = inb(FLOPPY_BASE + reg_dir);
	314	assert_bit_set(dir, DSKCHG);
	315
c3cdc1b0	316	send_seek(0);
59240c34 PH	317	dir = inb(FLOPPY_BASE + reg_dir);
	318	assert_bit_set(dir, DSKCHG);
	319	dir = inb(FLOPPY_BASE + reg_dir);
	320	assert_bit_set(dir, DSKCHG);
	321
	322	/* Step to next track should clear DSKCHG bit. */
c3cdc1b0	323	send_seek(1);
93e9eb68 KW	324	dir = inb(FLOPPY_BASE + reg_dir);
	325	assert_bit_clear(dir, DSKCHG);
	326	dir = inb(FLOPPY_BASE + reg_dir);
	327	assert_bit_clear(dir, DSKCHG);
1f507913 HP	328	}
	329
	330	static void test_media_change(void)
	331	{
	332	uint8_t dir;
	333
	334	test_media_insert();
7cd33161 PH	335
	336	/* Eject the floppy and check that DSKCHG is set. Reading it out doesn't
	337	* reset the bit. */
0d1aa05e SH	338	qmp_discard_response("{'execute':'eject', 'arguments':{"
	339	" 'device':'floppy0' }}");
	340	qmp_discard_response(""); /* ignore event */
7cd33161 PH	341
	342	dir = inb(FLOPPY_BASE + reg_dir);
	343	assert_bit_set(dir, DSKCHG);
	344	dir = inb(FLOPPY_BASE + reg_dir);
	345	assert_bit_set(dir, DSKCHG);
	346
c3cdc1b0	347	send_seek(0);
59240c34 PH	348	dir = inb(FLOPPY_BASE + reg_dir);
	349	assert_bit_set(dir, DSKCHG);
	350	dir = inb(FLOPPY_BASE + reg_dir);
	351	assert_bit_set(dir, DSKCHG);
	352
c3cdc1b0	353	send_seek(1);
7cd33161 PH	354	dir = inb(FLOPPY_BASE + reg_dir);
	355	assert_bit_set(dir, DSKCHG);
	356	dir = inb(FLOPPY_BASE + reg_dir);
	357	assert_bit_set(dir, DSKCHG);
93e9eb68 KW	358	}
93e9eb68 KW	359
b3ce604e PH	360	static void test_sense_interrupt(void)
	361	{
	362	int drive = 0;
	363	int head = 0;
	364	int cyl = 0;
	365	int ret = 0;
	366
	367	floppy_send(CMD_SENSE_INT);
	368	ret = floppy_recv();
	369	g_assert(ret == 0x80);
	370
	371	floppy_send(CMD_SEEK);
	372	floppy_send(head << 2 \| drive);
	373	g_assert(!get_irq(FLOPPY_IRQ));
	374	floppy_send(cyl);
	375
	376	floppy_send(CMD_SENSE_INT);
	377	ret = floppy_recv();
	378	g_assert(ret == 0x20);
	379	floppy_recv();
	380	}
	381
98272dbb PH	382	static void test_relative_seek(void)
	383	{
	384	uint8_t drive = 0;
	385	uint8_t head = 0;
	386	uint8_t cyl = 1;
c3cdc1b0	387	uint8_t pcn;
98272dbb PH	388
98272dbb PH	389	/* Send seek to track 0 */
c3cdc1b0	390	send_seek(0);
98272dbb PH	391
	392	/* Send relative seek to increase track by 1 */
	393	floppy_send(CMD_RELATIVE_SEEK_IN);
	394	floppy_send(head << 2 \| drive);
	395	g_assert(!get_irq(FLOPPY_IRQ));
	396	floppy_send(cyl);
	397
c3cdc1b0 KW	398	ack_irq(&pcn);
c3cdc1b0 KW	399	g_assert(pcn == 1);
98272dbb PH	400
	401	/* Send relative seek to decrease track by 1 */
	402	floppy_send(CMD_RELATIVE_SEEK_OUT);
	403	floppy_send(head << 2 \| drive);
	404	g_assert(!get_irq(FLOPPY_IRQ));
	405	floppy_send(cyl);
	406
c3cdc1b0 KW	407	ack_irq(&pcn);
c3cdc1b0 KW	408	g_assert(pcn == 0);
98272dbb PH	409	}
98272dbb PH	410
67f194bd KW	411	static void test_read_id(void)
	412	{
	413	uint8_t drive = 0;
	414	uint8_t head = 0;
	415	uint8_t cyl;
	416	uint8_t st0;
4964e18e	417	uint8_t msr;
67f194bd KW	418
	419	/* Seek to track 0 and check with READ ID */
	420	send_seek(0);
	421
	422	floppy_send(CMD_READ_ID);
	423	g_assert(!get_irq(FLOPPY_IRQ));
	424	floppy_send(head << 2 \| drive);
	425
4964e18e KW	426	msr = inb(FLOPPY_BASE + reg_msr);
	427	if (!get_irq(FLOPPY_IRQ)) {
	428	assert_bit_set(msr, BUSY);
	429	assert_bit_clear(msr, RQM);
	430	}
	431
67f194bd KW	432	while (!get_irq(FLOPPY_IRQ)) {
	433	/* qemu involves a timer with READ ID... */
	434	clock_step(1000000000LL / 50);
	435	}
	436
4964e18e KW	437	msr = inb(FLOPPY_BASE + reg_msr);
	438	assert_bit_set(msr, BUSY \| RQM \| DIO);
	439
67f194bd KW	440	st0 = floppy_recv();
	441	floppy_recv();
	442	floppy_recv();
	443	cyl = floppy_recv();
	444	head = floppy_recv();
	445	floppy_recv();
4964e18e	446	g_assert(get_irq(FLOPPY_IRQ));
67f194bd	447	floppy_recv();
4964e18e	448	g_assert(!get_irq(FLOPPY_IRQ));
67f194bd KW	449
	450	g_assert_cmpint(cyl, ==, 0);
	451	g_assert_cmpint(head, ==, 0);
	452	g_assert_cmpint(st0, ==, head << 2);
	453
	454	/* Seek to track 8 on head 1 and check with READ ID */
	455	head = 1;
	456	cyl = 8;
	457
	458	floppy_send(CMD_SEEK);
	459	floppy_send(head << 2 \| drive);
	460	g_assert(!get_irq(FLOPPY_IRQ));
	461	floppy_send(cyl);
	462	g_assert(get_irq(FLOPPY_IRQ));
	463	ack_irq(NULL);
	464
	465	floppy_send(CMD_READ_ID);
	466	g_assert(!get_irq(FLOPPY_IRQ));
	467	floppy_send(head << 2 \| drive);
	468
4964e18e KW	469	msr = inb(FLOPPY_BASE + reg_msr);
	470	if (!get_irq(FLOPPY_IRQ)) {
	471	assert_bit_set(msr, BUSY);
	472	assert_bit_clear(msr, RQM);
	473	}
	474
67f194bd KW	475	while (!get_irq(FLOPPY_IRQ)) {
	476	/* qemu involves a timer with READ ID... */
	477	clock_step(1000000000LL / 50);
	478	}
	479
4964e18e KW	480	msr = inb(FLOPPY_BASE + reg_msr);
	481	assert_bit_set(msr, BUSY \| RQM \| DIO);
	482
67f194bd KW	483	st0 = floppy_recv();
	484	floppy_recv();
	485	floppy_recv();
	486	cyl = floppy_recv();
	487	head = floppy_recv();
	488	floppy_recv();
4964e18e	489	g_assert(get_irq(FLOPPY_IRQ));
67f194bd	490	floppy_recv();
4964e18e	491	g_assert(!get_irq(FLOPPY_IRQ));
67f194bd KW	492
	493	g_assert_cmpint(cyl, ==, 8);
	494	g_assert_cmpint(head, ==, 1);
	495	g_assert_cmpint(st0, ==, head << 2);
	496	}
	497
5f8ae8e2 HP	498	static void test_read_no_dma_1(void)
	499	{
	500	uint8_t ret;
	501
	502	outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
	503	send_seek(0);
075f5532	504	ret = send_read_no_dma_command(1, 0x04);
5f8ae8e2 HP	505	g_assert(ret == 0);
	506	}
	507
	508	static void test_read_no_dma_18(void)
	509	{
	510	uint8_t ret;
	511
	512	outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
	513	send_seek(0);
075f5532	514	ret = send_read_no_dma_command(18, 0x04);
5f8ae8e2 HP	515	g_assert(ret == 0);
	516	}
	517
	518	static void test_read_no_dma_19(void)
	519	{
	520	uint8_t ret;
	521
	522	outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
	523	send_seek(0);
	524	ret = send_read_no_dma_command(19, 0x20);
	525	g_assert(ret == 0);
	526	}
	527
6f442fe8 HP	528	static void test_verify(void)
	529	{
	530	uint8_t ret;
	531
	532	ret = send_read_command(CMD_VERIFY);
	533	g_assert(ret == 0);
	534	}
	535
3359847e BS	536	/* success if no crash or abort */
	537	static void fuzz_registers(void)
	538	{
	539	unsigned int i;
	540
	541	for (i = 0; i < 1000; i++) {
	542	uint8_t reg, val;
	543
	544	reg = (uint8_t)g_test_rand_int_range(0, 8);
	545	val = (uint8_t)g_test_rand_int_range(0, 256);
	546
	547	outb(FLOPPY_BASE + reg, val);
	548	inb(FLOPPY_BASE + reg);
	549	}
	550	}
	551
93e9eb68 KW	552	int main(int argc, char **argv)
	553	{
	554	const char *arch = qtest_get_arch();
93e9eb68 KW	555	int fd;
	556	int ret;
	557
	558	/* Check architecture */
	559	if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
	560	g_test_message("Skipping test for non-x86\n");
	561	return 0;
	562	}
	563
	564	/* Create a temporary raw image */
	565	fd = mkstemp(test_image);
	566	g_assert(fd >= 0);
	567	ret = ftruncate(fd, TEST_IMAGE_SIZE);
	568	g_assert(ret == 0);
	569	close(fd);
	570
	571	/* Run the tests */
	572	g_test_init(&argc, &argv, NULL);
	573
b7fcff01	574	qtest_start(NULL);
93e9eb68	575	qtest_irq_intercept_in(global_qtest, "ioapic");
7cd33161 PH	576	qtest_add_func("/fdc/cmos", test_cmos);
7cd33161 PH	577	qtest_add_func("/fdc/no_media_on_start", test_no_media_on_start);
8b9ef60d	578	qtest_add_func("/fdc/read_without_media", test_read_without_media);
93e9eb68	579	qtest_add_func("/fdc/media_change", test_media_change);
b3ce604e	580	qtest_add_func("/fdc/sense_interrupt", test_sense_interrupt);
98272dbb	581	qtest_add_func("/fdc/relative_seek", test_relative_seek);
67f194bd	582	qtest_add_func("/fdc/read_id", test_read_id);
6f442fe8	583	qtest_add_func("/fdc/verify", test_verify);
44212dcc	584	qtest_add_func("/fdc/media_insert", test_media_insert);
5f8ae8e2 HP	585	qtest_add_func("/fdc/read_no_dma_1", test_read_no_dma_1);
	586	qtest_add_func("/fdc/read_no_dma_18", test_read_no_dma_18);
	587	qtest_add_func("/fdc/read_no_dma_19", test_read_no_dma_19);
3359847e	588	qtest_add_func("/fdc/fuzz-registers", fuzz_registers);
93e9eb68 KW	589
	590	ret = g_test_run();
	591
	592	/* Cleanup */
1d9358e6	593	qtest_end();
93e9eb68 KW	594	unlink(test_image);
	595
	596	return ret;
	597	}