[qemu.git] / hw / g364fb.c

/*
 * QEMU G364 framebuffer Emulator.
 *
 * Copyright (c) 2007-2008 Hervé Poussineau
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#include "hw.h"
#include "mips.h"
#include "console.h"
#include "pixel_ops.h"

//#define DEBUG_G364

typedef struct G364State {
    unsigned int vram_size;
    uint8_t *vram_buffer;
    uint32_t ctla;
    uint8_t palette[256][3];
    /* display refresh support */
    DisplayState *ds;
    QEMUConsole *console;
    int graphic_mode;
    uint32_t scr_width, scr_height; /* in pixels */
} G364State;

/*
 * graphic modes
 */
#define BPP 8
#define PIXEL_WIDTH 8
#include "g364fb_template.h"
#undef BPP
#undef PIXEL_WIDTH

#define BPP 15
#define PIXEL_WIDTH 16
#include "g364fb_template.h"
#undef BPP
#undef PIXEL_WIDTH

#define BPP 16
#define PIXEL_WIDTH 16
#include "g364fb_template.h"
#undef BPP
#undef PIXEL_WIDTH

#define BPP 32
#define PIXEL_WIDTH 32
#include "g364fb_template.h"
#undef BPP
#undef PIXEL_WIDTH

#define REG_DISPLAYX 0x0918
#define REG_DISPLAYY 0x0940

#define CTLA_FORCE_BLANK 0x400

static void g364fb_draw_graphic(G364State *s, int full_update)
{
    switch (ds_get_bits_per_pixel(s->ds)) {
        case 8:
            g364fb_draw_graphic8(s, full_update);
            break;
        case 15:
            g364fb_draw_graphic15(s, full_update);
            break;
        case 16:
            g364fb_draw_graphic16(s, full_update);
            break;
        case 32:
            g364fb_draw_graphic32(s, full_update);
            break;
        default:
            printf("g364fb: unknown depth %d\n", ds_get_bits_per_pixel(s->ds));
            return;
    }

    dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
}

static void g364fb_draw_blank(G364State *s, int full_update)
{
    int i, w;
    uint8_t *d;

    if (!full_update)
        return;

    w = s->scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
    d = ds_get_data(s->ds);
    for(i = 0; i < s->scr_height; i++) {
        memset(d, 0, w);
        d += ds_get_linesize(s->ds);
    }

    dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
}

#define GMODE_GRAPH 0
#define GMODE_BLANK 1

static void g364fb_update_display(void *opaque)
{
    G364State *s = opaque;
    int full_update, graphic_mode;

    if (s->scr_width == 0 || s->scr_height == 0)
        return;

    if (s->ctla & CTLA_FORCE_BLANK)
        graphic_mode = GMODE_BLANK;
    else
        graphic_mode = GMODE_GRAPH;
    full_update = 0;
    if (graphic_mode != s->graphic_mode) {
        s->graphic_mode = graphic_mode;
        full_update = 1;
    }
    if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
        qemu_console_resize(s->console, s->scr_width, s->scr_height);
        full_update = 1;
    }
    switch(graphic_mode) {
        case GMODE_GRAPH:
            g364fb_draw_graphic(s, full_update);
            break;
        case GMODE_BLANK:
        default:
            g364fb_draw_blank(s, full_update);
            break;
    }
}

/* force a full display refresh */
static void g364fb_invalidate_display(void *opaque)
{
    G364State *s = opaque;
    s->graphic_mode = -1; /* force full update */
}

static void g364fb_reset(void *opaque)
{
    G364State *s = opaque;

    memset(s->palette, 0, sizeof(s->palette));
    s->scr_width = s->scr_height = 0;
    memset(s->vram_buffer, 0, s->vram_size);
    s->graphic_mode = -1; /* force full update */
}

static void g364fb_screen_dump(void *opaque, const char *filename)
{
    G364State *s = opaque;
    int y, x;
    uint8_t index;
    uint8_t *data_buffer;
    FILE *f;

    f = fopen(filename, "wb");
    if (!f)
        return;

    data_buffer = s->vram_buffer;
    fprintf(f, "P6\n%d %d\n%d\n",
        s->scr_width, s->scr_height, 255);
    for(y = 0; y < s->scr_height; y++)
        for(x = 0; x < s->scr_width; x++, data_buffer++) {
            index = *data_buffer;
            fputc(s->palette[index][0], f);
            fputc(s->palette[index][1], f);
            fputc(s->palette[index][2], f);
        }
    fclose(f);
}

/* called for accesses to io ports */
static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
{
    //G364State *s = opaque;
    uint32_t val;

    addr &= 0xffff;

    switch (addr) {
        default:
#ifdef DEBUG_G364
            printf("g364fb/ctrl: invalid read at [" TARGET_FMT_lx "]\n", addr);
#endif
            val = 0;
            break;
    }

#ifdef DEBUG_G364
    printf("g364fb/ctrl: read 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
#endif

    return val;
}

static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
{
    uint32_t v;
    v = g364fb_ctrl_readb(opaque, addr);
    v |= g364fb_ctrl_readb(opaque, addr + 1) << 8;
    return v;
}

static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
{
    uint32_t v;
    v = g364fb_ctrl_readb(opaque, addr);
    v |= g364fb_ctrl_readb(opaque, addr + 1) << 8;
    v |= g364fb_ctrl_readb(opaque, addr + 2) << 16;
    v |= g364fb_ctrl_readb(opaque, addr + 3) << 24;
    return v;
}

static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    G364State *s = opaque;

    addr &= 0xffff;

#ifdef DEBUG_G364
    printf("g364fb/ctrl: write 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
#endif

    if (addr < 0x0800) {
        /* color palette */
        int idx = addr >> 3;
        int c = addr & 7;
        if (c < 3)
            s->palette[idx][c] = (uint8_t)val;
    } else {
        switch (addr) {
            case REG_DISPLAYX:
                s->scr_width = (s->scr_width & 0xfffffc03) | (val << 2);
                break;
            case REG_DISPLAYX + 1:
                s->scr_width = (s->scr_width & 0xfffc03ff) | (val << 10);
                break;
            case REG_DISPLAYY:
                s->scr_height = (s->scr_height & 0xffffff80) | (val >> 1);
                break;
            case REG_DISPLAYY + 1:
                s->scr_height = (s->scr_height & 0xffff801f) | (val << 7);
                break;
            default:
#ifdef DEBUG_G364
                printf("g364fb/ctrl: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
#endif
                break;
        }
    }
    s->graphic_mode = -1; /* force full update */
}

static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    g364fb_ctrl_writeb(opaque, addr, val & 0xff);
    g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}

static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    g364fb_ctrl_writeb(opaque, addr, val & 0xff);
    g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
    g364fb_ctrl_writeb(opaque, addr + 2, (val >> 16) & 0xff);
    g364fb_ctrl_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}

static CPUReadMemoryFunc *g364fb_ctrl_read[3] = {
    g364fb_ctrl_readb,
    g364fb_ctrl_readw,
    g364fb_ctrl_readl,
};

static CPUWriteMemoryFunc *g364fb_ctrl_write[3] = {
    g364fb_ctrl_writeb,
    g364fb_ctrl_writew,
    g364fb_ctrl_writel,
};

/* called for accesses to video ram */
static uint32_t g364fb_mem_readb(void *opaque, target_phys_addr_t addr)
{
    G364State *s = opaque;

    return s->vram_buffer[addr];
}

static uint32_t g364fb_mem_readw(void *opaque, target_phys_addr_t addr)
{
    uint32_t v;
    v = g364fb_mem_readb(opaque, addr);
    v |= g364fb_mem_readb(opaque, addr + 1) << 8;
    return v;
}

static uint32_t g364fb_mem_readl(void *opaque, target_phys_addr_t addr)
{
    uint32_t v;
    v = g364fb_mem_readb(opaque, addr);
    v |= g364fb_mem_readb(opaque, addr + 1) << 8;
    v |= g364fb_mem_readb(opaque, addr + 2) << 16;
    v |= g364fb_mem_readb(opaque, addr + 3) << 24;
    return v;
}

static void g364fb_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    G364State *s = opaque;

    s->vram_buffer[addr] = val;
}

static void g364fb_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    g364fb_mem_writeb(opaque, addr, val & 0xff);
    g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}

static void g364fb_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    g364fb_mem_writeb(opaque, addr, val & 0xff);
    g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
    g364fb_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
    g364fb_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}

static CPUReadMemoryFunc *g364fb_mem_read[3] = {
    g364fb_mem_readb,
    g364fb_mem_readw,
    g364fb_mem_readl,
};

static CPUWriteMemoryFunc *g364fb_mem_write[3] = {
    g364fb_mem_writeb,
    g364fb_mem_writew,
    g364fb_mem_writel,
};

int g364fb_mm_init(DisplayState *ds,
                   int vram_size, int it_shift,
                   target_phys_addr_t vram_base, target_phys_addr_t ctrl_base)
{
    G364State *s;
    int io_vram, io_ctrl;

    s = qemu_mallocz(sizeof(G364State));
    if (!s)
        return -1;

    s->vram_size = vram_size;
    s->vram_buffer = qemu_mallocz(s->vram_size);

    qemu_register_reset(g364fb_reset, s);
    g364fb_reset(s);

    s->ds = ds;

    s->console = graphic_console_init(ds, g364fb_update_display,
                                      g364fb_invalidate_display,
                                      g364fb_screen_dump, NULL, s);

    io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);
    cpu_register_physical_memory(vram_base, vram_size, io_vram);

    io_ctrl = cpu_register_io_memory(0, g364fb_ctrl_read, g364fb_ctrl_write, s);
    cpu_register_physical_memory(ctrl_base, 0x10000, io_ctrl);

    return 0;
}
Commit	Line	Data
1fc3d392 AJ	1	/*
	2	* QEMU G364 framebuffer Emulator.
	3	*
	4	* Copyright (c) 2007-2008 Hervé Poussineau
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
fad6cb1a AJ	16	* You should have received a copy of the GNU General Public License along
	17	* with this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
1fc3d392 AJ	19	*/
	20
	21	#include "hw.h"
cd5158ea	22	#include "mips.h"
1fc3d392 AJ	23	#include "console.h"
	24	#include "pixel_ops.h"
	25
	26	//#define DEBUG_G364
	27
	28	typedef struct G364State {
1fc3d392 AJ	29	unsigned int vram_size;
	30	uint8_t *vram_buffer;
	31	uint32_t ctla;
	32	uint8_t palette[256][3];
	33	/* display refresh support */
	34	DisplayState *ds;
c60e08d9	35	QEMUConsole *console;
1fc3d392 AJ	36	int graphic_mode;
1fc3d392 AJ	37	uint32_t scr_width, scr_height; /* in pixels */
1fc3d392 AJ	38	} G364State;
	39
	40	/*
	41	* graphic modes
	42	*/
	43	#define BPP 8
	44	#define PIXEL_WIDTH 8
	45	#include "g364fb_template.h"
	46	#undef BPP
	47	#undef PIXEL_WIDTH
	48
	49	#define BPP 15
	50	#define PIXEL_WIDTH 16
	51	#include "g364fb_template.h"
	52	#undef BPP
	53	#undef PIXEL_WIDTH
	54
	55	#define BPP 16
	56	#define PIXEL_WIDTH 16
	57	#include "g364fb_template.h"
	58	#undef BPP
	59	#undef PIXEL_WIDTH
	60
	61	#define BPP 32
	62	#define PIXEL_WIDTH 32
	63	#include "g364fb_template.h"
	64	#undef BPP
	65	#undef PIXEL_WIDTH
	66
	67	#define REG_DISPLAYX 0x0918
	68	#define REG_DISPLAYY 0x0940
	69
	70	#define CTLA_FORCE_BLANK 0x400
	71
	72	static void g364fb_draw_graphic(G364State *s, int full_update)
	73	{
0e1f5a0c	74	switch (ds_get_bits_per_pixel(s->ds)) {
1fc3d392 AJ	75	case 8:
	76	g364fb_draw_graphic8(s, full_update);
	77	break;
	78	case 15:
	79	g364fb_draw_graphic15(s, full_update);
	80	break;
	81	case 16:
	82	g364fb_draw_graphic16(s, full_update);
	83	break;
	84	case 32:
	85	g364fb_draw_graphic32(s, full_update);
	86	break;
	87	default:
0e1f5a0c	88	printf("g364fb: unknown depth %d\n", ds_get_bits_per_pixel(s->ds));
1fc3d392 AJ	89	return;
	90	}
	91
221bb2d5	92	dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
1fc3d392 AJ	93	}
	94
	95	static void g364fb_draw_blank(G364State *s, int full_update)
	96	{
	97	int i, w;
	98	uint8_t *d;
	99
	100	if (!full_update)
	101	return;
1fc3d392	102
0e1f5a0c AL	103	w = s->scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
0e1f5a0c AL	104	d = ds_get_data(s->ds);
221bb2d5	105	for(i = 0; i < s->scr_height; i++) {
1fc3d392	106	memset(d, 0, w);
0e1f5a0c	107	d += ds_get_linesize(s->ds);
1fc3d392	108	}
221bb2d5 AJ	109
221bb2d5 AJ	110	dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
1fc3d392 AJ	111	}
	112
	113	#define GMODE_GRAPH 0
	114	#define GMODE_BLANK 1
	115
	116	static void g364fb_update_display(void *opaque)
	117	{
	118	G364State *s = opaque;
	119	int full_update, graphic_mode;
	120
221bb2d5 AJ	121	if (s->scr_width == 0 \|\| s->scr_height == 0)
	122	return;
	123
1fc3d392 AJ	124	if (s->ctla & CTLA_FORCE_BLANK)
	125	graphic_mode = GMODE_BLANK;
	126	else
	127	graphic_mode = GMODE_GRAPH;
	128	full_update = 0;
	129	if (graphic_mode != s->graphic_mode) {
	130	s->graphic_mode = graphic_mode;
	131	full_update = 1;
	132	}
0e1f5a0c	133	if (s->scr_width != ds_get_width(s->ds) \|\| s->scr_height != ds_get_height(s->ds)) {
221bb2d5 AJ	134	qemu_console_resize(s->console, s->scr_width, s->scr_height);
	135	full_update = 1;
	136	}
1fc3d392 AJ	137	switch(graphic_mode) {
	138	case GMODE_GRAPH:
	139	g364fb_draw_graphic(s, full_update);
	140	break;
	141	case GMODE_BLANK:
	142	default:
	143	g364fb_draw_blank(s, full_update);
	144	break;
	145	}
	146	}
	147
	148	/* force a full display refresh */
	149	static void g364fb_invalidate_display(void *opaque)
	150	{
	151	G364State *s = opaque;
	152	s->graphic_mode = -1; /* force full update */
	153	}
	154
	155	static void g364fb_reset(void *opaque)
	156	{
	157	G364State *s = opaque;
	158
	159	memset(s->palette, 0, sizeof(s->palette));
	160	s->scr_width = s->scr_height = 0;
1fc3d392 AJ	161	memset(s->vram_buffer, 0, s->vram_size);
	162	s->graphic_mode = -1; /* force full update */
	163	}
	164
	165	static void g364fb_screen_dump(void opaque, const char filename)
	166	{
	167	G364State *s = opaque;
	168	int y, x;
	169	uint8_t index;
	170	uint8_t *data_buffer;
	171	FILE *f;
	172
	173	f = fopen(filename, "wb");
	174	if (!f)
	175	return;
	176
	177	data_buffer = s->vram_buffer;
	178	fprintf(f, "P6\n%d %d\n%d\n",
	179	s->scr_width, s->scr_height, 255);
	180	for(y = 0; y < s->scr_height; y++)
	181	for(x = 0; x < s->scr_width; x++, data_buffer++) {
	182	index = *data_buffer;
	183	fputc(s->palette[index][0], f);
	184	fputc(s->palette[index][1], f);
	185	fputc(s->palette[index][2], f);
	186	}
	187	fclose(f);
	188	}
	189
	190	/* called for accesses to io ports */
	191	static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
	192	{
	193	//G364State *s = opaque;
	194	uint32_t val;
	195
	196	addr &= 0xffff;
	197
	198	switch (addr) {
	199	default:
	200	#ifdef DEBUG_G364
	201	printf("g364fb/ctrl: invalid read at [" TARGET_FMT_lx "]\n", addr);
	202	#endif
	203	val = 0;
	204	break;
	205	}
	206
	207	#ifdef DEBUG_G364
	208	printf("g364fb/ctrl: read 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
	209	#endif
	210
	211	return val;
	212	}
	213
	214	static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
	215	{
	216	uint32_t v;
	217	v = g364fb_ctrl_readb(opaque, addr);
	218	v \|= g364fb_ctrl_readb(opaque, addr + 1) << 8;
	219	return v;
	220	}
	221
	222	static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
	223	{
	224	uint32_t v;
225	v = g364fb_ctrl_readb(opaque, addr);
226	v \|= g364fb_ctrl_readb(opaque, addr + 1) << 8;
227	v \|= g364fb_ctrl_readb(opaque, addr + 2) << 16;
228	v \|= g364fb_ctrl_readb(opaque, addr + 3) << 24;
229	return v;
230	}
231
232	static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
233	{
234	G364State *s = opaque;
235
236	addr &= 0xffff;
237
238	#ifdef DEBUG_G364
239	printf("g364fb/ctrl: write 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
240	#endif
241
242	if (addr < 0x0800) {
243	/* color palette */
244	int idx = addr >> 3;
245	int c = addr & 7;
246	if (c < 3)
247	s->palette[idx][c] = (uint8_t)val;
248	} else {
249	switch (addr) {
250	case REG_DISPLAYX:
251	s->scr_width = (s->scr_width & 0xfffffc03) \| (val << 2);
252	break;
253	case REG_DISPLAYX + 1:
254	s->scr_width = (s->scr_width & 0xfffc03ff) \| (val << 10);
255	break;
256	case REG_DISPLAYY:
257	s->scr_height = (s->scr_height & 0xffffff80) \| (val >> 1);
258	break;
259	case REG_DISPLAYY + 1:
260	s->scr_height = (s->scr_height & 0xffff801f) \| (val << 7);
261	break;
262	default:
263	#ifdef DEBUG_G364
264	printf("g364fb/ctrl: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
265	#endif
266	break;
267	}
268	}
c60e08d9	269	s->graphic_mode = -1; /* force full update */
1fc3d392 AJ	270	}
	271
	272	static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
	273	{
	274	g364fb_ctrl_writeb(opaque, addr, val & 0xff);
	275	g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
	276	}
	277
	278	static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	279	{
	280	g364fb_ctrl_writeb(opaque, addr, val & 0xff);
	281	g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
	282	g364fb_ctrl_writeb(opaque, addr + 2, (val >> 16) & 0xff);
	283	g364fb_ctrl_writeb(opaque, addr + 3, (val >> 24) & 0xff);
	284	}
	285
	286	static CPUReadMemoryFunc *g364fb_ctrl_read[3] = {
	287	g364fb_ctrl_readb,
	288	g364fb_ctrl_readw,
	289	g364fb_ctrl_readl,
	290	};
	291
	292	static CPUWriteMemoryFunc *g364fb_ctrl_write[3] = {
	293	g364fb_ctrl_writeb,
	294	g364fb_ctrl_writew,
	295	g364fb_ctrl_writel,
	296	};
	297
	298	/* called for accesses to video ram */
	299	static uint32_t g364fb_mem_readb(void *opaque, target_phys_addr_t addr)
	300	{
	301	G364State *s = opaque;
1fc3d392	302
8da3ff18	303	return s->vram_buffer[addr];
1fc3d392 AJ	304	}
	305
	306	static uint32_t g364fb_mem_readw(void *opaque, target_phys_addr_t addr)
	307	{
	308	uint32_t v;
	309	v = g364fb_mem_readb(opaque, addr);
	310	v \|= g364fb_mem_readb(opaque, addr + 1) << 8;
	311	return v;
	312	}
	313
	314	static uint32_t g364fb_mem_readl(void *opaque, target_phys_addr_t addr)
	315	{
	316	uint32_t v;
	317	v = g364fb_mem_readb(opaque, addr);
	318	v \|= g364fb_mem_readb(opaque, addr + 1) << 8;
	319	v \|= g364fb_mem_readb(opaque, addr + 2) << 16;
	320	v \|= g364fb_mem_readb(opaque, addr + 3) << 24;
	321	return v;
	322	}
	323
	324	static void g364fb_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
	325	{
	326	G364State *s = opaque;
1fc3d392	327
8da3ff18	328	s->vram_buffer[addr] = val;
1fc3d392 AJ	329	}
	330
	331	static void g364fb_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
	332	{
	333	g364fb_mem_writeb(opaque, addr, val & 0xff);
	334	g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
	335	}
	336
	337	static void g364fb_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	338	{
	339	g364fb_mem_writeb(opaque, addr, val & 0xff);
	340	g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
	341	g364fb_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
	342	g364fb_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
	343	}
	344
	345	static CPUReadMemoryFunc *g364fb_mem_read[3] = {
	346	g364fb_mem_readb,
	347	g364fb_mem_readw,
	348	g364fb_mem_readl,
	349	};
	350
	351	static CPUWriteMemoryFunc *g364fb_mem_write[3] = {
	352	g364fb_mem_writeb,
	353	g364fb_mem_writew,
	354	g364fb_mem_writel,
	355	};
	356
	357	int g364fb_mm_init(DisplayState *ds,
	358	int vram_size, int it_shift,
	359	target_phys_addr_t vram_base, target_phys_addr_t ctrl_base)
	360	{
	361	G364State *s;
	362	int io_vram, io_ctrl;
	363
	364	s = qemu_mallocz(sizeof(G364State));
	365	if (!s)
	366	return -1;
	367
	368	s->vram_size = vram_size;
	369	s->vram_buffer = qemu_mallocz(s->vram_size);
	370
	371	qemu_register_reset(g364fb_reset, s);
	372	g364fb_reset(s);
	373
	374	s->ds = ds;
1fc3d392	375
c60e08d9 PB	376	s->console = graphic_console_init(ds, g364fb_update_display,
	377	g364fb_invalidate_display,
	378	g364fb_screen_dump, NULL, s);
1fc3d392 AJ	379
1fc3d392 AJ	380	io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);
8da3ff18	381	cpu_register_physical_memory(vram_base, vram_size, io_vram);
1fc3d392 AJ	382
	383	io_ctrl = cpu_register_io_memory(0, g364fb_ctrl_read, g364fb_ctrl_write, s);
	384	cpu_register_physical_memory(ctrl_base, 0x10000, io_ctrl);
	385
	386	return 0;
	387	}