[qemu.git] / docs / specs / pci-testdev.txt

pci-test is a device used for testing low level IO

device implements up to two BARs: BAR0 and BAR1.
Each BAR can be memory or IO. Guests must detect
BAR type and act accordingly.

Each BAR size is up to 4K bytes.
Each BAR starts with the following header:

typedef struct PCITestDevHdr {
    uint8_t test;  <- write-only, starts a given test number
    uint8_t width_type; <- read-only, type and width of access for a given test.
                           1,2,4 for byte,word or long write.
                           any other value if test not supported on this BAR
    uint8_t pad0[2];
    uint32_t offset; <- read-only, offset in this BAR for a given test
    uint32_t data;    <- read-only, data to use for a given test
    uint32_t count;  <- for debugging. number of writes detected.
    uint8_t name[]; <- for debugging. 0-terminated ASCII string.
} PCITestDevHdr;

All registers are little endian.

device is expected to always implement tests 0 to N on each BAR, and to add new
tests with higher numbers.  In this way a guest can scan test numbers until it
detects an access type that it does not support on this BAR, then stop.
Commit	Line	Data
22773d60 MT	1	pci-test is a device used for testing low level IO
	2
	3	device implements up to two BARs: BAR0 and BAR1.
	4	Each BAR can be memory or IO. Guests must detect
	5	BAR type and act accordingly.
	6
	7	Each BAR size is up to 4K bytes.
	8	Each BAR starts with the following header:
	9
	10	typedef struct PCITestDevHdr {
	11	uint8_t test; <- write-only, starts a given test number
	12	uint8_t width_type; <- read-only, type and width of access for a given test.
	13	1,2,4 for byte,word or long write.
	14	any other value if test not supported on this BAR
	15	uint8_t pad0[2];
	16	uint32_t offset; <- read-only, offset in this BAR for a given test
	17	uint32_t data; <- read-only, data to use for a given test
	18	uint32_t count; <- for debugging. number of writes detected.
	19	uint8_t name[]; <- for debugging. 0-terminated ASCII string.
	20	} PCITestDevHdr;
	21
	22	All registers are little endian.
	23
	24	device is expected to always implement tests 0 to N on each BAR, and to add new
	25	tests with higher numbers. In this way a guest can scan test numbers until it
	26	detects an access type that it does not support on this BAR, then stop.