[qemu.git] / hw / slavio_intctl.c

/*
 * QEMU Sparc SLAVIO interrupt controller emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sun4m.h"
#include "monitor.h"
#include "sysbus.h"

//#define DEBUG_IRQ_COUNT
//#define DEBUG_IRQ

#ifdef DEBUG_IRQ
#define DPRINTF(fmt, ...)                                       \
    do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif

/*
 * Registers of interrupt controller in sun4m.
 *
 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * There is a system master controller and one for each cpu.
 *
 */

#define MAX_CPUS 16
#define MAX_PILS 16

struct SLAVIO_INTCTLState;

typedef struct SLAVIO_CPUINTCTLState {
    uint32_t intreg_pending;
    struct SLAVIO_INTCTLState *master;
    uint32_t cpu;
    uint32_t irl_out;
} SLAVIO_CPUINTCTLState;

typedef struct SLAVIO_INTCTLState {
    SysBusDevice busdev;
    uint32_t intregm_pending;
    uint32_t intregm_disabled;
    uint32_t target_cpu;
#ifdef DEBUG_IRQ_COUNT
    uint64_t irq_count[32];
#endif
    qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
    SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
} SLAVIO_INTCTLState;

#define INTCTL_MAXADDR 0xf
#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
#define INTCTLM_SIZE 0x14
#define MASTER_IRQ_MASK ~0x0fa2007f
#define MASTER_DISABLE 0x80000000
#define CPU_SOFTIRQ_MASK 0xfffe0000
#define CPU_IRQ_INT15_IN (1 << 15)
#define CPU_IRQ_TIMER_IN (1 << 14)

static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);

// per-cpu interrupt controller
static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_CPUINTCTLState *s = opaque;
    uint32_t saddr, ret;

    saddr = addr >> 2;
    switch (saddr) {
    case 0:
        ret = s->intreg_pending;
        break;
    default:
        ret = 0;
        break;
    }
    DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);

    return ret;
}

static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
                                     uint32_t val)
{
    SLAVIO_CPUINTCTLState *s = opaque;
    uint32_t saddr;

    saddr = addr >> 2;
    DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
    switch (saddr) {
    case 1: // clear pending softints
        val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN;
        s->intreg_pending &= ~val;
        slavio_check_interrupts(s->master, 1);
        DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
                s->intreg_pending);
        break;
    case 2: // set softint
        val &= CPU_SOFTIRQ_MASK;
        s->intreg_pending |= val;
        slavio_check_interrupts(s->master, 1);
        DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
                s->intreg_pending);
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc * const slavio_intctl_mem_read[3] = {
    NULL,
    NULL,
    slavio_intctl_mem_readl,
};

static CPUWriteMemoryFunc * const slavio_intctl_mem_write[3] = {
    NULL,
    NULL,
    slavio_intctl_mem_writel,
};

// master system interrupt controller
static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr, ret;

    saddr = addr >> 2;
    switch (saddr) {
    case 0:
        ret = s->intregm_pending & ~MASTER_DISABLE;
        break;
    case 1:
        ret = s->intregm_disabled & MASTER_IRQ_MASK;
        break;
    case 4:
        ret = s->target_cpu;
        break;
    default:
        ret = 0;
        break;
    }
    DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);

    return ret;
}

static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
                                      uint32_t val)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;

    saddr = addr >> 2;
    DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
    switch (saddr) {
    case 2: // clear (enable)
        // Force clear unused bits
        val &= MASTER_IRQ_MASK;
        s->intregm_disabled &= ~val;
        DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
                s->intregm_disabled);
        slavio_check_interrupts(s, 1);
        break;
    case 3: // set (disable, clear pending)
        // Force clear unused bits
        val &= MASTER_IRQ_MASK;
        s->intregm_disabled |= val;
        s->intregm_pending &= ~val;
        slavio_check_interrupts(s, 1);
        DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
                s->intregm_disabled);
        break;
    case 4:
        s->target_cpu = val & (MAX_CPUS - 1);
        slavio_check_interrupts(s, 1);
        DPRINTF("Set master irq cpu %d\n", s->target_cpu);
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc * const slavio_intctlm_mem_read[3] = {
    NULL,
    NULL,
    slavio_intctlm_mem_readl,
};

static CPUWriteMemoryFunc * const slavio_intctlm_mem_write[3] = {
    NULL,
    NULL,
    slavio_intctlm_mem_writel,
};

void slavio_pic_info(Monitor *mon, DeviceState *dev)
{
    SysBusDevice *sd;
    SLAVIO_INTCTLState *s;
    int i;

    sd = sysbus_from_qdev(dev);
    s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
    for (i = 0; i < MAX_CPUS; i++) {
        monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
                       s->slaves[i].intreg_pending);
    }
    monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
                   s->intregm_pending, s->intregm_disabled);
}

void slavio_irq_info(Monitor *mon, DeviceState *dev)
{
#ifndef DEBUG_IRQ_COUNT
    monitor_printf(mon, "irq statistic code not compiled.\n");
#else
    SysBusDevice *sd;
    SLAVIO_INTCTLState *s;
    int i;
    int64_t count;

    sd = sysbus_from_qdev(dev);
    s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
    monitor_printf(mon, "IRQ statistics:\n");
    for (i = 0; i < 32; i++) {
        count = s->irq_count[i];
        if (count > 0)
            monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
    }
#endif
}

static const uint32_t intbit_to_level[] = {
    2, 3, 5, 7, 9, 11, 13, 2,   3, 5, 7, 9, 11, 13, 12, 12,
    6, 13, 4, 10, 8, 9, 11, 0,  0, 0, 0, 15, 15, 15, 15, 0,
};

static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
{
    uint32_t pending = s->intregm_pending, pil_pending;
    unsigned int i, j;

    pending &= ~s->intregm_disabled;

    DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
    for (i = 0; i < MAX_CPUS; i++) {
        pil_pending = 0;

        /* If we are the current interrupt target, get hard interrupts */
        if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
            (i == s->target_cpu)) {
            for (j = 0; j < 32; j++) {
                if ((pending & (1 << j)) && intbit_to_level[j]) {
                    pil_pending |= 1 << intbit_to_level[j];
                }
            }
        }

        /* Calculate current pending hard interrupts for display */
        s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN |
            CPU_IRQ_TIMER_IN;
        if (i == s->target_cpu) {
            for (j = 0; j < 32; j++) {
                if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) {
                    s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
                }
            }
        }

        /* Level 15 and CPU timer interrupts are not maskable */
        pil_pending |= s->slaves[i].intreg_pending &
            (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);

        /* Add soft interrupts */
        pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;

        if (set_irqs) {
            for (j = MAX_PILS; j > 0; j--) {
                if (pil_pending & (1 << j)) {
                    if (!(s->slaves[i].irl_out & (1 << j))) {
                        qemu_irq_raise(s->cpu_irqs[i][j]);
                    }
                } else {
                    if (s->slaves[i].irl_out & (1 << j)) {
                        qemu_irq_lower(s->cpu_irqs[i][j]);
                    }
                }
            }
        }
        s->slaves[i].irl_out = pil_pending;
    }
}

/*
 * "irq" here is the bit number in the system interrupt register to
 * separate serial and keyboard interrupts sharing a level.
 */
static void slavio_set_irq(void *opaque, int irq, int level)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t mask = 1 << irq;
    uint32_t pil = intbit_to_level[irq];
    unsigned int i;

    DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
            level);
    if (pil > 0) {
        if (level) {
#ifdef DEBUG_IRQ_COUNT
            s->irq_count[pil]++;
#endif
            s->intregm_pending |= mask;
            if (pil == 15) {
                for (i = 0; i < MAX_CPUS; i++) {
                    s->slaves[i].intreg_pending |= 1 << pil;
                }
            }
        } else {
            s->intregm_pending &= ~mask;
            if (pil == 15) {
                for (i = 0; i < MAX_CPUS; i++) {
                    s->slaves[i].intreg_pending &= ~(1 << pil);
                }
            }
        }
        slavio_check_interrupts(s, 1);
    }
}

static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
{
    SLAVIO_INTCTLState *s = opaque;

    DPRINTF("Set cpu %d local timer level %d\n", cpu, level);

    if (level) {
        s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN;
    } else {
        s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN;
    }

    slavio_check_interrupts(s, 1);
}

static void slavio_set_irq_all(void *opaque, int irq, int level)
{
    if (irq < 32) {
        slavio_set_irq(opaque, irq, level);
    } else {
        slavio_set_timer_irq_cpu(opaque, irq - 32, level);
    }
}

static int vmstate_intctl_post_load(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;

    slavio_check_interrupts(s, 0);
    return 0;
}

static const VMStateDescription vmstate_intctl_cpu = {
    .name ="slavio_intctl_cpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_intctl = {
    .name ="slavio_intctl",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = vmstate_intctl_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1,
                             vmstate_intctl_cpu, SLAVIO_CPUINTCTLState),
        VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState),
        VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState),
        VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState),
        VMSTATE_END_OF_LIST()
    }
};

static void slavio_intctl_reset(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    for (i = 0; i < MAX_CPUS; i++) {
        s->slaves[i].intreg_pending = 0;
        s->slaves[i].irl_out = 0;
    }
    s->intregm_disabled = ~MASTER_IRQ_MASK;
    s->intregm_pending = 0;
    s->target_cpu = 0;
    slavio_check_interrupts(s, 0);
}

static int slavio_intctl_init1(SysBusDevice *dev)
{
    SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
    int io_memory;
    unsigned int i, j;

    qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
    io_memory = cpu_register_io_memory(slavio_intctlm_mem_read,
                                       slavio_intctlm_mem_write, s);
    sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory);

    for (i = 0; i < MAX_CPUS; i++) {
        for (j = 0; j < MAX_PILS; j++) {
            sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
        }
        io_memory = cpu_register_io_memory(slavio_intctl_mem_read,
                                           slavio_intctl_mem_write,
                                           &s->slaves[i]);
        sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
        s->slaves[i].cpu = i;
        s->slaves[i].master = s;
    }
    vmstate_register(-1, &vmstate_intctl, s);
    qemu_register_reset(slavio_intctl_reset, s);
    slavio_intctl_reset(s);
    return 0;
}

static SysBusDeviceInfo slavio_intctl_info = {
    .init = slavio_intctl_init1,
    .qdev.name  = "slavio_intctl",
    .qdev.size  = sizeof(SLAVIO_INTCTLState),
};

static void slavio_intctl_register_devices(void)
{
    sysbus_register_withprop(&slavio_intctl_info);
}

device_init(slavio_intctl_register_devices)
Commit	Line	Data
e80cfcfc FB	1	/*
e80cfcfc FB	2	* QEMU Sparc SLAVIO interrupt controller emulation
5fafdf24	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
e80cfcfc FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
a1961a4b	24
87ecb68b	25	#include "sun4m.h"
376253ec	26	#include "monitor.h"
a1961a4b	27	#include "sysbus.h"
87ecb68b	28
e80cfcfc	29	//#define DEBUG_IRQ_COUNT
66321a11 FB	30	//#define DEBUG_IRQ
	31
	32	#ifdef DEBUG_IRQ
001faf32 BS	33	#define DPRINTF(fmt, ...) \
001faf32 BS	34	do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
66321a11	35	#else
001faf32	36	#define DPRINTF(fmt, ...)
66321a11	37	#endif
e80cfcfc FB	38
	39	/*
	40	* Registers of interrupt controller in sun4m.
	41	*
	42	* This is the interrupt controller part of chip STP2001 (Slave I/O), also
	43	* produced as NCR89C105. See
	44	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	45	*
	46	* There is a system master controller and one for each cpu.
5fafdf24	47	*
e80cfcfc FB	48	*/
	49
	50	#define MAX_CPUS 16
b3a23197	51	#define MAX_PILS 16
e80cfcfc	52
a1961a4b BS	53	struct SLAVIO_INTCTLState;
	54
	55	typedef struct SLAVIO_CPUINTCTLState {
	56	uint32_t intreg_pending;
	57	struct SLAVIO_INTCTLState *master;
	58	uint32_t cpu;
462eda24	59	uint32_t irl_out;
a1961a4b	60	} SLAVIO_CPUINTCTLState;
a8f48dcc	61
e80cfcfc	62	typedef struct SLAVIO_INTCTLState {
a1961a4b	63	SysBusDevice busdev;
e80cfcfc FB	64	uint32_t intregm_pending;
	65	uint32_t intregm_disabled;
	66	uint32_t target_cpu;
	67	#ifdef DEBUG_IRQ_COUNT
	68	uint64_t irq_count[32];
	69	#endif
a1961a4b	70	qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
a1961a4b	71	SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
e80cfcfc FB	72	} SLAVIO_INTCTLState;
	73
	74	#define INTCTL_MAXADDR 0xf
5aca8c3b	75	#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
a8f48dcc	76	#define INTCTLM_SIZE 0x14
80be36b8	77	#define MASTER_IRQ_MASK ~0x0fa2007f
9a87ce9b	78	#define MASTER_DISABLE 0x80000000
6341fdcb	79	#define CPU_SOFTIRQ_MASK 0xfffe0000
462eda24 BS	80	#define CPU_IRQ_INT15_IN (1 << 15)
462eda24 BS	81	#define CPU_IRQ_TIMER_IN (1 << 14)
9a87ce9b	82
0d0a7e69	83	static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
e80cfcfc FB	84
	85	// per-cpu interrupt controller
	86	static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
	87	{
a8f48dcc	88	SLAVIO_CPUINTCTLState *s = opaque;
dd4131b3	89	uint32_t saddr, ret;
e80cfcfc	90
a8f48dcc	91	saddr = addr >> 2;
e80cfcfc FB	92	switch (saddr) {
e80cfcfc FB	93	case 0:
a8f48dcc	94	ret = s->intreg_pending;
dd4131b3	95	break;
e80cfcfc	96	default:
dd4131b3 BS	97	ret = 0;
dd4131b3 BS	98	break;
e80cfcfc	99	}
3c4cf535	100	DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
dd4131b3 BS	101
dd4131b3 BS	102	return ret;
e80cfcfc FB	103	}
e80cfcfc FB	104
77f193da BS	105	static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
77f193da BS	106	uint32_t val)
e80cfcfc	107	{
a8f48dcc	108	SLAVIO_CPUINTCTLState *s = opaque;
e80cfcfc	109	uint32_t saddr;
e80cfcfc	110
a8f48dcc	111	saddr = addr >> 2;
3c4cf535	112	DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
e80cfcfc FB	113	switch (saddr) {
e80cfcfc FB	114	case 1: // clear pending softints
462eda24	115	val &= CPU_SOFTIRQ_MASK \| CPU_IRQ_INT15_IN;
a8f48dcc	116	s->intreg_pending &= ~val;
0d0a7e69	117	slavio_check_interrupts(s->master, 1);
a8f48dcc BS	118	DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
a8f48dcc BS	119	s->intreg_pending);
f930d07e	120	break;
e80cfcfc	121	case 2: // set softint
6341fdcb	122	val &= CPU_SOFTIRQ_MASK;
a8f48dcc	123	s->intreg_pending \|= val;
0d0a7e69	124	slavio_check_interrupts(s->master, 1);
a8f48dcc BS	125	DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
a8f48dcc BS	126	s->intreg_pending);
f930d07e	127	break;
e80cfcfc	128	default:
f930d07e	129	break;
e80cfcfc FB	130	}
	131	}
	132
d60efc6b	133	static CPUReadMemoryFunc * const slavio_intctl_mem_read[3] = {
7c560456 BS	134	NULL,
7c560456 BS	135	NULL,
e80cfcfc FB	136	slavio_intctl_mem_readl,
	137	};
	138
d60efc6b	139	static CPUWriteMemoryFunc * const slavio_intctl_mem_write[3] = {
7c560456 BS	140	NULL,
7c560456 BS	141	NULL,
e80cfcfc FB	142	slavio_intctl_mem_writel,
	143	};
	144
	145	// master system interrupt controller
	146	static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
	147	{
	148	SLAVIO_INTCTLState *s = opaque;
dd4131b3	149	uint32_t saddr, ret;
e80cfcfc	150
a8f48dcc	151	saddr = addr >> 2;
e80cfcfc FB	152	switch (saddr) {
e80cfcfc FB	153	case 0:
9a87ce9b	154	ret = s->intregm_pending & ~MASTER_DISABLE;
dd4131b3	155	break;
e80cfcfc	156	case 1:
80be36b8	157	ret = s->intregm_disabled & MASTER_IRQ_MASK;
dd4131b3	158	break;
e80cfcfc	159	case 4:
dd4131b3 BS	160	ret = s->target_cpu;
dd4131b3 BS	161	break;
e80cfcfc	162	default:
dd4131b3 BS	163	ret = 0;
dd4131b3 BS	164	break;
e80cfcfc	165	}
1569fc29	166	DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
dd4131b3 BS	167
dd4131b3 BS	168	return ret;
e80cfcfc FB	169	}
e80cfcfc FB	170
77f193da BS	171	static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
77f193da BS	172	uint32_t val)
e80cfcfc FB	173	{
	174	SLAVIO_INTCTLState *s = opaque;
	175	uint32_t saddr;
	176
a8f48dcc	177	saddr = addr >> 2;
1569fc29	178	DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
e80cfcfc FB	179	switch (saddr) {
e80cfcfc FB	180	case 2: // clear (enable)
f930d07e	181	// Force clear unused bits
9a87ce9b	182	val &= MASTER_IRQ_MASK;
f930d07e	183	s->intregm_disabled &= ~val;
77f193da BS	184	DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
77f193da BS	185	s->intregm_disabled);
0d0a7e69	186	slavio_check_interrupts(s, 1);
f930d07e	187	break;
e80cfcfc	188	case 3: // set (disable, clear pending)
f930d07e	189	// Force clear unused bits
9a87ce9b	190	val &= MASTER_IRQ_MASK;
f930d07e BS	191	s->intregm_disabled \|= val;
f930d07e BS	192	s->intregm_pending &= ~val;
0d0a7e69	193	slavio_check_interrupts(s, 1);
77f193da BS	194	DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
77f193da BS	195	s->intregm_disabled);
f930d07e	196	break;
e80cfcfc	197	case 4:
f930d07e	198	s->target_cpu = val & (MAX_CPUS - 1);
0d0a7e69	199	slavio_check_interrupts(s, 1);
f930d07e BS	200	DPRINTF("Set master irq cpu %d\n", s->target_cpu);
f930d07e BS	201	break;
e80cfcfc	202	default:
f930d07e	203	break;
e80cfcfc FB	204	}
	205	}
	206
d60efc6b	207	static CPUReadMemoryFunc * const slavio_intctlm_mem_read[3] = {
7c560456 BS	208	NULL,
7c560456 BS	209	NULL,
e80cfcfc FB	210	slavio_intctlm_mem_readl,
	211	};
	212
d60efc6b	213	static CPUWriteMemoryFunc * const slavio_intctlm_mem_write[3] = {
7c560456 BS	214	NULL,
7c560456 BS	215	NULL,
e80cfcfc FB	216	slavio_intctlm_mem_writel,
	217	};
	218
d453c2c3	219	void slavio_pic_info(Monitor mon, DeviceState dev)
e80cfcfc	220	{
d453c2c3 BS	221	SysBusDevice *sd;
d453c2c3 BS	222	SLAVIO_INTCTLState *s;
e80cfcfc FB	223	int i;
e80cfcfc FB	224
d453c2c3 BS	225	sd = sysbus_from_qdev(dev);
d453c2c3 BS	226	s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
e80cfcfc	227	for (i = 0; i < MAX_CPUS; i++) {
376253ec	228	monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
a1961a4b	229	s->slaves[i].intreg_pending);
e80cfcfc	230	}
376253ec AL	231	monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
376253ec AL	232	s->intregm_pending, s->intregm_disabled);
e80cfcfc FB	233	}
e80cfcfc FB	234
d453c2c3	235	void slavio_irq_info(Monitor mon, DeviceState dev)
e80cfcfc FB	236	{
e80cfcfc FB	237	#ifndef DEBUG_IRQ_COUNT
376253ec	238	monitor_printf(mon, "irq statistic code not compiled.\n");
e80cfcfc	239	#else
d453c2c3 BS	240	SysBusDevice *sd;
d453c2c3 BS	241	SLAVIO_INTCTLState *s;
e80cfcfc FB	242	int i;
	243	int64_t count;
	244
d453c2c3 BS	245	sd = sysbus_from_qdev(dev);
d453c2c3 BS	246	s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
376253ec	247	monitor_printf(mon, "IRQ statistics:\n");
e80cfcfc FB	248	for (i = 0; i < 32; i++) {
	249	count = s->irq_count[i];
	250	if (count > 0)
376253ec	251	monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
e80cfcfc FB	252	}
	253	#endif
	254	}
	255
68556e2e	256	static const uint32_t intbit_to_level[] = {
462eda24 BS	257	2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12,
462eda24 BS	258	6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0,
68556e2e BS	259	};
68556e2e BS	260
0d0a7e69	261	static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
66321a11	262	{
327ac2e7 BS	263	uint32_t pending = s->intregm_pending, pil_pending;
327ac2e7 BS	264	unsigned int i, j;
66321a11 FB	265
	266	pending &= ~s->intregm_disabled;
	267
b3a23197	268	DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
ba3c64fb	269	for (i = 0; i < MAX_CPUS; i++) {
327ac2e7	270	pil_pending = 0;
462eda24 BS	271
462eda24 BS	272	/* If we are the current interrupt target, get hard interrupts */
9a87ce9b	273	if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
b3a23197 BS	274	(i == s->target_cpu)) {
b3a23197 BS	275	for (j = 0; j < 32; j++) {
462eda24	276	if ((pending & (1 << j)) && intbit_to_level[j]) {
68556e2e	277	pil_pending \|= 1 << intbit_to_level[j];
462eda24 BS	278	}
	279	}
	280	}
	281
	282	/* Calculate current pending hard interrupts for display */
	283	s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK \| CPU_IRQ_INT15_IN \|
	284	CPU_IRQ_TIMER_IN;
	285	if (i == s->target_cpu) {
	286	for (j = 0; j < 32; j++) {
	287	if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) {
	288	s->slaves[i].intreg_pending \|= 1 << intbit_to_level[j];
	289	}
b3a23197 BS	290	}
b3a23197 BS	291	}
462eda24 BS	292
	293	/* Level 15 and CPU timer interrupts are not maskable */
	294	pil_pending \|= s->slaves[i].intreg_pending &
	295	(CPU_IRQ_INT15_IN \| CPU_IRQ_TIMER_IN);
	296
	297	/* Add soft interrupts */
a1961a4b	298	pil_pending \|= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
327ac2e7	299
0d0a7e69	300	if (set_irqs) {
462eda24	301	for (j = MAX_PILS; j > 0; j--) {
0d0a7e69	302	if (pil_pending & (1 << j)) {
462eda24	303	if (!(s->slaves[i].irl_out & (1 << j))) {
0d0a7e69 BS	304	qemu_irq_raise(s->cpu_irqs[i][j]);
	305	}
	306	} else {
462eda24	307	if (s->slaves[i].irl_out & (1 << j)) {
0d0a7e69 BS	308	qemu_irq_lower(s->cpu_irqs[i][j]);
	309	}
	310	}
ba3c64fb FB	311	}
ba3c64fb FB	312	}
462eda24	313	s->slaves[i].irl_out = pil_pending;
ba3c64fb	314	}
66321a11 FB	315	}
66321a11 FB	316
e80cfcfc FB	317	/*
	318	* "irq" here is the bit number in the system interrupt register to
	319	* separate serial and keyboard interrupts sharing a level.
	320	*/
d7edfd27	321	static void slavio_set_irq(void *opaque, int irq, int level)
e80cfcfc FB	322	{
e80cfcfc FB	323	SLAVIO_INTCTLState *s = opaque;
b3a23197	324	uint32_t mask = 1 << irq;
68556e2e	325	uint32_t pil = intbit_to_level[irq];
462eda24	326	unsigned int i;
b3a23197 BS	327
	328	DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
	329	level);
	330	if (pil > 0) {
	331	if (level) {
327ac2e7 BS	332	#ifdef DEBUG_IRQ_COUNT
	333	s->irq_count[pil]++;
	334	#endif
b3a23197	335	s->intregm_pending \|= mask;
462eda24 BS	336	if (pil == 15) {
	337	for (i = 0; i < MAX_CPUS; i++) {
	338	s->slaves[i].intreg_pending \|= 1 << pil;
	339	}
	340	}
b3a23197 BS	341	} else {
b3a23197 BS	342	s->intregm_pending &= ~mask;
462eda24 BS	343	if (pil == 15) {
	344	for (i = 0; i < MAX_CPUS; i++) {
	345	s->slaves[i].intreg_pending &= ~(1 << pil);
	346	}
	347	}
b3a23197	348	}
0d0a7e69	349	slavio_check_interrupts(s, 1);
e80cfcfc FB	350	}
	351	}
	352
d7edfd27	353	static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
ba3c64fb FB	354	{
	355	SLAVIO_INTCTLState *s = opaque;
	356
b3a23197	357	DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
d7edfd27	358
e3a79bca	359	if (level) {
462eda24	360	s->slaves[cpu].intreg_pending \|= CPU_IRQ_TIMER_IN;
e3a79bca	361	} else {
462eda24	362	s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN;
e3a79bca	363	}
d7edfd27	364
0d0a7e69	365	slavio_check_interrupts(s, 1);
ba3c64fb FB	366	}
ba3c64fb FB	367
a1961a4b BS	368	static void slavio_set_irq_all(void *opaque, int irq, int level)
	369	{
	370	if (irq < 32) {
	371	slavio_set_irq(opaque, irq, level);
	372	} else {
	373	slavio_set_timer_irq_cpu(opaque, irq - 32, level);
	374	}
	375	}
	376
752ff2fa	377	static int vmstate_intctl_post_load(void *opaque)
e80cfcfc FB	378	{
e80cfcfc FB	379	SLAVIO_INTCTLState *s = opaque;
3b46e624	380
c9e95029 BS	381	slavio_check_interrupts(s, 0);
c9e95029 BS	382	return 0;
e80cfcfc FB	383	}
e80cfcfc FB	384
c9e95029 BS	385	static const VMStateDescription vmstate_intctl_cpu = {
	386	.name ="slavio_intctl_cpu",
	387	.version_id = 1,
	388	.minimum_version_id = 1,
	389	.minimum_version_id_old = 1,
	390	.fields = (VMStateField []) {
	391	VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState),
	392	VMSTATE_END_OF_LIST()
	393	}
	394	};
e80cfcfc	395
c9e95029 BS	396	static const VMStateDescription vmstate_intctl = {
	397	.name ="slavio_intctl",
	398	.version_id = 1,
	399	.minimum_version_id = 1,
	400	.minimum_version_id_old = 1,
752ff2fa	401	.post_load = vmstate_intctl_post_load,
c9e95029 BS	402	.fields = (VMStateField []) {
	403	VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1,
	404	vmstate_intctl_cpu, SLAVIO_CPUINTCTLState),
	405	VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState),
	406	VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState),
	407	VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState),
	408	VMSTATE_END_OF_LIST()
e80cfcfc	409	}
c9e95029	410	};
e80cfcfc FB	411
	412	static void slavio_intctl_reset(void *opaque)
	413	{
	414	SLAVIO_INTCTLState *s = opaque;
	415	int i;
	416
	417	for (i = 0; i < MAX_CPUS; i++) {
a1961a4b	418	s->slaves[i].intreg_pending = 0;
462eda24	419	s->slaves[i].irl_out = 0;
e80cfcfc	420	}
9a87ce9b	421	s->intregm_disabled = ~MASTER_IRQ_MASK;
e80cfcfc FB	422	s->intregm_pending = 0;
e80cfcfc FB	423	s->target_cpu = 0;
0d0a7e69	424	slavio_check_interrupts(s, 0);
e80cfcfc FB	425	}
e80cfcfc FB	426
81a322d4	427	static int slavio_intctl_init1(SysBusDevice *dev)
e80cfcfc	428	{
a1961a4b	429	SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
ee6847d1	430	int io_memory;
a1961a4b	431	unsigned int i, j;
e80cfcfc	432
a1961a4b BS	433	qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
	434	io_memory = cpu_register_io_memory(slavio_intctlm_mem_read,
	435	slavio_intctlm_mem_write, s);
	436	sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory);
e80cfcfc FB	437
e80cfcfc FB	438	for (i = 0; i < MAX_CPUS; i++) {
a1961a4b BS	439	for (j = 0; j < MAX_PILS; j++) {
	440	sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
	441	}
	442	io_memory = cpu_register_io_memory(slavio_intctl_mem_read,
	443	slavio_intctl_mem_write,
	444	&s->slaves[i]);
	445	sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
	446	s->slaves[i].cpu = i;
	447	s->slaves[i].master = s;
	448	}
c9e95029	449	vmstate_register(-1, &vmstate_intctl, s);
a1961a4b BS	450	qemu_register_reset(slavio_intctl_reset, s);
a1961a4b BS	451	slavio_intctl_reset(s);
81a322d4	452	return 0;
a1961a4b BS	453	}
a1961a4b BS	454
a1961a4b BS	455	static SysBusDeviceInfo slavio_intctl_info = {
	456	.init = slavio_intctl_init1,
	457	.qdev.name = "slavio_intctl",
	458	.qdev.size = sizeof(SLAVIO_INTCTLState),
a1961a4b	459	};
d7edfd27	460
a1961a4b BS	461	static void slavio_intctl_register_devices(void)
	462	{
	463	sysbus_register_withprop(&slavio_intctl_info);
e80cfcfc	464	}
a1961a4b BS	465
a1961a4b BS	466	device_init(slavio_intctl_register_devices)