projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| e516572f JB |
1 | #ifndef HW_ICH9_H |
| 2 | #define HW_ICH9_H | |
| 3 | ||
| 4 | #include "hw.h" | |
| 1de7afc9 | 5 | #include "qemu/range.h" |
| e516572f JB |
6 | #include "isa.h" |
| 7 | #include "sysbus.h" | |
| 8 | #include "pc.h" | |
| 9 | #include "apm.h" | |
| 10 | #include "ioapic.h" | |
| a2cb15b0 MT |
11 | #include "pci/pci.h" |
| 12 | #include "pci/pcie_host.h" | |
| 13 | #include "pci/pci_bridge.h" | |
| e516572f JB |
14 | #include "acpi.h" |
| 15 | #include "acpi_ich9.h" | |
| 16 | #include "pam.h" | |
| 06aac7bd | 17 | #include "pci/pci_bus.h" |
| e516572f JB |
18 | |
| 19 | void ich9_lpc_set_irq(void *opaque, int irq_num, int level); | |
| 20 | int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx); | |
| 21 | void ich9_lpc_pm_init(PCIDevice *pci_lpc, qemu_irq cmos_s3); | |
| 22 | PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus); | |
| 23 | i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base); | |
| 24 | ||
| 25 | #define ICH9_CC_SIZE (16 * 1024) /* 16KB */ | |
| 26 | ||
| 27 | #define TYPE_ICH9_LPC_DEVICE "ICH9 LPC" | |
| 28 | #define ICH9_LPC_DEVICE(obj) \ | |
| 29 | OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE) | |
| 30 | ||
| 31 | typedef struct ICH9LPCState { | |
| 32 | /* ICH9 LPC PCI to ISA bridge */ | |
| 33 | PCIDevice d; | |
| 34 | ||
| 35 | /* (pci device, intx) -> pirq | |
| 36 | * In real chipset case, the unused slots are never used | |
| 37 | * as ICH9 supports only D25-D32 irq routing. | |
| 38 | * On the other hand in qemu case, any slot/function can be populated | |
| 39 | * via command line option. | |
| 40 | * So fallback interrupt routing for any devices in any slots is necessary. | |
| 41 | */ | |
| 42 | uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; | |
| 43 | ||
| 44 | APMState apm; | |
| 45 | ICH9LPCPMRegs pm; | |
| 46 | uint32_t sci_level; /* track sci level */ | |
| 47 | ||
| 48 | /* 10.1 Chipset Configuration registers(Memory Space) | |
| 49 | which is pointed by RCBA */ | |
| 50 | uint8_t chip_config[ICH9_CC_SIZE]; | |
| 51 | /* isa bus */ | |
| 52 | ISABus *isa_bus; | |
| 53 | MemoryRegion rbca_mem; | |
| 3f5bc9e8 | 54 | Notifier machine_ready; |
| e516572f JB |
55 | |
| 56 | qemu_irq *pic; | |
| 57 | qemu_irq *ioapic; | |
| 58 | } ICH9LPCState; | |
| 59 | ||
| 60 | #define Q35_MASK(bit, ms_bit, ls_bit) \ | |
| 61 | ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) | |
| 62 | ||
| 63 | /* ICH9: Chipset Configuration Registers */ | |
| 64 | #define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) | |
| 65 | ||
| 66 | #define ICH9_CC | |
| 67 | #define ICH9_CC_D28IP 0x310C | |
| 68 | #define ICH9_CC_D28IP_SHIFT 4 | |
| 69 | #define ICH9_CC_D28IP_MASK 0xf | |
| 70 | #define ICH9_CC_D28IP_DEFAULT 0x00214321 | |
| 71 | #define ICH9_CC_D31IR 0x3140 | |
| 72 | #define ICH9_CC_D30IR 0x3142 | |
| 73 | #define ICH9_CC_D29IR 0x3144 | |
| 74 | #define ICH9_CC_D28IR 0x3146 | |
| 75 | #define ICH9_CC_D27IR 0x3148 | |
| 76 | #define ICH9_CC_D26IR 0x314C | |
| 77 | #define ICH9_CC_D25IR 0x3150 | |
| 78 | #define ICH9_CC_DIR_DEFAULT 0x3210 | |
| 79 | #define ICH9_CC_D30IR_DEFAULT 0x0 | |
| 80 | #define ICH9_CC_DIR_SHIFT 4 | |
| 81 | #define ICH9_CC_DIR_MASK 0x7 | |
| 82 | #define ICH9_CC_OIC 0x31FF | |
| 83 | #define ICH9_CC_OIC_AEN 0x1 | |
| 84 | ||
| 85 | /* D28:F[0-5] */ | |
| 86 | #define ICH9_PCIE_DEV 28 | |
| 87 | #define ICH9_PCIE_FUNC_MAX 6 | |
| 88 | ||
| 89 | ||
| 90 | /* D29:F0 USB UHCI Controller #1 */ | |
| 91 | #define ICH9_USB_UHCI1_DEV 29 | |
| 92 | #define ICH9_USB_UHCI1_FUNC 0 | |
| 93 | ||
| 94 | /* D30:F0 DMI-to-PCI brdige */ | |
| 95 | #define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE" | |
| 96 | #define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0 | |
| 97 | ||
| 98 | #define ICH9_D2P_BRIDGE_DEV 30 | |
| 99 | #define ICH9_D2P_BRIDGE_FUNC 0 | |
| 100 | ||
| 101 | #define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) | |
| 102 | ||
| 103 | #define ICH9_D2P_A2_REVISION 0x92 | |
| 104 | ||
| 105 | ||
| 106 | /* D31:F1 LPC controller */ | |
| 107 | #define ICH9_A2_LPC "ICH9 A2 LPC" | |
| 108 | #define ICH9_A2_LPC_SAVEVM_VERSION 0 | |
| 109 | ||
| 110 | #define ICH9_LPC_DEV 31 | |
| 111 | #define ICH9_LPC_FUNC 0 | |
| 112 | ||
| 113 | #define ICH9_A2_LPC_REVISION 0x2 | |
| 114 | #define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ | |
| 115 | ||
| 116 | #define ICH9_LPC_PMBASE 0x40 | |
| 117 | #define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7) | |
| 118 | #define ICH9_LPC_PMBASE_RTE 0x1 | |
| 119 | #define ICH9_LPC_PMBASE_DEFAULT 0x1 | |
| 120 | #define ICH9_LPC_ACPI_CTRL 0x44 | |
| 121 | #define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 | |
| 122 | #define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0) | |
| 123 | #define ICH9_LPC_ACPI_CTRL_9 0x0 | |
| 124 | #define ICH9_LPC_ACPI_CTRL_10 0x1 | |
| 125 | #define ICH9_LPC_ACPI_CTRL_11 0x2 | |
| 126 | #define ICH9_LPC_ACPI_CTRL_20 0x4 | |
| 127 | #define ICH9_LPC_ACPI_CTRL_21 0x5 | |
| 128 | #define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 | |
| 129 | ||
| 130 | #define ICH9_LPC_PIRQA_ROUT 0x60 | |
| 131 | #define ICH9_LPC_PIRQB_ROUT 0x61 | |
| 132 | #define ICH9_LPC_PIRQC_ROUT 0x62 | |
| 133 | #define ICH9_LPC_PIRQD_ROUT 0x63 | |
| 134 | ||
| 135 | #define ICH9_LPC_PIRQE_ROUT 0x68 | |
| 136 | #define ICH9_LPC_PIRQF_ROUT 0x69 | |
| 137 | #define ICH9_LPC_PIRQG_ROUT 0x6a | |
| 138 | #define ICH9_LPC_PIRQH_ROUT 0x6b | |
| 139 | ||
| 140 | #define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 | |
| 141 | #define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0) | |
| 142 | #define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 | |
| 143 | ||
| 144 | #define ICH9_LPC_RCBA 0xf0 | |
| 145 | #define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14) | |
| 146 | #define ICH9_LPC_RCBA_EN 0x1 | |
| 147 | #define ICH9_LPC_RCBA_DEFAULT 0x0 | |
| 148 | ||
| 149 | #define ICH9_LPC_PIC_NUM_PINS 16 | |
| 150 | #define ICH9_LPC_IOAPIC_NUM_PINS 24 | |
| 151 | ||
| 152 | /* D31:F2 SATA Controller #1 */ | |
| 153 | #define ICH9_SATA1_DEV 31 | |
| 154 | #define ICH9_SATA1_FUNC 2 | |
| 155 | ||
| 156 | /* D30:F1 power management I/O registers | |
| 157 | offset from the address ICH9_LPC_PMBASE */ | |
| 158 | ||
| 159 | /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ | |
| 160 | #define ICH9_PMIO_SIZE 128 | |
| 161 | #define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) | |
| 162 | ||
| 163 | #define ICH9_PMIO_PM1_STS 0x00 | |
| 164 | #define ICH9_PMIO_PM1_EN 0x02 | |
| 165 | #define ICH9_PMIO_PM1_CNT 0x04 | |
| 166 | #define ICH9_PMIO_PM1_TMR 0x08 | |
| 167 | #define ICH9_PMIO_GPE0_STS 0x20 | |
| 168 | #define ICH9_PMIO_GPE0_EN 0x28 | |
| 169 | #define ICH9_PMIO_GPE0_LEN 16 | |
| 170 | #define ICH9_PMIO_SMI_EN 0x30 | |
| 171 | #define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) | |
| 172 | #define ICH9_PMIO_SMI_STS 0x34 | |
| 173 | ||
| 174 | /* FADT ACPI_ENABLE/ACPI_DISABLE */ | |
| 175 | #define ICH9_APM_ACPI_ENABLE 0x2 | |
| 176 | #define ICH9_APM_ACPI_DISABLE 0x3 | |
| 177 | ||
| 178 | ||
| 179 | /* D31:F3 SMBus controller */ | |
| 180 | #define ICH9_A2_SMB_REVISION 0x02 | |
| 181 | #define ICH9_SMB_PI 0x00 | |
| 182 | ||
| 183 | #define ICH9_SMB_SMBMBAR0 0x10 | |
| 184 | #define ICH9_SMB_SMBMBAR1 0x14 | |
| 185 | #define ICH9_SMB_SMBM_BAR 0 | |
| 186 | #define ICH9_SMB_SMBM_SIZE (1 << 8) | |
| 187 | #define ICH9_SMB_SMB_BASE 0x20 | |
| 188 | #define ICH9_SMB_SMB_BASE_BAR 4 | |
| 189 | #define ICH9_SMB_SMB_BASE_SIZE (1 << 5) | |
| 190 | #define ICH9_SMB_HOSTC 0x40 | |
| 191 | #define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) | |
| 192 | #define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) | |
| 193 | #define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) | |
| 194 | #define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) | |
| 195 | ||
| 196 | /* D31:F3 SMBus I/O and memory mapped I/O registers */ | |
| 197 | #define ICH9_SMB_DEV 31 | |
| 198 | #define ICH9_SMB_FUNC 3 | |
| 199 | ||
| 200 | #define ICH9_SMB_HST_STS 0x00 | |
| 201 | #define ICH9_SMB_HST_CNT 0x02 | |
| 202 | #define ICH9_SMB_HST_CMD 0x03 | |
| 203 | #define ICH9_SMB_XMIT_SLVA 0x04 | |
| 204 | #define ICH9_SMB_HST_D0 0x05 | |
| 205 | #define ICH9_SMB_HST_D1 0x06 | |
| 206 | #define ICH9_SMB_HOST_BLOCK_DB 0x07 | |
| 207 | ||
| 208 | #endif /* HW_ICH9_H */ |