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Commit | Line | Data |
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39ac8455 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Hypercall based emulated RTAS | |
5 | * | |
6 | * Copyright (c) 2010-2011 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
39ac8455 | 28 | #include "cpu.h" |
03dd024f | 29 | #include "qemu/log.h" |
ce9863b7 | 30 | #include "qemu/error-report.h" |
9c17d615 | 31 | #include "sysemu/sysemu.h" |
dccfcd0e | 32 | #include "sysemu/char.h" |
39ac8455 | 33 | #include "hw/qdev.h" |
9c17d615 | 34 | #include "sysemu/device_tree.h" |
db4ef288 | 35 | #include "sysemu/cpus.h" |
77ac58dd | 36 | #include "sysemu/kvm.h" |
39ac8455 | 37 | |
0d09e41a PB |
38 | #include "hw/ppc/spapr.h" |
39 | #include "hw/ppc/spapr_vio.h" | |
eeddd59f | 40 | #include "hw/ppc/spapr_rtas.h" |
af81cf32 | 41 | #include "hw/ppc/ppc.h" |
e010ad8f | 42 | #include "qapi-event.h" |
e3943228 | 43 | #include "hw/boards.h" |
39ac8455 DG |
44 | |
45 | #include <libfdt.h> | |
8c8639df | 46 | #include "hw/ppc/spapr_drc.h" |
f348b6d1 | 47 | #include "qemu/cutils.h" |
028ec3ce | 48 | #include "trace.h" |
3f5dabce | 49 | #include "hw/ppc/fdt.h" |
8c8639df | 50 | |
28e02042 | 51 | static sPAPRConfigureConnectorState *spapr_ccs_find(sPAPRMachineState *spapr, |
46503c2b MR |
52 | uint32_t drc_index) |
53 | { | |
54 | sPAPRConfigureConnectorState *ccs = NULL; | |
55 | ||
56 | QTAILQ_FOREACH(ccs, &spapr->ccs_list, next) { | |
57 | if (ccs->drc_index == drc_index) { | |
58 | break; | |
59 | } | |
60 | } | |
61 | ||
62 | return ccs; | |
63 | } | |
64 | ||
28e02042 | 65 | static void spapr_ccs_add(sPAPRMachineState *spapr, |
46503c2b MR |
66 | sPAPRConfigureConnectorState *ccs) |
67 | { | |
68 | g_assert(!spapr_ccs_find(spapr, ccs->drc_index)); | |
69 | QTAILQ_INSERT_HEAD(&spapr->ccs_list, ccs, next); | |
70 | } | |
71 | ||
28e02042 | 72 | static void spapr_ccs_remove(sPAPRMachineState *spapr, |
46503c2b MR |
73 | sPAPRConfigureConnectorState *ccs) |
74 | { | |
75 | QTAILQ_REMOVE(&spapr->ccs_list, ccs, next); | |
76 | g_free(ccs); | |
77 | } | |
78 | ||
79 | void spapr_ccs_reset_hook(void *opaque) | |
80 | { | |
28e02042 | 81 | sPAPRMachineState *spapr = opaque; |
46503c2b MR |
82 | sPAPRConfigureConnectorState *ccs, *ccs_tmp; |
83 | ||
84 | QTAILQ_FOREACH_SAFE(ccs, &spapr->ccs_list, next, ccs_tmp) { | |
85 | spapr_ccs_remove(spapr, ccs); | |
86 | } | |
87 | } | |
39ac8455 | 88 | |
28e02042 | 89 | static void rtas_display_character(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
821303f5 DG |
90 | uint32_t token, uint32_t nargs, |
91 | target_ulong args, | |
92 | uint32_t nret, target_ulong rets) | |
93 | { | |
94 | uint8_t c = rtas_ld(args, 0); | |
5f2e2ba2 | 95 | VIOsPAPRDevice *sdev = vty_lookup(spapr, 0); |
821303f5 DG |
96 | |
97 | if (!sdev) { | |
a64d325d | 98 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
821303f5 DG |
99 | } else { |
100 | vty_putchars(sdev, &c, sizeof(c)); | |
a64d325d | 101 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
821303f5 DG |
102 | } |
103 | } | |
104 | ||
28e02042 | 105 | static void rtas_power_off(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
821303f5 DG |
106 | uint32_t token, uint32_t nargs, target_ulong args, |
107 | uint32_t nret, target_ulong rets) | |
108 | { | |
109 | if (nargs != 2 || nret != 1) { | |
a64d325d | 110 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
821303f5 DG |
111 | return; |
112 | } | |
113 | qemu_system_shutdown_request(); | |
8a9c1b77 | 114 | cpu_stop_current(); |
a64d325d | 115 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
821303f5 DG |
116 | } |
117 | ||
28e02042 | 118 | static void rtas_system_reboot(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
c821a43c DG |
119 | uint32_t token, uint32_t nargs, |
120 | target_ulong args, | |
121 | uint32_t nret, target_ulong rets) | |
122 | { | |
123 | if (nargs != 0 || nret != 1) { | |
a64d325d | 124 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
c821a43c DG |
125 | return; |
126 | } | |
127 | qemu_system_reset_request(); | |
a64d325d | 128 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
c821a43c DG |
129 | } |
130 | ||
210b580b | 131 | static void rtas_query_cpu_stopped_state(PowerPCCPU *cpu_, |
28e02042 | 132 | sPAPRMachineState *spapr, |
a9f8ad8f DG |
133 | uint32_t token, uint32_t nargs, |
134 | target_ulong args, | |
135 | uint32_t nret, target_ulong rets) | |
136 | { | |
137 | target_ulong id; | |
0f20ba62 | 138 | PowerPCCPU *cpu; |
a9f8ad8f DG |
139 | |
140 | if (nargs != 1 || nret != 2) { | |
a64d325d | 141 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
a9f8ad8f DG |
142 | return; |
143 | } | |
144 | ||
145 | id = rtas_ld(args, 0); | |
0f20ba62 | 146 | cpu = ppc_get_vcpu_by_dt_id(id); |
05318a85 | 147 | if (cpu != NULL) { |
0f20ba62 | 148 | if (CPU(cpu)->halted) { |
a9f8ad8f DG |
149 | rtas_st(rets, 1, 0); |
150 | } else { | |
151 | rtas_st(rets, 1, 2); | |
152 | } | |
153 | ||
a64d325d | 154 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
a9f8ad8f DG |
155 | return; |
156 | } | |
157 | ||
158 | /* Didn't find a matching cpu */ | |
a64d325d | 159 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
a9f8ad8f DG |
160 | } |
161 | ||
af81cf32 BR |
162 | /* |
163 | * Set the timebase offset of the CPU to that of first CPU. | |
164 | * This helps hotplugged CPU to have the correct timebase offset. | |
165 | */ | |
166 | static void spapr_cpu_update_tb_offset(PowerPCCPU *cpu) | |
167 | { | |
168 | PowerPCCPU *fcpu = POWERPC_CPU(first_cpu); | |
169 | ||
170 | cpu->env.tb_env->tb_offset = fcpu->env.tb_env->tb_offset; | |
171 | } | |
172 | ||
173 | static void spapr_cpu_set_endianness(PowerPCCPU *cpu) | |
174 | { | |
175 | PowerPCCPU *fcpu = POWERPC_CPU(first_cpu); | |
176 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(fcpu); | |
177 | ||
178 | if (!pcc->interrupts_big_endian(fcpu)) { | |
179 | cpu->env.spr[SPR_LPCR] |= LPCR_ILE; | |
180 | } | |
181 | } | |
182 | ||
28e02042 | 183 | static void rtas_start_cpu(PowerPCCPU *cpu_, sPAPRMachineState *spapr, |
a9f8ad8f DG |
184 | uint32_t token, uint32_t nargs, |
185 | target_ulong args, | |
186 | uint32_t nret, target_ulong rets) | |
187 | { | |
188 | target_ulong id, start, r3; | |
0f20ba62 | 189 | PowerPCCPU *cpu; |
a9f8ad8f DG |
190 | |
191 | if (nargs != 3 || nret != 1) { | |
a64d325d | 192 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
a9f8ad8f DG |
193 | return; |
194 | } | |
195 | ||
196 | id = rtas_ld(args, 0); | |
197 | start = rtas_ld(args, 1); | |
198 | r3 = rtas_ld(args, 2); | |
199 | ||
0f20ba62 AK |
200 | cpu = ppc_get_vcpu_by_dt_id(id); |
201 | if (cpu != NULL) { | |
202 | CPUState *cs = CPU(cpu); | |
c67e216b | 203 | CPUPPCState *env = &cpu->env; |
a9f8ad8f | 204 | |
c67e216b | 205 | if (!cs->halted) { |
a64d325d | 206 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
a9f8ad8f DG |
207 | return; |
208 | } | |
209 | ||
048706d9 DG |
210 | /* This will make sure qemu state is up to date with kvm, and |
211 | * mark it dirty so our changes get flushed back before the | |
212 | * new cpu enters */ | |
dd1750d7 | 213 | kvm_cpu_synchronize_state(cs); |
048706d9 | 214 | |
a9f8ad8f DG |
215 | env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME); |
216 | env->nip = start; | |
217 | env->gpr[3] = r3; | |
c67e216b | 218 | cs->halted = 0; |
af81cf32 BR |
219 | spapr_cpu_set_endianness(cpu); |
220 | spapr_cpu_update_tb_offset(cpu); | |
a9f8ad8f | 221 | |
c67e216b | 222 | qemu_cpu_kick(cs); |
a9f8ad8f | 223 | |
a64d325d | 224 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
a9f8ad8f DG |
225 | return; |
226 | } | |
227 | ||
228 | /* Didn't find a matching cpu */ | |
a64d325d | 229 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
a9f8ad8f DG |
230 | } |
231 | ||
28e02042 | 232 | static void rtas_stop_self(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
59760f2d AK |
233 | uint32_t token, uint32_t nargs, |
234 | target_ulong args, | |
235 | uint32_t nret, target_ulong rets) | |
236 | { | |
237 | CPUState *cs = CPU(cpu); | |
238 | CPUPPCState *env = &cpu->env; | |
239 | ||
240 | cs->halted = 1; | |
9102deda | 241 | qemu_cpu_kick(cs); |
59760f2d AK |
242 | /* |
243 | * While stopping a CPU, the guest calls H_CPPR which | |
244 | * effectively disables interrupts on XICS level. | |
245 | * However decrementer interrupts in TCG can still | |
246 | * wake the CPU up so here we disable interrupts in MSR | |
247 | * as well. | |
248 | * As rtas_start_cpu() resets the whole MSR anyway, there is | |
249 | * no need to bother with specific bits, we just clear it. | |
250 | */ | |
251 | env->msr = 0; | |
252 | } | |
253 | ||
c920f7b4 DG |
254 | static inline int sysparm_st(target_ulong addr, target_ulong len, |
255 | const void *val, uint16_t vallen) | |
256 | { | |
257 | hwaddr phys = ppc64_phys_to_real(addr); | |
258 | ||
259 | if (len < 2) { | |
260 | return RTAS_OUT_SYSPARM_PARAM_ERROR; | |
261 | } | |
262 | stw_be_phys(&address_space_memory, phys, vallen); | |
263 | cpu_physical_memory_write(phys + 2, val, MIN(len - 2, vallen)); | |
264 | return RTAS_OUT_SUCCESS; | |
265 | } | |
266 | ||
3ada6b11 | 267 | static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu, |
28e02042 | 268 | sPAPRMachineState *spapr, |
3ada6b11 AK |
269 | uint32_t token, uint32_t nargs, |
270 | target_ulong args, | |
271 | uint32_t nret, target_ulong rets) | |
272 | { | |
273 | target_ulong parameter = rtas_ld(args, 0); | |
274 | target_ulong buffer = rtas_ld(args, 1); | |
275 | target_ulong length = rtas_ld(args, 2); | |
c920f7b4 | 276 | target_ulong ret; |
3ada6b11 AK |
277 | |
278 | switch (parameter) { | |
3b50d897 | 279 | case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: { |
e3943228 SB |
280 | char *param_val = g_strdup_printf("MaxEntCap=%d," |
281 | "DesMem=%llu," | |
282 | "DesProcs=%d," | |
283 | "MaxPlatProcs=%d", | |
284 | max_cpus, | |
285 | current_machine->ram_size / M_BYTE, | |
286 | smp_cpus, | |
287 | max_cpus); | |
c920f7b4 | 288 | ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1); |
3b50d897 S |
289 | g_free(param_val); |
290 | break; | |
291 | } | |
3052d951 S |
292 | case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: { |
293 | uint8_t param_val = DIAGNOSTICS_RUN_MODE_DISABLED; | |
294 | ||
c920f7b4 | 295 | ret = sysparm_st(buffer, length, ¶m_val, sizeof(param_val)); |
3ada6b11 AK |
296 | break; |
297 | } | |
b907d7b0 | 298 | case RTAS_SYSPARM_UUID: |
9c5ce8db FZ |
299 | ret = sysparm_st(buffer, length, (unsigned char *)&qemu_uuid, |
300 | (qemu_uuid_set ? 16 : 0)); | |
b907d7b0 | 301 | break; |
3052d951 S |
302 | default: |
303 | ret = RTAS_OUT_NOT_SUPPORTED; | |
304 | } | |
3ada6b11 AK |
305 | |
306 | rtas_st(rets, 0, ret); | |
307 | } | |
308 | ||
309 | static void rtas_ibm_set_system_parameter(PowerPCCPU *cpu, | |
28e02042 | 310 | sPAPRMachineState *spapr, |
3ada6b11 AK |
311 | uint32_t token, uint32_t nargs, |
312 | target_ulong args, | |
313 | uint32_t nret, target_ulong rets) | |
314 | { | |
315 | target_ulong parameter = rtas_ld(args, 0); | |
316 | target_ulong ret = RTAS_OUT_NOT_SUPPORTED; | |
317 | ||
318 | switch (parameter) { | |
3b50d897 | 319 | case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: |
3052d951 | 320 | case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: |
b907d7b0 | 321 | case RTAS_SYSPARM_UUID: |
3ada6b11 AK |
322 | ret = RTAS_OUT_NOT_AUTHORIZED; |
323 | break; | |
324 | } | |
325 | ||
326 | rtas_st(rets, 0, ret); | |
327 | } | |
328 | ||
2e14072f | 329 | static void rtas_ibm_os_term(PowerPCCPU *cpu, |
28e02042 | 330 | sPAPRMachineState *spapr, |
2e14072f ND |
331 | uint32_t token, uint32_t nargs, |
332 | target_ulong args, | |
333 | uint32_t nret, target_ulong rets) | |
334 | { | |
335 | target_ulong ret = 0; | |
336 | ||
c86f106b AN |
337 | qapi_event_send_guest_panicked(GUEST_PANIC_ACTION_PAUSE, false, NULL, |
338 | &error_abort); | |
2e14072f ND |
339 | |
340 | rtas_st(rets, 0, ret); | |
341 | } | |
342 | ||
28e02042 | 343 | static void rtas_set_power_level(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
094d2058 NF |
344 | uint32_t token, uint32_t nargs, |
345 | target_ulong args, uint32_t nret, | |
346 | target_ulong rets) | |
347 | { | |
348 | int32_t power_domain; | |
349 | ||
350 | if (nargs != 2 || nret != 2) { | |
351 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
352 | return; | |
353 | } | |
354 | ||
355 | /* we currently only use a single, "live insert" powerdomain for | |
356 | * hotplugged/dlpar'd resources, so the power is always live/full (100) | |
357 | */ | |
358 | power_domain = rtas_ld(args, 0); | |
359 | if (power_domain != -1) { | |
360 | rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); | |
361 | return; | |
362 | } | |
363 | ||
364 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
365 | rtas_st(rets, 1, 100); | |
366 | } | |
367 | ||
28e02042 | 368 | static void rtas_get_power_level(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
094d2058 NF |
369 | uint32_t token, uint32_t nargs, |
370 | target_ulong args, uint32_t nret, | |
371 | target_ulong rets) | |
372 | { | |
373 | int32_t power_domain; | |
374 | ||
375 | if (nargs != 1 || nret != 2) { | |
376 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
377 | return; | |
378 | } | |
379 | ||
380 | /* we currently only use a single, "live insert" powerdomain for | |
381 | * hotplugged/dlpar'd resources, so the power is always live/full (100) | |
382 | */ | |
383 | power_domain = rtas_ld(args, 0); | |
384 | if (power_domain != -1) { | |
385 | rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); | |
386 | return; | |
387 | } | |
388 | ||
389 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
390 | rtas_st(rets, 1, 100); | |
391 | } | |
392 | ||
8c8639df MD |
393 | static bool sensor_type_is_dr(uint32_t sensor_type) |
394 | { | |
395 | switch (sensor_type) { | |
396 | case RTAS_SENSOR_TYPE_ISOLATION_STATE: | |
397 | case RTAS_SENSOR_TYPE_DR: | |
398 | case RTAS_SENSOR_TYPE_ALLOCATION_STATE: | |
399 | return true; | |
400 | } | |
401 | ||
402 | return false; | |
403 | } | |
404 | ||
28e02042 | 405 | static void rtas_set_indicator(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
8c8639df MD |
406 | uint32_t token, uint32_t nargs, |
407 | target_ulong args, uint32_t nret, | |
408 | target_ulong rets) | |
409 | { | |
410 | uint32_t sensor_type; | |
411 | uint32_t sensor_index; | |
412 | uint32_t sensor_state; | |
0cb688d2 | 413 | uint32_t ret = RTAS_OUT_SUCCESS; |
8c8639df MD |
414 | sPAPRDRConnector *drc; |
415 | sPAPRDRConnectorClass *drck; | |
416 | ||
417 | if (nargs != 3 || nret != 1) { | |
0cb688d2 MR |
418 | ret = RTAS_OUT_PARAM_ERROR; |
419 | goto out; | |
8c8639df MD |
420 | } |
421 | ||
422 | sensor_type = rtas_ld(args, 0); | |
423 | sensor_index = rtas_ld(args, 1); | |
424 | sensor_state = rtas_ld(args, 2); | |
425 | ||
426 | if (!sensor_type_is_dr(sensor_type)) { | |
427 | goto out_unimplemented; | |
428 | } | |
429 | ||
430 | /* if this is a DR sensor we can assume sensor_index == drc_index */ | |
431 | drc = spapr_dr_connector_by_index(sensor_index); | |
432 | if (!drc) { | |
028ec3ce | 433 | trace_spapr_rtas_set_indicator_invalid(sensor_index); |
0cb688d2 MR |
434 | ret = RTAS_OUT_PARAM_ERROR; |
435 | goto out; | |
8c8639df MD |
436 | } |
437 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
438 | ||
439 | switch (sensor_type) { | |
440 | case RTAS_SENSOR_TYPE_ISOLATION_STATE: | |
46503c2b MR |
441 | /* if the guest is configuring a device attached to this |
442 | * DRC, we should reset the configuration state at this | |
443 | * point since it may no longer be reliable (guest released | |
444 | * device and needs to start over, or unplug occurred so | |
445 | * the FDT is no longer valid) | |
446 | */ | |
447 | if (sensor_state == SPAPR_DR_ISOLATION_STATE_ISOLATED) { | |
448 | sPAPRConfigureConnectorState *ccs = spapr_ccs_find(spapr, | |
449 | sensor_index); | |
450 | if (ccs) { | |
451 | spapr_ccs_remove(spapr, ccs); | |
452 | } | |
453 | } | |
0cb688d2 | 454 | ret = drck->set_isolation_state(drc, sensor_state); |
8c8639df MD |
455 | break; |
456 | case RTAS_SENSOR_TYPE_DR: | |
0cb688d2 | 457 | ret = drck->set_indicator_state(drc, sensor_state); |
8c8639df MD |
458 | break; |
459 | case RTAS_SENSOR_TYPE_ALLOCATION_STATE: | |
0cb688d2 | 460 | ret = drck->set_allocation_state(drc, sensor_state); |
8c8639df MD |
461 | break; |
462 | default: | |
463 | goto out_unimplemented; | |
464 | } | |
465 | ||
0cb688d2 MR |
466 | out: |
467 | rtas_st(rets, 0, ret); | |
8c8639df MD |
468 | return; |
469 | ||
470 | out_unimplemented: | |
471 | /* currently only DR-related sensors are implemented */ | |
028ec3ce | 472 | trace_spapr_rtas_set_indicator_not_supported(sensor_index, sensor_type); |
8c8639df MD |
473 | rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); |
474 | } | |
475 | ||
28e02042 | 476 | static void rtas_get_sensor_state(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
886445a6 MD |
477 | uint32_t token, uint32_t nargs, |
478 | target_ulong args, uint32_t nret, | |
479 | target_ulong rets) | |
480 | { | |
481 | uint32_t sensor_type; | |
482 | uint32_t sensor_index; | |
0cb688d2 | 483 | uint32_t sensor_state = 0; |
886445a6 MD |
484 | sPAPRDRConnector *drc; |
485 | sPAPRDRConnectorClass *drck; | |
0cb688d2 | 486 | uint32_t ret = RTAS_OUT_SUCCESS; |
886445a6 MD |
487 | |
488 | if (nargs != 2 || nret != 2) { | |
0cb688d2 MR |
489 | ret = RTAS_OUT_PARAM_ERROR; |
490 | goto out; | |
886445a6 MD |
491 | } |
492 | ||
493 | sensor_type = rtas_ld(args, 0); | |
494 | sensor_index = rtas_ld(args, 1); | |
495 | ||
496 | if (sensor_type != RTAS_SENSOR_TYPE_ENTITY_SENSE) { | |
497 | /* currently only DR-related sensors are implemented */ | |
028ec3ce LV |
498 | trace_spapr_rtas_get_sensor_state_not_supported(sensor_index, |
499 | sensor_type); | |
0cb688d2 MR |
500 | ret = RTAS_OUT_NOT_SUPPORTED; |
501 | goto out; | |
886445a6 MD |
502 | } |
503 | ||
504 | drc = spapr_dr_connector_by_index(sensor_index); | |
505 | if (!drc) { | |
028ec3ce | 506 | trace_spapr_rtas_get_sensor_state_invalid(sensor_index); |
0cb688d2 MR |
507 | ret = RTAS_OUT_PARAM_ERROR; |
508 | goto out; | |
886445a6 MD |
509 | } |
510 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
0cb688d2 | 511 | ret = drck->entity_sense(drc, &sensor_state); |
886445a6 | 512 | |
0cb688d2 MR |
513 | out: |
514 | rtas_st(rets, 0, ret); | |
515 | rtas_st(rets, 1, sensor_state); | |
886445a6 MD |
516 | } |
517 | ||
46503c2b MR |
518 | /* configure-connector work area offsets, int32_t units for field |
519 | * indexes, bytes for field offset/len values. | |
520 | * | |
521 | * as documented by PAPR+ v2.7, 13.5.3.5 | |
522 | */ | |
523 | #define CC_IDX_NODE_NAME_OFFSET 2 | |
524 | #define CC_IDX_PROP_NAME_OFFSET 2 | |
525 | #define CC_IDX_PROP_LEN 3 | |
526 | #define CC_IDX_PROP_DATA_OFFSET 4 | |
527 | #define CC_VAL_DATA_OFFSET ((CC_IDX_PROP_DATA_OFFSET + 1) * 4) | |
528 | #define CC_WA_LEN 4096 | |
529 | ||
f201987b DG |
530 | static void configure_connector_st(target_ulong addr, target_ulong offset, |
531 | const void *buf, size_t len) | |
532 | { | |
533 | cpu_physical_memory_write(ppc64_phys_to_real(addr + offset), | |
534 | buf, MIN(len, CC_WA_LEN - offset)); | |
535 | } | |
536 | ||
46503c2b | 537 | static void rtas_ibm_configure_connector(PowerPCCPU *cpu, |
28e02042 | 538 | sPAPRMachineState *spapr, |
46503c2b MR |
539 | uint32_t token, uint32_t nargs, |
540 | target_ulong args, uint32_t nret, | |
541 | target_ulong rets) | |
542 | { | |
543 | uint64_t wa_addr; | |
544 | uint64_t wa_offset; | |
545 | uint32_t drc_index; | |
546 | sPAPRDRConnector *drc; | |
547 | sPAPRDRConnectorClass *drck; | |
548 | sPAPRConfigureConnectorState *ccs; | |
549 | sPAPRDRCCResponse resp = SPAPR_DR_CC_RESPONSE_CONTINUE; | |
550 | int rc; | |
551 | const void *fdt; | |
552 | ||
553 | if (nargs != 2 || nret != 1) { | |
554 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
555 | return; | |
556 | } | |
557 | ||
558 | wa_addr = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 0); | |
559 | ||
560 | drc_index = rtas_ld(wa_addr, 0); | |
561 | drc = spapr_dr_connector_by_index(drc_index); | |
562 | if (!drc) { | |
028ec3ce | 563 | trace_spapr_rtas_ibm_configure_connector_invalid(drc_index); |
46503c2b MR |
564 | rc = RTAS_OUT_PARAM_ERROR; |
565 | goto out; | |
566 | } | |
567 | ||
568 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
569 | fdt = drck->get_fdt(drc, NULL); | |
e6fc9568 | 570 | if (!fdt) { |
028ec3ce | 571 | trace_spapr_rtas_ibm_configure_connector_missing_fdt(drc_index); |
e6fc9568 BR |
572 | rc = SPAPR_DR_CC_RESPONSE_NOT_CONFIGURABLE; |
573 | goto out; | |
574 | } | |
46503c2b MR |
575 | |
576 | ccs = spapr_ccs_find(spapr, drc_index); | |
577 | if (!ccs) { | |
578 | ccs = g_new0(sPAPRConfigureConnectorState, 1); | |
579 | (void)drck->get_fdt(drc, &ccs->fdt_offset); | |
580 | ccs->drc_index = drc_index; | |
581 | spapr_ccs_add(spapr, ccs); | |
582 | } | |
583 | ||
584 | do { | |
585 | uint32_t tag; | |
586 | const char *name; | |
587 | const struct fdt_property *prop; | |
588 | int fdt_offset_next, prop_len; | |
589 | ||
590 | tag = fdt_next_tag(fdt, ccs->fdt_offset, &fdt_offset_next); | |
591 | ||
592 | switch (tag) { | |
593 | case FDT_BEGIN_NODE: | |
594 | ccs->fdt_depth++; | |
595 | name = fdt_get_name(fdt, ccs->fdt_offset, NULL); | |
596 | ||
597 | /* provide the name of the next OF node */ | |
598 | wa_offset = CC_VAL_DATA_OFFSET; | |
599 | rtas_st(wa_addr, CC_IDX_NODE_NAME_OFFSET, wa_offset); | |
f201987b | 600 | configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1); |
46503c2b MR |
601 | resp = SPAPR_DR_CC_RESPONSE_NEXT_CHILD; |
602 | break; | |
603 | case FDT_END_NODE: | |
604 | ccs->fdt_depth--; | |
605 | if (ccs->fdt_depth == 0) { | |
606 | /* done sending the device tree, don't need to track | |
607 | * the state anymore | |
608 | */ | |
609 | drck->set_configured(drc); | |
610 | spapr_ccs_remove(spapr, ccs); | |
611 | ccs = NULL; | |
612 | resp = SPAPR_DR_CC_RESPONSE_SUCCESS; | |
613 | } else { | |
614 | resp = SPAPR_DR_CC_RESPONSE_PREV_PARENT; | |
615 | } | |
616 | break; | |
617 | case FDT_PROP: | |
618 | prop = fdt_get_property_by_offset(fdt, ccs->fdt_offset, | |
619 | &prop_len); | |
620 | name = fdt_string(fdt, fdt32_to_cpu(prop->nameoff)); | |
621 | ||
622 | /* provide the name of the next OF property */ | |
623 | wa_offset = CC_VAL_DATA_OFFSET; | |
624 | rtas_st(wa_addr, CC_IDX_PROP_NAME_OFFSET, wa_offset); | |
f201987b | 625 | configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1); |
46503c2b MR |
626 | |
627 | /* provide the length and value of the OF property. data gets | |
628 | * placed immediately after NULL terminator of the OF property's | |
629 | * name string | |
630 | */ | |
631 | wa_offset += strlen(name) + 1, | |
632 | rtas_st(wa_addr, CC_IDX_PROP_LEN, prop_len); | |
633 | rtas_st(wa_addr, CC_IDX_PROP_DATA_OFFSET, wa_offset); | |
f201987b | 634 | configure_connector_st(wa_addr, wa_offset, prop->data, prop_len); |
46503c2b MR |
635 | resp = SPAPR_DR_CC_RESPONSE_NEXT_PROPERTY; |
636 | break; | |
637 | case FDT_END: | |
638 | resp = SPAPR_DR_CC_RESPONSE_ERROR; | |
639 | default: | |
640 | /* keep seeking for an actionable tag */ | |
641 | break; | |
642 | } | |
643 | if (ccs) { | |
644 | ccs->fdt_offset = fdt_offset_next; | |
645 | } | |
646 | } while (resp == SPAPR_DR_CC_RESPONSE_CONTINUE); | |
647 | ||
648 | rc = resp; | |
649 | out: | |
650 | rtas_st(rets, 0, rc); | |
651 | } | |
652 | ||
39ac8455 DG |
653 | static struct rtas_call { |
654 | const char *name; | |
655 | spapr_rtas_fn fn; | |
3a3b8502 | 656 | } rtas_table[RTAS_TOKEN_MAX - RTAS_TOKEN_BASE]; |
39ac8455 | 657 | |
28e02042 | 658 | target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
39ac8455 DG |
659 | uint32_t token, uint32_t nargs, target_ulong args, |
660 | uint32_t nret, target_ulong rets) | |
661 | { | |
3a3b8502 AK |
662 | if ((token >= RTAS_TOKEN_BASE) && (token < RTAS_TOKEN_MAX)) { |
663 | struct rtas_call *call = rtas_table + (token - RTAS_TOKEN_BASE); | |
39ac8455 DG |
664 | |
665 | if (call->fn) { | |
210b580b | 666 | call->fn(cpu, spapr, token, nargs, args, nret, rets); |
39ac8455 DG |
667 | return H_SUCCESS; |
668 | } | |
669 | } | |
670 | ||
821303f5 DG |
671 | /* HACK: Some Linux early debug code uses RTAS display-character, |
672 | * but assumes the token value is 0xa (which it is on some real | |
673 | * machines) without looking it up in the device tree. This | |
674 | * special case makes this work */ | |
675 | if (token == 0xa) { | |
210b580b | 676 | rtas_display_character(cpu, spapr, 0xa, nargs, args, nret, rets); |
821303f5 DG |
677 | return H_SUCCESS; |
678 | } | |
679 | ||
39ac8455 | 680 | hcall_dprintf("Unknown RTAS token 0x%x\n", token); |
a64d325d | 681 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
39ac8455 DG |
682 | return H_PARAMETER; |
683 | } | |
684 | ||
eeddd59f LV |
685 | uint64_t qtest_rtas_call(char *cmd, uint32_t nargs, uint64_t args, |
686 | uint32_t nret, uint64_t rets) | |
687 | { | |
688 | int token; | |
689 | ||
690 | for (token = 0; token < RTAS_TOKEN_MAX - RTAS_TOKEN_BASE; token++) { | |
691 | if (strcmp(cmd, rtas_table[token].name) == 0) { | |
692 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); | |
693 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); | |
694 | ||
695 | rtas_table[token].fn(cpu, spapr, token + RTAS_TOKEN_BASE, | |
696 | nargs, args, nret, rets); | |
697 | return H_SUCCESS; | |
698 | } | |
699 | } | |
700 | return H_PARAMETER; | |
701 | } | |
702 | ||
3a3b8502 | 703 | void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn) |
39ac8455 | 704 | { |
adf9ac50 | 705 | assert((token >= RTAS_TOKEN_BASE) && (token < RTAS_TOKEN_MAX)); |
c89d5299 | 706 | |
3a3b8502 | 707 | token -= RTAS_TOKEN_BASE; |
adf9ac50 DG |
708 | |
709 | assert(!rtas_table[token].name); | |
39ac8455 | 710 | |
3a3b8502 AK |
711 | rtas_table[token].name = name; |
712 | rtas_table[token].fn = fn; | |
39ac8455 DG |
713 | } |
714 | ||
3f5dabce | 715 | void spapr_dt_rtas_tokens(void *fdt, int rtas) |
39ac8455 | 716 | { |
39ac8455 DG |
717 | int i; |
718 | ||
3a3b8502 | 719 | for (i = 0; i < RTAS_TOKEN_MAX - RTAS_TOKEN_BASE; i++) { |
39ac8455 DG |
720 | struct rtas_call *call = &rtas_table[i]; |
721 | ||
d36b66f7 | 722 | if (!call->name) { |
39ac8455 DG |
723 | continue; |
724 | } | |
725 | ||
3f5dabce | 726 | _FDT(fdt_setprop_cell(fdt, rtas, call->name, i + RTAS_TOKEN_BASE)); |
39ac8455 | 727 | } |
39ac8455 | 728 | } |
821303f5 | 729 | |
2cac78c1 DG |
730 | void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr) |
731 | { | |
732 | int rtas_node; | |
733 | int ret; | |
734 | ||
735 | /* Copy RTAS blob into guest RAM */ | |
736 | cpu_physical_memory_write(addr, spapr->rtas_blob, spapr->rtas_size); | |
737 | ||
738 | ret = fdt_add_mem_rsv(fdt, addr, spapr->rtas_size); | |
739 | if (ret < 0) { | |
740 | error_report("Couldn't add RTAS reserve entry: %s", | |
741 | fdt_strerror(ret)); | |
742 | exit(1); | |
743 | } | |
744 | ||
745 | /* Update the device tree with the blob's location */ | |
746 | rtas_node = fdt_path_offset(fdt, "/rtas"); | |
747 | assert(rtas_node >= 0); | |
748 | ||
749 | ret = fdt_setprop_cell(fdt, rtas_node, "linux,rtas-base", addr); | |
750 | if (ret < 0) { | |
751 | error_report("Couldn't add linux,rtas-base property: %s", | |
752 | fdt_strerror(ret)); | |
753 | exit(1); | |
754 | } | |
755 | ||
756 | ret = fdt_setprop_cell(fdt, rtas_node, "linux,rtas-entry", addr); | |
757 | if (ret < 0) { | |
758 | error_report("Couldn't add linux,rtas-entry property: %s", | |
759 | fdt_strerror(ret)); | |
760 | exit(1); | |
761 | } | |
762 | ||
763 | ret = fdt_setprop_cell(fdt, rtas_node, "rtas-size", spapr->rtas_size); | |
764 | if (ret < 0) { | |
765 | error_report("Couldn't add rtas-size property: %s", | |
766 | fdt_strerror(ret)); | |
767 | exit(1); | |
768 | } | |
769 | } | |
770 | ||
83f7d43a | 771 | static void core_rtas_register_types(void) |
821303f5 | 772 | { |
3a3b8502 AK |
773 | spapr_rtas_register(RTAS_DISPLAY_CHARACTER, "display-character", |
774 | rtas_display_character); | |
3a3b8502 AK |
775 | spapr_rtas_register(RTAS_POWER_OFF, "power-off", rtas_power_off); |
776 | spapr_rtas_register(RTAS_SYSTEM_REBOOT, "system-reboot", | |
777 | rtas_system_reboot); | |
778 | spapr_rtas_register(RTAS_QUERY_CPU_STOPPED_STATE, "query-cpu-stopped-state", | |
a9f8ad8f | 779 | rtas_query_cpu_stopped_state); |
3a3b8502 AK |
780 | spapr_rtas_register(RTAS_START_CPU, "start-cpu", rtas_start_cpu); |
781 | spapr_rtas_register(RTAS_STOP_SELF, "stop-self", rtas_stop_self); | |
782 | spapr_rtas_register(RTAS_IBM_GET_SYSTEM_PARAMETER, | |
783 | "ibm,get-system-parameter", | |
3ada6b11 | 784 | rtas_ibm_get_system_parameter); |
3a3b8502 AK |
785 | spapr_rtas_register(RTAS_IBM_SET_SYSTEM_PARAMETER, |
786 | "ibm,set-system-parameter", | |
3ada6b11 | 787 | rtas_ibm_set_system_parameter); |
2e14072f ND |
788 | spapr_rtas_register(RTAS_IBM_OS_TERM, "ibm,os-term", |
789 | rtas_ibm_os_term); | |
094d2058 NF |
790 | spapr_rtas_register(RTAS_SET_POWER_LEVEL, "set-power-level", |
791 | rtas_set_power_level); | |
792 | spapr_rtas_register(RTAS_GET_POWER_LEVEL, "get-power-level", | |
793 | rtas_get_power_level); | |
8c8639df MD |
794 | spapr_rtas_register(RTAS_SET_INDICATOR, "set-indicator", |
795 | rtas_set_indicator); | |
886445a6 MD |
796 | spapr_rtas_register(RTAS_GET_SENSOR_STATE, "get-sensor-state", |
797 | rtas_get_sensor_state); | |
46503c2b MR |
798 | spapr_rtas_register(RTAS_IBM_CONFIGURE_CONNECTOR, "ibm,configure-connector", |
799 | rtas_ibm_configure_connector); | |
821303f5 | 800 | } |
83f7d43a AF |
801 | |
802 | type_init(core_rtas_register_types) |