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9ee6e8bb PB |
1 | /* |
2 | * ARM RealView Emulation Baseboard Interrupt Controller | |
3 | * | |
4 | * Copyright (c) 2006-2007 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
7 | * This code is licenced under the GPL. | |
8 | */ | |
9 | ||
fe7e8758 | 10 | #include "sysbus.h" |
9ee6e8bb PB |
11 | |
12 | #define GIC_NIRQ 96 | |
13 | #define NCPU 1 | |
14 | ||
15 | /* Only a single "CPU" interface is present. */ | |
16 | static inline int | |
17 | gic_get_current_cpu(void) | |
18 | { | |
19 | return 0; | |
20 | } | |
21 | ||
22 | #include "arm_gic.c" | |
23 | ||
fe7e8758 PB |
24 | typedef struct { |
25 | gic_state gic; | |
26 | int iomemtype; | |
27 | } RealViewGICState; | |
28 | ||
c227f099 | 29 | static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset) |
9ee6e8bb PB |
30 | { |
31 | gic_state *s = (gic_state *)opaque; | |
9ee6e8bb PB |
32 | return gic_cpu_read(s, gic_get_current_cpu(), offset); |
33 | } | |
34 | ||
c227f099 | 35 | static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset, |
9ee6e8bb PB |
36 | uint32_t value) |
37 | { | |
38 | gic_state *s = (gic_state *)opaque; | |
9ee6e8bb PB |
39 | gic_cpu_write(s, gic_get_current_cpu(), offset, value); |
40 | } | |
41 | ||
d60efc6b | 42 | static CPUReadMemoryFunc * const realview_gic_cpu_readfn[] = { |
9ee6e8bb PB |
43 | realview_gic_cpu_read, |
44 | realview_gic_cpu_read, | |
45 | realview_gic_cpu_read | |
46 | }; | |
47 | ||
d60efc6b | 48 | static CPUWriteMemoryFunc * const realview_gic_cpu_writefn[] = { |
9ee6e8bb PB |
49 | realview_gic_cpu_write, |
50 | realview_gic_cpu_write, | |
51 | realview_gic_cpu_write | |
52 | }; | |
53 | ||
c227f099 | 54 | static void realview_gic_map(SysBusDevice *dev, target_phys_addr_t base) |
9ee6e8bb | 55 | { |
fe7e8758 PB |
56 | RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev); |
57 | cpu_register_physical_memory(base, 0x1000, s->iomemtype); | |
58 | cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype); | |
59 | } | |
60 | ||
81a322d4 | 61 | static int realview_gic_init(SysBusDevice *dev) |
fe7e8758 PB |
62 | { |
63 | RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev); | |
9ee6e8bb | 64 | |
fe7e8758 | 65 | gic_init(&s->gic); |
1eed09cb | 66 | s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn, |
fe7e8758 PB |
67 | realview_gic_cpu_writefn, s); |
68 | sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map); | |
81a322d4 | 69 | return 0; |
9ee6e8bb | 70 | } |
fe7e8758 PB |
71 | |
72 | static void realview_gic_register_devices(void) | |
73 | { | |
74 | sysbus_register_dev("realview_gic", sizeof(RealViewGICState), | |
75 | realview_gic_init); | |
76 | } | |
77 | ||
78 | device_init(realview_gic_register_devices) |