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Merge branch 'eflags3' of git://github.com/rth7680/qemu
[qemu.git] / hw / omap_dma.c
CommitLineData
b4e3104b
AZ		 1/*
2 * TI OMAP DMA gigacell.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <[email protected]>
5 * Copyright (C) 2007-2008 Lauro Ramos Venancio <[email protected]>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
fad6cb1a 17 * You should have received a copy of the GNU General Public License along
8167ee88 18 * with this program; if not, see <http://www.gnu.org/licenses/>.
b4e3104b
AZ		 19 */
20#include "qemu-common.h"
1de7afc9 21#include "qemu/timer.h"
b4e3104b
AZ		 22#include "omap.h"
23#include "irq.h"
afbb5194 24#include "soc_dma.h"
b4e3104b
AZ		 25
26struct omap_dma_channel_s {
27 /* transfer data */
28 int burst[2];
29 int pack[2];
827df9f3
AZ		 30 int endian[2];
31 int endian_lock[2];
32 int translate[2];
b4e3104b 33 enum omap_dma_port port[2];
a8170e5e 34 hwaddr addr[2];
c227f099 35 omap_dma_addressing_t mode[2];
827df9f3 36 uint32_t elements;
b4e3104b 37 uint16_t frames;
827df9f3 38 int32_t frame_index[2];
b4e3104b
AZ		 39 int16_t element_index[2];
40 int data_type;
41
42 /* transfer type */
43 int transparent_copy;
44 int constant_fill;
45 uint32_t color;
827df9f3 46 int prefetch;
b4e3104b
AZ		 47
48 /* auto init and linked channel data */
49 int end_prog;
50 int repeat;
51 int auto_init;
52 int link_enabled;
53 int link_next_ch;
54
55 /* interruption data */
56 int interrupts;
57 int status;
827df9f3 58 int cstatus;
b4e3104b
AZ		 59
60 /* state data */
61 int active;
62 int enable;
63 int sync;
827df9f3 64 int src_sync;
b4e3104b
AZ		 65 int pending_request;
66 int waiting_end_prog;
67 uint16_t cpc;
afbb5194 68 int set_update;
b4e3104b
AZ		 69
70 /* sync type */
71 int fs;
72 int bs;
73
74 /* compatibility */
75 int omap_3_1_compatible_disable;
76
77 qemu_irq irq;
78 struct omap_dma_channel_s *sibling;
79
80 struct omap_dma_reg_set_s {
a8170e5e 81 hwaddr src, dest;
b4e3104b
AZ		 82 int frame;
83 int element;
827df9f3 84 int pck_element;
b4e3104b
AZ		 85 int frame_delta[2];
86 int elem_delta[2];
87 int frames;
88 int elements;
827df9f3 89 int pck_elements;
b4e3104b
AZ		 90 } active_set;
91
afbb5194
AZ		 92 struct soc_dma_ch_s *dma;
93
b4e3104b 94 /* unused parameters */
827df9f3 95 int write_mode;
b4e3104b
AZ		 96 int priority;
97 int interleave_disabled;
98 int type;
827df9f3
AZ		 99 int suspend;
100 int buf_disable;
b4e3104b
AZ		 101};
102
103struct omap_dma_s {
afbb5194 104 struct soc_dma_s *dma;
7405165e 105 MemoryRegion iomem;
afbb5194 106
b4e3104b 107 struct omap_mpu_state_s *mpu;
b4e3104b 108 omap_clk clk;
827df9f3
AZ		 109 qemu_irq irq[4];
110 void (*intr_update)(struct omap_dma_s *s);
b4e3104b
AZ		 111 enum omap_dma_model model;
112 int omap_3_1_mapping_disabled;
113
827df9f3
AZ		 114 uint32_t gcr;
115 uint32_t ocp;
116 uint32_t caps[5];
117 uint32_t irqen[4];
118 uint32_t irqstat[4];
b4e3104b
AZ		 119
120 int chans;
827df9f3 121 struct omap_dma_channel_s ch[32];
b4e3104b
AZ		 122 struct omap_dma_lcd_channel_s lcd_ch;
123};
124
125/* Interrupts */
126#define TIMEOUT_INTR (1 << 0)
127#define EVENT_DROP_INTR (1 << 1)
128#define HALF_FRAME_INTR (1 << 2)
129#define END_FRAME_INTR (1 << 3)
130#define LAST_FRAME_INTR (1 << 4)
131#define END_BLOCK_INTR (1 << 5)
132#define SYNC (1 << 6)
827df9f3
AZ		 133#define END_PKT_INTR (1 << 7)
134#define TRANS_ERR_INTR (1 << 8)
135#define MISALIGN_INTR (1 << 11)
b4e3104b 136
827df9f3 137static inline void omap_dma_interrupts_update(struct omap_dma_s *s)
b4e3104b 138{
827df9f3 139 return s->intr_update(s);
b4e3104b
AZ		 140}
141
afbb5194 142static void omap_dma_channel_load(struct omap_dma_channel_s *ch)
b4e3104b
AZ		 143{
144 struct omap_dma_reg_set_s *a = &ch->active_set;
afbb5194 145 int i, normal;
b4e3104b
AZ		 146 int omap_3_1 = !ch->omap_3_1_compatible_disable;
147
148 /*
149 * TODO: verify address ranges and alignment
150 * TODO: port endianness
151 */
152
153 a->src = ch->addr[0];
154 a->dest = ch->addr[1];
155 a->frames = ch->frames;
156 a->elements = ch->elements;
827df9f3 157 a->pck_elements = ch->frame_index[!ch->src_sync];
b4e3104b
AZ		 158 a->frame = 0;
159 a->element = 0;
827df9f3 160 a->pck_element = 0;
b4e3104b
AZ		 161
162 if (unlikely(!ch->elements || !ch->frames)) {
163 printf("%s: bad DMA request\n", __FUNCTION__);
164 return;
165 }
166
167 for (i = 0; i < 2; i ++)
168 switch (ch->mode[i]) {
169 case constant:
170 a->elem_delta[i] = 0;
171 a->frame_delta[i] = 0;
172 break;
173 case post_incremented:
174 a->elem_delta[i] = ch->data_type;
175 a->frame_delta[i] = 0;
176 break;
177 case single_index:
178 a->elem_delta[i] = ch->data_type +
179 ch->element_index[omap_3_1 ? 0 : i] - 1;
180 a->frame_delta[i] = 0;
181 break;
182 case double_index:
183 a->elem_delta[i] = ch->data_type +
184 ch->element_index[omap_3_1 ? 0 : i] - 1;
185 a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
186 ch->element_index[omap_3_1 ? 0 : i];
187 break;
188 default:
189 break;
190 }
afbb5194
AZ		 191
192 normal = !ch->transparent_copy && !ch->constant_fill &&
193 /* FIFO is big-endian so either (ch->endian[n] == 1) OR
194 * (ch->endian_lock[n] == 1) mean no endianism conversion. */
195 (ch->endian[0] | ch->endian_lock[0]) ==
196 (ch->endian[1] | ch->endian_lock[1]);
197 for (i = 0; i < 2; i ++) {
198 /* TODO: for a->frame_delta[i] > 0 still use the fast path, just
199 * limit min_elems in omap_dma_transfer_setup to the nearest frame
200 * end. */
201 if (!a->elem_delta[i] && normal &&
202 (a->frames == 1 || !a->frame_delta[i]))
203 ch->dma->type[i] = soc_dma_access_const;
204 else if (a->elem_delta[i] == ch->data_type && normal &&
205 (a->frames == 1 || !a->frame_delta[i]))
206 ch->dma->type[i] = soc_dma_access_linear;
207 else
208 ch->dma->type[i] = soc_dma_access_other;
209
210 ch->dma->vaddr[i] = ch->addr[i];
211 }
212 soc_dma_ch_update(ch->dma);
b4e3104b
AZ		 213}
214
215static void omap_dma_activate_channel(struct omap_dma_s *s,
216 struct omap_dma_channel_s *ch)
217{
218 if (!ch->active) {
afbb5194
AZ		 219 if (ch->set_update) {
220 /* It's not clear when the active set is supposed to be
221 * loaded from registers. We're already loading it when the
222 * channel is enabled, and for some guests this is not enough
223 * but that may be also because of a race condition (no
224 * delays in qemu) in the guest code, which we're just
225 * working around here. */
226 omap_dma_channel_load(ch);
227 ch->set_update = 0;
228 }
229
b4e3104b 230 ch->active = 1;
afbb5194 231 soc_dma_set_request(ch->dma, 1);
b4e3104b
AZ		 232 if (ch->sync)
233 ch->status |= SYNC;
b4e3104b 234 }
b4e3104b
AZ		 235}
236
237static void omap_dma_deactivate_channel(struct omap_dma_s *s,
238 struct omap_dma_channel_s *ch)
239{
240 /* Update cpc */
241 ch->cpc = ch->active_set.dest & 0xffff;
242
827df9f3 243 if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {
b4e3104b
AZ		 244 /* Don't deactivate the channel */
245 ch->pending_request = 0;
827df9f3 246 return;
b4e3104b
AZ		 247 }
248
249 /* Don't deactive the channel if it is synchronized and the DMA request is
250 active */
afbb5194 251 if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync)))
b4e3104b
AZ		 252 return;
253
254 if (ch->active) {
255 ch->active = 0;
256 ch->status &= ~SYNC;
afbb5194 257 soc_dma_set_request(ch->dma, 0);
b4e3104b 258 }
b4e3104b
AZ		 259}
260
261static void omap_dma_enable_channel(struct omap_dma_s *s,
262 struct omap_dma_channel_s *ch)
263{
264 if (!ch->enable) {
265 ch->enable = 1;
266 ch->waiting_end_prog = 0;
afbb5194 267 omap_dma_channel_load(ch);
827df9f3 268 /* TODO: theoretically if ch->sync && ch->prefetch &&
afbb5194
AZ		 269 * !s->dma->drqbmp[ch->sync], we should also activate and fetch
270 * from source and then stall until signalled. */
271 if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync)))
b4e3104b
AZ		 272 omap_dma_activate_channel(s, ch);
273 }
274}
275
276static void omap_dma_disable_channel(struct omap_dma_s *s,
277 struct omap_dma_channel_s *ch)
278{
279 if (ch->enable) {
280 ch->enable = 0;
281 /* Discard any pending request */
282 ch->pending_request = 0;
283 omap_dma_deactivate_channel(s, ch);
284 }
285}
286
287static void omap_dma_channel_end_prog(struct omap_dma_s *s,
288 struct omap_dma_channel_s *ch)
289{
290 if (ch->waiting_end_prog) {
291 ch->waiting_end_prog = 0;
292 if (!ch->sync || ch->pending_request) {
293 ch->pending_request = 0;
294 omap_dma_activate_channel(s, ch);
295 }
296 }
297}
298
827df9f3
AZ		 299static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s)
300{
301 struct omap_dma_channel_s *ch = s->ch;
302
303 /* First three interrupts are shared between two channels each. */
304 if (ch[0].status | ch[6].status)
305 qemu_irq_raise(ch[0].irq);
306 if (ch[1].status | ch[7].status)
307 qemu_irq_raise(ch[1].irq);
308 if (ch[2].status | ch[8].status)
309 qemu_irq_raise(ch[2].irq);
310 if (ch[3].status)
311 qemu_irq_raise(ch[3].irq);
312 if (ch[4].status)
313 qemu_irq_raise(ch[4].irq);
314 if (ch[5].status)
315 qemu_irq_raise(ch[5].irq);
316}
317
318static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s)
319{
320 struct omap_dma_channel_s *ch = s->ch;
321 int i;
322
323 for (i = s->chans; i; ch ++, i --)
324 if (ch->status)
325 qemu_irq_raise(ch->irq);
326}
327
b4e3104b
AZ		 328static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)
329{
330 s->omap_3_1_mapping_disabled = 0;
331 s->chans = 9;
827df9f3 332 s->intr_update = omap_dma_interrupts_3_1_update;
b4e3104b
AZ		 333}
334
335static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s)
336{
337 s->omap_3_1_mapping_disabled = 1;
338 s->chans = 16;
827df9f3 339 s->intr_update = omap_dma_interrupts_3_2_update;
b4e3104b
AZ		 340}
341
342static void omap_dma_process_request(struct omap_dma_s *s, int request)
343{
344 int channel;
345 int drop_event = 0;
346 struct omap_dma_channel_s *ch = s->ch;
347
348 for (channel = 0; channel < s->chans; channel ++, ch ++) {
349 if (ch->enable && ch->sync == request) {
350 if (!ch->active)
351 omap_dma_activate_channel(s, ch);
352 else if (!ch->pending_request)
353 ch->pending_request = 1;
354 else {
355 /* Request collision */
356 /* Second request received while processing other request */
357 ch->status |= EVENT_DROP_INTR;
358 drop_event = 1;
359 }
360 }
361 }
362
363 if (drop_event)
364 omap_dma_interrupts_update(s);
365}
366
afbb5194 367static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma)
b4e3104b 368{
b4e3104b 369 uint8_t value[4];
afbb5194
AZ		 370 struct omap_dma_channel_s *ch = dma->opaque;
371 struct omap_dma_reg_set_s *a = &ch->active_set;
372 int bytes = dma->bytes;
373#ifdef MULTI_REQ
374 uint16_t status = ch->status;
375#endif
b4e3104b 376
afbb5194
AZ		 377 do {
378 /* Transfer a single element */
379 /* FIXME: check the endianness */
380 if (!ch->constant_fill)
381 cpu_physical_memory_read(a->src, value, ch->data_type);
382 else
383 *(uint32_t *) value = ch->color;
384
385 if (!ch->transparent_copy || *(uint32_t *) value != ch->color)
386 cpu_physical_memory_write(a->dest, value, ch->data_type);
387
388 a->src += a->elem_delta[0];
389 a->dest += a->elem_delta[1];
390 a->element ++;
391
392#ifndef MULTI_REQ
393 if (a->element == a->elements) {
394 /* End of Frame */
395 a->element = 0;
396 a->src += a->frame_delta[0];
397 a->dest += a->frame_delta[1];
398 a->frame ++;
399
400 /* If the channel is async, update cpc */
401 if (!ch->sync)
402 ch->cpc = a->dest & 0xffff;
403 }
404 } while ((bytes -= ch->data_type));
405#else
406 /* If the channel is element synchronized, deactivate it */
407 if (ch->sync && !ch->fs && !ch->bs)
b4e3104b 408 omap_dma_deactivate_channel(s, ch);
afbb5194
AZ		 409
410 /* If it is the last frame, set the LAST_FRAME interrupt */
411 if (a->element == 1 && a->frame == a->frames - 1)
412 if (ch->interrupts & LAST_FRAME_INTR)
413 ch->status |= LAST_FRAME_INTR;
414
415 /* If the half of the frame was reached, set the HALF_FRAME
416 interrupt */
417 if (a->element == (a->elements >> 1))
418 if (ch->interrupts & HALF_FRAME_INTR)
419 ch->status |= HALF_FRAME_INTR;
420
421 if (ch->fs && ch->bs) {
422 a->pck_element ++;
423 /* Check if a full packet has beed transferred. */
424 if (a->pck_element == a->pck_elements) {
425 a->pck_element = 0;
426
427 /* Set the END_PKT interrupt */
428 if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync)
429 ch->status |= END_PKT_INTR;
430
431 /* If the channel is packet-synchronized, deactivate it */
432 if (ch->sync)
433 omap_dma_deactivate_channel(s, ch);
434 }
b4e3104b
AZ		 435 }
436
afbb5194
AZ		 437 if (a->element == a->elements) {
438 /* End of Frame */
439 a->element = 0;
440 a->src += a->frame_delta[0];
441 a->dest += a->frame_delta[1];
442 a->frame ++;
443
444 /* If the channel is frame synchronized, deactivate it */
445 if (ch->sync && ch->fs && !ch->bs)
b4e3104b
AZ		 446 omap_dma_deactivate_channel(s, ch);
447
afbb5194
AZ		 448 /* If the channel is async, update cpc */
449 if (!ch->sync)
450 ch->cpc = a->dest & 0xffff;
451
452 /* Set the END_FRAME interrupt */
453 if (ch->interrupts & END_FRAME_INTR)
454 ch->status |= END_FRAME_INTR;
455
456 if (a->frame == a->frames) {
457 /* End of Block */
458 /* Disable the channel */
459
460 if (ch->omap_3_1_compatible_disable) {
461 omap_dma_disable_channel(s, ch);
462 if (ch->link_enabled)
463 omap_dma_enable_channel(s,
464 &s->ch[ch->link_next_ch]);
465 } else {
466 if (!ch->auto_init)
467 omap_dma_disable_channel(s, ch);
468 else if (ch->repeat || ch->end_prog)
469 omap_dma_channel_load(ch);
470 else {
471 ch->waiting_end_prog = 1;
827df9f3 472 omap_dma_deactivate_channel(s, ch);
afbb5194 473 }
827df9f3 474 }
afbb5194
AZ		 475
476 if (ch->interrupts & END_BLOCK_INTR)
477 ch->status |= END_BLOCK_INTR;
827df9f3 478 }
afbb5194
AZ		 479 }
480 } while (status == ch->status && ch->active);
827df9f3 481
afbb5194
AZ		 482 omap_dma_interrupts_update(s);
483#endif
484}
b4e3104b 485
afbb5194
AZ		 486enum {
487 omap_dma_intr_element_sync,
488 omap_dma_intr_last_frame,
489 omap_dma_intr_half_frame,
490 omap_dma_intr_frame,
491 omap_dma_intr_frame_sync,
492 omap_dma_intr_packet,
493 omap_dma_intr_packet_sync,
494 omap_dma_intr_block,
495 __omap_dma_intr_last,
496};
b4e3104b 497
afbb5194
AZ		 498static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma)
499{
500 struct omap_dma_port_if_s *src_p, *dest_p;
501 struct omap_dma_reg_set_s *a;
502 struct omap_dma_channel_s *ch = dma->opaque;
503 struct omap_dma_s *s = dma->dma->opaque;
504 int frames, min_elems, elements[__omap_dma_intr_last];
b4e3104b 505
afbb5194 506 a = &ch->active_set;
b4e3104b 507
afbb5194
AZ		 508 src_p = &s->mpu->port[ch->port[0]];
509 dest_p = &s->mpu->port[ch->port[1]];
510 if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
511 (!dest_p->addr_valid(s->mpu, a->dest))) {
512#if 0
513 /* Bus time-out */
514 if (ch->interrupts & TIMEOUT_INTR)
515 ch->status |= TIMEOUT_INTR;
516 omap_dma_deactivate_channel(s, ch);
517 continue;
518#endif
519 printf("%s: Bus time-out in DMA%i operation\n",
520 __FUNCTION__, dma->num);
521 }
b4e3104b 522
afbb5194
AZ		 523 min_elems = INT_MAX;
524
525 /* Check all the conditions that terminate the transfer starting
526 * with those that can occur the soonest. */
527#define INTR_CHECK(cond, id, nelements) \
528 if (cond) { \
529 elements[id] = nelements; \
530 if (elements[id] < min_elems) \
531 min_elems = elements[id]; \
532 } else \
533 elements[id] = INT_MAX;
534
535 /* Elements */
536 INTR_CHECK(
537 ch->sync && !ch->fs && !ch->bs,
538 omap_dma_intr_element_sync,
539 1)
540
541 /* Frames */
542 /* TODO: for transfers where entire frames can be read and written
543 * using memcpy() but a->frame_delta is non-zero, try to still do
544 * transfers using soc_dma but limit min_elems to a->elements - ...
545 * See also the TODO in omap_dma_channel_load. */
546 INTR_CHECK(
547 (ch->interrupts & LAST_FRAME_INTR) &&
548 ((a->frame < a->frames - 1) || !a->element),
549 omap_dma_intr_last_frame,
550 (a->frames - a->frame - 2) * a->elements +
551 (a->elements - a->element + 1))
552 INTR_CHECK(
553 ch->interrupts & HALF_FRAME_INTR,
554 omap_dma_intr_half_frame,
555 (a->elements >> 1) +
556 (a->element >= (a->elements >> 1) ? a->elements : 0) -
557 a->element)
558 INTR_CHECK(
559 ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR),
560 omap_dma_intr_frame,
561 a->elements - a->element)
562 INTR_CHECK(
563 ch->sync && ch->fs && !ch->bs,
564 omap_dma_intr_frame_sync,
565 a->elements - a->element)
566
567 /* Packets */
568 INTR_CHECK(
569 ch->fs && ch->bs &&
570 (ch->interrupts & END_PKT_INTR) && !ch->src_sync,
571 omap_dma_intr_packet,
572 a->pck_elements - a->pck_element)
573 INTR_CHECK(
574 ch->fs && ch->bs && ch->sync,
575 omap_dma_intr_packet_sync,
576 a->pck_elements - a->pck_element)
577
578 /* Blocks */
579 INTR_CHECK(
580 1,
581 omap_dma_intr_block,
582 (a->frames - a->frame - 1) * a->elements +
583 (a->elements - a->element))
584
585 dma->bytes = min_elems * ch->data_type;
586
587 /* Set appropriate interrupts and/or deactivate channels */
588
589#ifdef MULTI_REQ
590 /* TODO: should all of this only be done if dma->update, and otherwise
591 * inside omap_dma_transfer_generic below - check what's faster. */
317b7e67 592 if (dma->update) {
afbb5194 593#endif
b4e3104b 594
317b7e67
MT		 595 /* If the channel is element synchronized, deactivate it */
596 if (min_elems == elements[omap_dma_intr_element_sync])
597 omap_dma_deactivate_channel(s, ch);
afbb5194 598
317b7e67
MT		 599 /* If it is the last frame, set the LAST_FRAME interrupt */
600 if (min_elems == elements[omap_dma_intr_last_frame])
601 ch->status |= LAST_FRAME_INTR;
afbb5194 602
317b7e67
MT		 603 /* If exactly half of the frame was reached, set the HALF_FRAME
604 interrupt */
605 if (min_elems == elements[omap_dma_intr_half_frame])
606 ch->status |= HALF_FRAME_INTR;
afbb5194 607
317b7e67
MT		 608 /* If a full packet has been transferred, set the END_PKT interrupt */
609 if (min_elems == elements[omap_dma_intr_packet])
610 ch->status |= END_PKT_INTR;
afbb5194 611
317b7e67
MT		 612 /* If the channel is packet-synchronized, deactivate it */
613 if (min_elems == elements[omap_dma_intr_packet_sync])
614 omap_dma_deactivate_channel(s, ch);
afbb5194 615
317b7e67
MT		 616 /* If the channel is frame synchronized, deactivate it */
617 if (min_elems == elements[omap_dma_intr_frame_sync])
618 omap_dma_deactivate_channel(s, ch);
afbb5194 619
317b7e67
MT		 620 /* Set the END_FRAME interrupt */
621 if (min_elems == elements[omap_dma_intr_frame])
622 ch->status |= END_FRAME_INTR;
afbb5194 623
317b7e67
MT		 624 if (min_elems == elements[omap_dma_intr_block]) {
625 /* End of Block */
626 /* Disable the channel */
afbb5194 627
317b7e67 628 if (ch->omap_3_1_compatible_disable) {
afbb5194 629 omap_dma_disable_channel(s, ch);
317b7e67
MT		 630 if (ch->link_enabled)
631 omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]);
632 } else {
633 if (!ch->auto_init)
634 omap_dma_disable_channel(s, ch);
635 else if (ch->repeat || ch->end_prog)
636 omap_dma_channel_load(ch);
637 else {
638 ch->waiting_end_prog = 1;
639 omap_dma_deactivate_channel(s, ch);
640 }
b4e3104b 641 }
afbb5194 642
317b7e67
MT		 643 if (ch->interrupts & END_BLOCK_INTR)
644 ch->status |= END_BLOCK_INTR;
645 }
afbb5194 646
317b7e67
MT		 647 /* Update packet number */
648 if (ch->fs && ch->bs) {
649 a->pck_element += min_elems;
650 a->pck_element %= a->pck_elements;
651 }
afbb5194 652
317b7e67
MT		 653 /* TODO: check if we really need to update anything here or perhaps we
654 * can skip part of this. */
afbb5194 655#ifndef MULTI_REQ
317b7e67 656 if (dma->update) {
afbb5194 657#endif
317b7e67 658 a->element += min_elems;
afbb5194 659
317b7e67
MT		 660 frames = a->element / a->elements;
661 a->element = a->element % a->elements;
662 a->frame += frames;
663 a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0];
664 a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1];
afbb5194 665
317b7e67
MT		 666 /* If the channel is async, update cpc */
667 if (!ch->sync && frames)
668 ch->cpc = a->dest & 0xffff;
d4066479 669
317b7e67
MT		 670 /* TODO: if the destination port is IMIF or EMIFF, set the dirty
671 * bits on it. */
f90554ad 672#ifndef MULTI_REQ
317b7e67
MT		 673 }
674#else
b4e3104b 675 }
f90554ad 676#endif
b4e3104b
AZ		 677
678 omap_dma_interrupts_update(s);
b4e3104b
AZ		 679}
680
afbb5194 681void omap_dma_reset(struct soc_dma_s *dma)
b4e3104b
AZ		 682{
683 int i;
afbb5194 684 struct omap_dma_s *s = dma->opaque;
b4e3104b 685
afbb5194 686 soc_dma_reset(s->dma);
827df9f3
AZ		 687 if (s->model < omap_dma_4)
688 s->gcr = 0x0004;
689 else
690 s->gcr = 0x00010010;
691 s->ocp = 0x00000000;
692 memset(&s->irqstat, 0, sizeof(s->irqstat));
693 memset(&s->irqen, 0, sizeof(s->irqen));
b4e3104b
AZ		 694 s->lcd_ch.src = emiff;
695 s->lcd_ch.condition = 0;
696 s->lcd_ch.interrupts = 0;
697 s->lcd_ch.dual = 0;
827df9f3
AZ		 698 if (s->model < omap_dma_4)
699 omap_dma_enable_3_1_mapping(s);
b4e3104b 700 for (i = 0; i < s->chans; i ++) {
827df9f3
AZ		 701 s->ch[i].suspend = 0;
702 s->ch[i].prefetch = 0;
703 s->ch[i].buf_disable = 0;
704 s->ch[i].src_sync = 0;
b4e3104b
AZ		 705 memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
706 memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
707 memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
b4e3104b
AZ		 708 memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
709 memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
827df9f3
AZ		 710 memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian));
711 memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock));
712 memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate));
713 s->ch[i].write_mode = 0;
714 s->ch[i].data_type = 0;
715 s->ch[i].transparent_copy = 0;
716 s->ch[i].constant_fill = 0;
717 s->ch[i].color = 0x00000000;
718 s->ch[i].end_prog = 0;
719 s->ch[i].repeat = 0;
720 s->ch[i].auto_init = 0;
721 s->ch[i].link_enabled = 0;
722 if (s->model < omap_dma_4)
723 s->ch[i].interrupts = 0x0003;
724 else
725 s->ch[i].interrupts = 0x0000;
726 s->ch[i].status = 0;
727 s->ch[i].cstatus = 0;
728 s->ch[i].active = 0;
729 s->ch[i].enable = 0;
730 s->ch[i].sync = 0;
731 s->ch[i].pending_request = 0;
732 s->ch[i].waiting_end_prog = 0;
733 s->ch[i].cpc = 0x0000;
734 s->ch[i].fs = 0;
735 s->ch[i].bs = 0;
736 s->ch[i].omap_3_1_compatible_disable = 0;
b4e3104b 737 memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
827df9f3
AZ		 738 s->ch[i].priority = 0;
739 s->ch[i].interleave_disabled = 0;
740 s->ch[i].type = 0;
b4e3104b
AZ		 741 }
742}
743
744static int omap_dma_ch_reg_read(struct omap_dma_s *s,
745 struct omap_dma_channel_s *ch, int reg, uint16_t *value)
746{
747 switch (reg) {
748 case 0x00: /* SYS_DMA_CSDP_CH0 */
749 *value = (ch->burst[1] << 14) |
750 (ch->pack[1] << 13) |
751 (ch->port[1] << 9) |
752 (ch->burst[0] << 7) |
753 (ch->pack[0] << 6) |
754 (ch->port[0] << 2) |
755 (ch->data_type >> 1);
756 break;
757
758 case 0x02: /* SYS_DMA_CCR_CH0 */
827df9f3 759 if (s->model <= omap_dma_3_1)
b4e3104b
AZ		 760 *value = 0 << 10; /* FIFO_FLUSH reads as 0 */
761 else
762 *value = ch->omap_3_1_compatible_disable << 10;
763 *value |= (ch->mode[1] << 14) |
764 (ch->mode[0] << 12) |
765 (ch->end_prog << 11) |
766 (ch->repeat << 9) |
767 (ch->auto_init << 8) |
768 (ch->enable << 7) |
769 (ch->priority << 6) |
770 (ch->fs << 5) | ch->sync;
771 break;
772
773 case 0x04: /* SYS_DMA_CICR_CH0 */
774 *value = ch->interrupts;
775 break;
776
777 case 0x06: /* SYS_DMA_CSR_CH0 */
778 *value = ch->status;
779 ch->status &= SYNC;
780 if (!ch->omap_3_1_compatible_disable && ch->sibling) {
781 *value |= (ch->sibling->status & 0x3f) << 6;
782 ch->sibling->status &= SYNC;
783 }
784 qemu_irq_lower(ch->irq);
785 break;
786
787 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
788 *value = ch->addr[0] & 0x0000ffff;
789 break;
790
791 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
792 *value = ch->addr[0] >> 16;
793 break;
794
795 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
796 *value = ch->addr[1] & 0x0000ffff;
797 break;
798
799 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
800 *value = ch->addr[1] >> 16;
801 break;
802
803 case 0x10: /* SYS_DMA_CEN_CH0 */
804 *value = ch->elements;
805 break;
806
807 case 0x12: /* SYS_DMA_CFN_CH0 */
808 *value = ch->frames;
809 break;
810
811 case 0x14: /* SYS_DMA_CFI_CH0 */
812 *value = ch->frame_index[0];
813 break;
814
815 case 0x16: /* SYS_DMA_CEI_CH0 */
816 *value = ch->element_index[0];
817 break;
818
819 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
820 if (ch->omap_3_1_compatible_disable)
821 *value = ch->active_set.src & 0xffff; /* CSAC */
822 else
823 *value = ch->cpc;
824 break;
825
826 case 0x1a: /* DMA_CDAC */
827 *value = ch->active_set.dest & 0xffff; /* CDAC */
828 break;
829
830 case 0x1c: /* DMA_CDEI */
831 *value = ch->element_index[1];
832 break;
833
834 case 0x1e: /* DMA_CDFI */
835 *value = ch->frame_index[1];
836 break;
837
838 case 0x20: /* DMA_COLOR_L */
839 *value = ch->color & 0xffff;
840 break;
841
842 case 0x22: /* DMA_COLOR_U */
843 *value = ch->color >> 16;
844 break;
845
846 case 0x24: /* DMA_CCR2 */
847 *value = (ch->bs << 2) |
848 (ch->transparent_copy << 1) |
849 ch->constant_fill;
850 break;
851
852 case 0x28: /* DMA_CLNK_CTRL */
853 *value = (ch->link_enabled << 15) |
854 (ch->link_next_ch & 0xf);
855 break;
856
857 case 0x2a: /* DMA_LCH_CTRL */
858 *value = (ch->interleave_disabled << 15) |
859 ch->type;
860 break;
861
862 default:
863 return 1;
864 }
865 return 0;
866}
867
868static int omap_dma_ch_reg_write(struct omap_dma_s *s,
869 struct omap_dma_channel_s *ch, int reg, uint16_t value)
870{
871 switch (reg) {
872 case 0x00: /* SYS_DMA_CSDP_CH0 */
873 ch->burst[1] = (value & 0xc000) >> 14;
874 ch->pack[1] = (value & 0x2000) >> 13;
875 ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
876 ch->burst[0] = (value & 0x0180) >> 7;
877 ch->pack[0] = (value & 0x0040) >> 6;
878 ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
827df9f3
AZ		 879 ch->data_type = 1 << (value & 3);
880 if (ch->port[0] >= __omap_dma_port_last)
b4e3104b
AZ		 881 printf("%s: invalid DMA port %i\n", __FUNCTION__,
882 ch->port[0]);
827df9f3 883 if (ch->port[1] >= __omap_dma_port_last)
b4e3104b
AZ		 884 printf("%s: invalid DMA port %i\n", __FUNCTION__,
885 ch->port[1]);
886 if ((value & 3) == 3)
887 printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
888 break;
889
890 case 0x02: /* SYS_DMA_CCR_CH0 */
c227f099
AL		 891 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
892 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
b4e3104b 893 ch->end_prog = (value & 0x0800) >> 11;
827df9f3 894 if (s->model >= omap_dma_3_2)
b4e3104b
AZ		 895 ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
896 ch->repeat = (value & 0x0200) >> 9;
897 ch->auto_init = (value & 0x0100) >> 8;
898 ch->priority = (value & 0x0040) >> 6;
899 ch->fs = (value & 0x0020) >> 5;
900 ch->sync = value & 0x001f;
901
902 if (value & 0x0080)
903 omap_dma_enable_channel(s, ch);
904 else
905 omap_dma_disable_channel(s, ch);
906
907 if (ch->end_prog)
908 omap_dma_channel_end_prog(s, ch);
909
910 break;
911
912 case 0x04: /* SYS_DMA_CICR_CH0 */
827df9f3 913 ch->interrupts = value & 0x3f;
b4e3104b
AZ		 914 break;
915
916 case 0x06: /* SYS_DMA_CSR_CH0 */
a8170e5e 917 OMAP_RO_REG((hwaddr) reg);
b4e3104b
AZ		 918 break;
919
920 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
921 ch->addr[0] &= 0xffff0000;
922 ch->addr[0] |= value;
923 break;
924
925 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
926 ch->addr[0] &= 0x0000ffff;
927 ch->addr[0] |= (uint32_t) value << 16;
928 break;
929
930 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
931 ch->addr[1] &= 0xffff0000;
932 ch->addr[1] |= value;
933 break;
934
935 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
936 ch->addr[1] &= 0x0000ffff;
937 ch->addr[1] |= (uint32_t) value << 16;
938 break;
939
940 case 0x10: /* SYS_DMA_CEN_CH0 */
941 ch->elements = value;
942 break;
943
944 case 0x12: /* SYS_DMA_CFN_CH0 */
945 ch->frames = value;
946 break;
947
948 case 0x14: /* SYS_DMA_CFI_CH0 */
949 ch->frame_index[0] = (int16_t) value;
950 break;
951
952 case 0x16: /* SYS_DMA_CEI_CH0 */
953 ch->element_index[0] = (int16_t) value;
954 break;
955
956 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
a8170e5e 957 OMAP_RO_REG((hwaddr) reg);
b4e3104b
AZ		 958 break;
959
960 case 0x1c: /* DMA_CDEI */
961 ch->element_index[1] = (int16_t) value;
962 break;
963
964 case 0x1e: /* DMA_CDFI */
965 ch->frame_index[1] = (int16_t) value;
966 break;
967
968 case 0x20: /* DMA_COLOR_L */
969 ch->color &= 0xffff0000;
970 ch->color |= value;
971 break;
972
973 case 0x22: /* DMA_COLOR_U */
974 ch->color &= 0xffff;
975 ch->color |= value << 16;
976 break;
977
978 case 0x24: /* DMA_CCR2 */
827df9f3 979 ch->bs = (value >> 2) & 0x1;
b4e3104b
AZ		 980 ch->transparent_copy = (value >> 1) & 0x1;
981 ch->constant_fill = value & 0x1;
982 break;
983
984 case 0x28: /* DMA_CLNK_CTRL */
985 ch->link_enabled = (value >> 15) & 0x1;
986 if (value & (1 << 14)) { /* Stop_Lnk */
987 ch->link_enabled = 0;
988 omap_dma_disable_channel(s, ch);
989 }
990 ch->link_next_ch = value & 0x1f;
991 break;
992
993 case 0x2a: /* DMA_LCH_CTRL */
994 ch->interleave_disabled = (value >> 15) & 0x1;
995 ch->type = value & 0xf;
996 break;
997
998 default:
999 return 1;
1000 }
1001 return 0;
1002}
1003
1004static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1005 uint16_t value)
1006{
1007 switch (offset) {
1008 case 0xbc0: /* DMA_LCD_CSDP */
1009 s->brust_f2 = (value >> 14) & 0x3;
1010 s->pack_f2 = (value >> 13) & 0x1;
1011 s->data_type_f2 = (1 << ((value >> 11) & 0x3));
1012 s->brust_f1 = (value >> 7) & 0x3;
1013 s->pack_f1 = (value >> 6) & 0x1;
1014 s->data_type_f1 = (1 << ((value >> 0) & 0x3));
1015 break;
1016
1017 case 0xbc2: /* DMA_LCD_CCR */
1018 s->mode_f2 = (value >> 14) & 0x3;
1019 s->mode_f1 = (value >> 12) & 0x3;
1020 s->end_prog = (value >> 11) & 0x1;
1021 s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
1022 s->repeat = (value >> 9) & 0x1;
1023 s->auto_init = (value >> 8) & 0x1;
1024 s->running = (value >> 7) & 0x1;
1025 s->priority = (value >> 6) & 0x1;
1026 s->bs = (value >> 4) & 0x1;
1027 break;
1028
1029 case 0xbc4: /* DMA_LCD_CTRL */
1030 s->dst = (value >> 8) & 0x1;
1031 s->src = ((value >> 6) & 0x3) << 1;
1032 s->condition = 0;
1033 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1034 s->interrupts = (value >> 1) & 1;
1035 s->dual = value & 1;
1036 break;
1037
1038 case 0xbc8: /* TOP_B1_L */
1039 s->src_f1_top &= 0xffff0000;
1040 s->src_f1_top |= 0x0000ffff & value;
1041 break;
1042
1043 case 0xbca: /* TOP_B1_U */
1044 s->src_f1_top &= 0x0000ffff;
1045 s->src_f1_top |= value << 16;
1046 break;
1047
1048 case 0xbcc: /* BOT_B1_L */
1049 s->src_f1_bottom &= 0xffff0000;
1050 s->src_f1_bottom |= 0x0000ffff & value;
1051 break;
1052
1053 case 0xbce: /* BOT_B1_U */
1054 s->src_f1_bottom &= 0x0000ffff;
1055 s->src_f1_bottom |= (uint32_t) value << 16;
1056 break;
1057
1058 case 0xbd0: /* TOP_B2_L */
1059 s->src_f2_top &= 0xffff0000;
1060 s->src_f2_top |= 0x0000ffff & value;
1061 break;
1062
1063 case 0xbd2: /* TOP_B2_U */
1064 s->src_f2_top &= 0x0000ffff;
1065 s->src_f2_top |= (uint32_t) value << 16;
1066 break;
1067
1068 case 0xbd4: /* BOT_B2_L */
1069 s->src_f2_bottom &= 0xffff0000;
1070 s->src_f2_bottom |= 0x0000ffff & value;
1071 break;
1072
1073 case 0xbd6: /* BOT_B2_U */
1074 s->src_f2_bottom &= 0x0000ffff;
1075 s->src_f2_bottom |= (uint32_t) value << 16;
1076 break;
1077
1078 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1079 s->element_index_f1 = value;
1080 break;
1081
1082 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1083 s->frame_index_f1 &= 0xffff0000;
1084 s->frame_index_f1 |= 0x0000ffff & value;
1085 break;
1086
1087 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1088 s->frame_index_f1 &= 0x0000ffff;
1089 s->frame_index_f1 |= (uint32_t) value << 16;
1090 break;
1091
1092 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1093 s->element_index_f2 = value;
1094 break;
1095
1096 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1097 s->frame_index_f2 &= 0xffff0000;
1098 s->frame_index_f2 |= 0x0000ffff & value;
1099 break;
1100
1101 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1102 s->frame_index_f2 &= 0x0000ffff;
1103 s->frame_index_f2 |= (uint32_t) value << 16;
1104 break;
1105
1106 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1107 s->elements_f1 = value;
1108 break;
1109
1110 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1111 s->frames_f1 = value;
1112 break;
1113
1114 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1115 s->elements_f2 = value;
1116 break;
1117
1118 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1119 s->frames_f2 = value;
1120 break;
1121
1122 case 0xbea: /* DMA_LCD_LCH_CTRL */
1123 s->lch_type = value & 0xf;
1124 break;
1125
1126 default:
1127 return 1;
1128 }
1129 return 0;
1130}
1131
1132static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1133 uint16_t *ret)
1134{
1135 switch (offset) {
1136 case 0xbc0: /* DMA_LCD_CSDP */
1137 *ret = (s->brust_f2 << 14) |
1138 (s->pack_f2 << 13) |
1139 ((s->data_type_f2 >> 1) << 11) |
1140 (s->brust_f1 << 7) |
1141 (s->pack_f1 << 6) |
1142 ((s->data_type_f1 >> 1) << 0);
1143 break;
1144
1145 case 0xbc2: /* DMA_LCD_CCR */
1146 *ret = (s->mode_f2 << 14) |
1147 (s->mode_f1 << 12) |
1148 (s->end_prog << 11) |
1149 (s->omap_3_1_compatible_disable << 10) |
1150 (s->repeat << 9) |
1151 (s->auto_init << 8) |
1152 (s->running << 7) |
1153 (s->priority << 6) |
1154 (s->bs << 4);
1155 break;
1156
1157 case 0xbc4: /* DMA_LCD_CTRL */
1158 qemu_irq_lower(s->irq);
1159 *ret = (s->dst << 8) |
1160 ((s->src & 0x6) << 5) |
1161 (s->condition << 3) |
1162 (s->interrupts << 1) |
1163 s->dual;
1164 break;
1165
1166 case 0xbc8: /* TOP_B1_L */
1167 *ret = s->src_f1_top & 0xffff;
1168 break;
1169
1170 case 0xbca: /* TOP_B1_U */
1171 *ret = s->src_f1_top >> 16;
1172 break;
1173
1174 case 0xbcc: /* BOT_B1_L */
1175 *ret = s->src_f1_bottom & 0xffff;
1176 break;
1177
1178 case 0xbce: /* BOT_B1_U */
1179 *ret = s->src_f1_bottom >> 16;
1180 break;
1181
1182 case 0xbd0: /* TOP_B2_L */
1183 *ret = s->src_f2_top & 0xffff;
1184 break;
1185
1186 case 0xbd2: /* TOP_B2_U */
1187 *ret = s->src_f2_top >> 16;
1188 break;
1189
1190 case 0xbd4: /* BOT_B2_L */
1191 *ret = s->src_f2_bottom & 0xffff;
1192 break;
1193
1194 case 0xbd6: /* BOT_B2_U */
1195 *ret = s->src_f2_bottom >> 16;
1196 break;
1197
1198 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1199 *ret = s->element_index_f1;
1200 break;
1201
1202 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1203 *ret = s->frame_index_f1 & 0xffff;
1204 break;
1205
1206 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1207 *ret = s->frame_index_f1 >> 16;
1208 break;
1209
1210 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1211 *ret = s->element_index_f2;
1212 break;
1213
1214 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1215 *ret = s->frame_index_f2 & 0xffff;
1216 break;
1217
1218 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1219 *ret = s->frame_index_f2 >> 16;
1220 break;
1221
1222 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1223 *ret = s->elements_f1;
1224 break;
1225
1226 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1227 *ret = s->frames_f1;
1228 break;
1229
1230 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1231 *ret = s->elements_f2;
1232 break;
1233
1234 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1235 *ret = s->frames_f2;
1236 break;
1237
1238 case 0xbea: /* DMA_LCD_LCH_CTRL */
1239 *ret = s->lch_type;
1240 break;
1241
1242 default:
1243 return 1;
1244 }
1245 return 0;
1246}
1247
1248static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1249 uint16_t value)
1250{
1251 switch (offset) {
1252 case 0x300: /* SYS_DMA_LCD_CTRL */
1253 s->src = (value & 0x40) ? imif : emiff;
1254 s->condition = 0;
1255 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1256 s->interrupts = (value >> 1) & 1;
1257 s->dual = value & 1;
1258 break;
1259
1260 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1261 s->src_f1_top &= 0xffff0000;
1262 s->src_f1_top |= 0x0000ffff & value;
1263 break;
1264
1265 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1266 s->src_f1_top &= 0x0000ffff;
1267 s->src_f1_top |= value << 16;
1268 break;
1269
1270 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1271 s->src_f1_bottom &= 0xffff0000;
1272 s->src_f1_bottom |= 0x0000ffff & value;
1273 break;
1274
1275 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1276 s->src_f1_bottom &= 0x0000ffff;
1277 s->src_f1_bottom |= value << 16;
1278 break;
1279
1280 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1281 s->src_f2_top &= 0xffff0000;
1282 s->src_f2_top |= 0x0000ffff & value;
1283 break;
1284
1285 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1286 s->src_f2_top &= 0x0000ffff;
1287 s->src_f2_top |= value << 16;
1288 break;
1289
1290 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1291 s->src_f2_bottom &= 0xffff0000;
1292 s->src_f2_bottom |= 0x0000ffff & value;
1293 break;
1294
1295 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1296 s->src_f2_bottom &= 0x0000ffff;
1297 s->src_f2_bottom |= value << 16;
1298 break;
1299
1300 default:
1301 return 1;
1302 }
1303 return 0;
1304}
1305
1306static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1307 uint16_t *ret)
1308{
1309 int i;
1310
1311 switch (offset) {
1312 case 0x300: /* SYS_DMA_LCD_CTRL */
1313 i = s->condition;
1314 s->condition = 0;
1315 qemu_irq_lower(s->irq);
1316 *ret = ((s->src == imif) << 6) | (i << 3) |
1317 (s->interrupts << 1) | s->dual;
1318 break;
1319
1320 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1321 *ret = s->src_f1_top & 0xffff;
1322 break;
1323
1324 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1325 *ret = s->src_f1_top >> 16;
1326 break;
1327
1328 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1329 *ret = s->src_f1_bottom & 0xffff;
1330 break;
1331
1332 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1333 *ret = s->src_f1_bottom >> 16;
1334 break;
1335
1336 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1337 *ret = s->src_f2_top & 0xffff;
1338 break;
1339
1340 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1341 *ret = s->src_f2_top >> 16;
1342 break;
1343
1344 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1345 *ret = s->src_f2_bottom & 0xffff;
1346 break;
1347
1348 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1349 *ret = s->src_f2_bottom >> 16;
1350 break;
1351
1352 default:
1353 return 1;
1354 }
1355 return 0;
1356}
1357
1358static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value)
1359{
1360 switch (offset) {
1361 case 0x400: /* SYS_DMA_GCR */
1362 s->gcr = value;
1363 break;
1364
1365 case 0x404: /* DMA_GSCR */
1366 if (value & 0x8)
1367 omap_dma_disable_3_1_mapping(s);
1368 else
1369 omap_dma_enable_3_1_mapping(s);
1370 break;
1371
1372 case 0x408: /* DMA_GRST */
1373 if (value & 0x1)
afbb5194 1374 omap_dma_reset(s->dma);
b4e3104b
AZ		 1375 break;
1376
1377 default:
1378 return 1;
1379 }
1380 return 0;
1381}
1382
1383static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
1384 uint16_t *ret)
1385{
1386 switch (offset) {
1387 case 0x400: /* SYS_DMA_GCR */
1388 *ret = s->gcr;
1389 break;
1390
1391 case 0x404: /* DMA_GSCR */
1392 *ret = s->omap_3_1_mapping_disabled << 3;
1393 break;
1394
1395 case 0x408: /* DMA_GRST */
1396 *ret = 0;
1397 break;
1398
1399 case 0x442: /* DMA_HW_ID */
1400 case 0x444: /* DMA_PCh2_ID */
1401 case 0x446: /* DMA_PCh0_ID */
1402 case 0x448: /* DMA_PCh1_ID */
1403 case 0x44a: /* DMA_PChG_ID */
1404 case 0x44c: /* DMA_PChD_ID */
1405 *ret = 1;
1406 break;
1407
1408 case 0x44e: /* DMA_CAPS_0_U */
827df9f3 1409 *ret = (s->caps[0] >> 16) & 0xffff;
b4e3104b 1410 break;
b4e3104b 1411 case 0x450: /* DMA_CAPS_0_L */
827df9f3 1412 *ret = (s->caps[0] >> 0) & 0xffff;
b4e3104b
AZ		 1413 break;
1414
827df9f3
AZ		 1415 case 0x452: /* DMA_CAPS_1_U */
1416 *ret = (s->caps[1] >> 16) & 0xffff;
1417 break;
b4e3104b 1418 case 0x454: /* DMA_CAPS_1_L */
827df9f3 1419 *ret = (s->caps[1] >> 0) & 0xffff;
b4e3104b
AZ		 1420 break;
1421
1422 case 0x456: /* DMA_CAPS_2 */
827df9f3 1423 *ret = s->caps[2];
b4e3104b
AZ		 1424 break;
1425
1426 case 0x458: /* DMA_CAPS_3 */
827df9f3 1427 *ret = s->caps[3];
b4e3104b
AZ		 1428 break;
1429
1430 case 0x45a: /* DMA_CAPS_4 */
827df9f3 1431 *ret = s->caps[4];
b4e3104b
AZ		 1432 break;
1433
1434 case 0x460: /* DMA_PCh2_SR */
1435 case 0x480: /* DMA_PCh0_SR */
1436 case 0x482: /* DMA_PCh1_SR */
1437 case 0x4c0: /* DMA_PChD_SR_0 */
1438 printf("%s: Physical Channel Status Registers not implemented.\n",
1439 __FUNCTION__);
1440 *ret = 0xff;
1441 break;
1442
1443 default:
1444 return 1;
1445 }
1446 return 0;
1447}
1448
a8170e5e 1449static uint64_t omap_dma_read(void *opaque, hwaddr addr,
7405165e 1450 unsigned size)
b4e3104b
AZ		 1451{
1452 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
8da3ff18 1453 int reg, ch;
b4e3104b
AZ		 1454 uint16_t ret;
1455
7405165e
AK		 1456 if (size != 2) {
1457 return omap_badwidth_read16(opaque, addr);
1458 }
1459
8da3ff18 1460 switch (addr) {
b4e3104b 1461 case 0x300 ... 0x3fe:
827df9f3 1462 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
8da3ff18 1463 if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
b4e3104b
AZ		 1464 break;
1465 return ret;
1466 }
1467 /* Fall through. */
1468 case 0x000 ... 0x2fe:
8da3ff18
PB		 1469 reg = addr & 0x3f;
1470 ch = (addr >> 6) & 0x0f;
b4e3104b
AZ		 1471 if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
1472 break;
1473 return ret;
1474
1475 case 0x404 ... 0x4fe:
827df9f3 1476 if (s->model <= omap_dma_3_1)
b4e3104b
AZ		 1477 break;
1478 /* Fall through. */
1479 case 0x400:
8da3ff18 1480 if (omap_dma_sys_read(s, addr, &ret))
b4e3104b
AZ		 1481 break;
1482 return ret;
1483
1484 case 0xb00 ... 0xbfe:
1485 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
8da3ff18 1486 if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
b4e3104b
AZ		 1487 break;
1488 return ret;
1489 }
1490 break;
1491 }
1492
1493 OMAP_BAD_REG(addr);
1494 return 0;
1495}
1496
a8170e5e 1497static void omap_dma_write(void *opaque, hwaddr addr,
7405165e 1498 uint64_t value, unsigned size)
b4e3104b
AZ		 1499{
1500 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
8da3ff18 1501 int reg, ch;
b4e3104b 1502
7405165e
AK		 1503 if (size != 2) {
1504 return omap_badwidth_write16(opaque, addr, value);
1505 }
1506
8da3ff18 1507 switch (addr) {
b4e3104b 1508 case 0x300 ... 0x3fe:
827df9f3 1509 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
8da3ff18 1510 if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
b4e3104b
AZ		 1511 break;
1512 return;
1513 }
1514 /* Fall through. */
1515 case 0x000 ... 0x2fe:
8da3ff18
PB		 1516 reg = addr & 0x3f;
1517 ch = (addr >> 6) & 0x0f;
b4e3104b
AZ		 1518 if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
1519 break;
1520 return;
1521
1522 case 0x404 ... 0x4fe:
827df9f3 1523 if (s->model <= omap_dma_3_1)
b4e3104b
AZ		 1524 break;
1525 case 0x400:
1526 /* Fall through. */
8da3ff18 1527 if (omap_dma_sys_write(s, addr, value))
b4e3104b
AZ		 1528 break;
1529 return;
1530
1531 case 0xb00 ... 0xbfe:
1532 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
8da3ff18 1533 if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
b4e3104b
AZ		 1534 break;
1535 return;
1536 }
1537 break;
1538 }
1539
1540 OMAP_BAD_REG(addr);
1541}
1542
7405165e
AK		 1543static const MemoryRegionOps omap_dma_ops = {
1544 .read = omap_dma_read,
1545 .write = omap_dma_write,
1546 .endianness = DEVICE_NATIVE_ENDIAN,
b4e3104b
AZ		 1547};
1548
1549static void omap_dma_request(void *opaque, int drq, int req)
1550{
1551 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
827df9f3 1552 /* The request pins are level triggered in QEMU. */
b4e3104b 1553 if (req) {
afbb5194
AZ		 1554 if (~s->dma->drqbmp & (1 << drq)) {
1555 s->dma->drqbmp |= 1 << drq;
b4e3104b
AZ		 1556 omap_dma_process_request(s, drq);
1557 }
1558 } else
afbb5194 1559 s->dma->drqbmp &= ~(1 << drq);
b4e3104b
AZ		 1560}
1561
afbb5194 1562/* XXX: this won't be needed once soc_dma knows about clocks. */
b4e3104b
AZ		 1563static void omap_dma_clk_update(void *opaque, int line, int on)
1564{
1565 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
afbb5194 1566 int i;
b4e3104b 1567
afbb5194
AZ		 1568 s->dma->freq = omap_clk_getrate(s->clk);
1569
1570 for (i = 0; i < s->chans; i ++)
1571 if (s->ch[i].active)
1572 soc_dma_set_request(s->ch[i].dma, on);
b4e3104b
AZ		 1573}
1574
827df9f3
AZ		 1575static void omap_dma_setcaps(struct omap_dma_s *s)
1576{
1577 switch (s->model) {
1578 default:
1579 case omap_dma_3_1:
1580 break;
1581 case omap_dma_3_2:
1582 case omap_dma_4:
1583 /* XXX Only available for sDMA */
1584 s->caps[0] =
1585 (1 << 19) | /* Constant Fill Capability */
1586 (1 << 18); /* Transparent BLT Capability */
1587 s->caps[1] =
1588 (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */
1589 s->caps[2] =
1590 (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */
1591 (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */
1592 (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */
1593 (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */
1594 (1 << 4) | /* DST_CONST_ADRS_CPBLTY */
1595 (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */
1596 (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */
1597 (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */
1598 (1 << 0); /* SRC_CONST_ADRS_CPBLTY */
1599 s->caps[3] =
1600 (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */
1601 (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */
1602 (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */
1603 (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */
1604 (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */
1605 (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */
1606 (1 << 1) | /* FRAME_SYNCHR_CPBLTY */
1607 (1 << 0); /* ELMNT_SYNCHR_CPBLTY */
1608 s->caps[4] =
1609 (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */
1610 (1 << 6) | /* SYNC_STATUS_CPBLTY */
1611 (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */
1612 (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */
1613 (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */
1614 (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */
1615 (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */
1616 (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */
1617 break;
1618 }
1619}
1620
a8170e5e 1621struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
7405165e 1622 MemoryRegion *sysmem,
b4e3104b
AZ		 1623 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
1624 enum omap_dma_model model)
1625{
7405165e 1626 int num_irqs, memsize, i;
b4e3104b 1627 struct omap_dma_s *s = (struct omap_dma_s *)
7267c094 1628 g_malloc0(sizeof(struct omap_dma_s));
b4e3104b 1629
827df9f3 1630 if (model <= omap_dma_3_1) {
b4e3104b
AZ		 1631 num_irqs = 6;
1632 memsize = 0x800;
1633 } else {
1634 num_irqs = 16;
1635 memsize = 0xc00;
1636 }
b4e3104b
AZ		 1637 s->model = model;
1638 s->mpu = mpu;
1639 s->clk = clk;
1640 s->lcd_ch.irq = lcd_irq;
1641 s->lcd_ch.mpu = mpu;
afbb5194
AZ		 1642
1643 s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16);
1644 s->dma->freq = omap_clk_getrate(clk);
1645 s->dma->transfer_fn = omap_dma_transfer_generic;
1646 s->dma->setup_fn = omap_dma_transfer_setup;
1647 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
1648 s->dma->opaque = s;
1649
b4e3104b
AZ		 1650 while (num_irqs --)
1651 s->ch[num_irqs].irq = irqs[num_irqs];
1652 for (i = 0; i < 3; i ++) {
1653 s->ch[i].sibling = &s->ch[i + 6];
1654 s->ch[i + 6].sibling = &s->ch[i];
1655 }
afbb5194
AZ		 1656 for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) {
1657 s->ch[i].dma = &s->dma->ch[i];
1658 s->dma->ch[i].opaque = &s->ch[i];
1659 }
1660
1661 omap_dma_setcaps(s);
b4e3104b 1662 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
afbb5194 1663 omap_dma_reset(s->dma);
b4e3104b
AZ		 1664 omap_dma_clk_update(s, 0, 1);
1665
7405165e
AK		 1666 memory_region_init_io(&s->iomem, &omap_dma_ops, s, "omap.dma", memsize);
1667 memory_region_add_subregion(sysmem, base, &s->iomem);
b4e3104b 1668
afbb5194
AZ		 1669 mpu->drq = s->dma->drq;
1670
1671 return s->dma;
b4e3104b
AZ		 1672}
1673
827df9f3
AZ		 1674static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
1675{
1676 struct omap_dma_channel_s *ch = s->ch;
1677 uint32_t bmp, bit;
1678
1679 for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1)
1680 if (ch->status) {
1681 bmp |= bit;
1682 ch->cstatus |= ch->status;
1683 ch->status = 0;
1684 }
1685 if ((s->irqstat[0] |= s->irqen[0] & bmp))
1686 qemu_irq_raise(s->irq[0]);
1687 if ((s->irqstat[1] |= s->irqen[1] & bmp))
1688 qemu_irq_raise(s->irq[1]);
1689 if ((s->irqstat[2] |= s->irqen[2] & bmp))
1690 qemu_irq_raise(s->irq[2]);
1691 if ((s->irqstat[3] |= s->irqen[3] & bmp))
1692 qemu_irq_raise(s->irq[3]);
1693}
1694
a8170e5e 1695static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
7405165e 1696 unsigned size)
827df9f3
AZ		 1697{
1698 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
8da3ff18 1699 int irqn = 0, chnum;
827df9f3
AZ		 1700 struct omap_dma_channel_s *ch;
1701
7405165e
AK		 1702 if (size == 1) {
1703 return omap_badwidth_read16(opaque, addr);
1704 }
1705
8da3ff18 1706 switch (addr) {
827df9f3
AZ		 1707 case 0x00: /* DMA4_REVISION */
1708 return 0x40;
1709
1710 case 0x14: /* DMA4_IRQSTATUS_L3 */
1711 irqn ++;
be688dfb 1712 /* fall through */
827df9f3
AZ		 1713 case 0x10: /* DMA4_IRQSTATUS_L2 */
1714 irqn ++;
be688dfb 1715 /* fall through */
827df9f3
AZ		 1716 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1717 irqn ++;
be688dfb 1718 /* fall through */
827df9f3
AZ		 1719 case 0x08: /* DMA4_IRQSTATUS_L0 */
1720 return s->irqstat[irqn];
1721
1722 case 0x24: /* DMA4_IRQENABLE_L3 */
1723 irqn ++;
be688dfb 1724 /* fall through */
827df9f3
AZ		 1725 case 0x20: /* DMA4_IRQENABLE_L2 */
1726 irqn ++;
be688dfb 1727 /* fall through */
827df9f3
AZ		 1728 case 0x1c: /* DMA4_IRQENABLE_L1 */
1729 irqn ++;
be688dfb 1730 /* fall through */
827df9f3
AZ		 1731 case 0x18: /* DMA4_IRQENABLE_L0 */
1732 return s->irqen[irqn];
1733
1734 case 0x28: /* DMA4_SYSSTATUS */
1735 return 1; /* RESETDONE */
1736
1737 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1738 return s->ocp;
1739
1740 case 0x64: /* DMA4_CAPS_0 */
1741 return s->caps[0];
1742 case 0x6c: /* DMA4_CAPS_2 */
1743 return s->caps[2];
1744 case 0x70: /* DMA4_CAPS_3 */
1745 return s->caps[3];
1746 case 0x74: /* DMA4_CAPS_4 */
1747 return s->caps[4];
1748
1749 case 0x78: /* DMA4_GCR */
1750 return s->gcr;
1751
1752 case 0x80 ... 0xfff:
8da3ff18
PB		 1753 addr -= 0x80;
1754 chnum = addr / 0x60;
827df9f3 1755 ch = s->ch + chnum;
8da3ff18 1756 addr -= chnum * 0x60;
827df9f3
AZ		 1757 break;
1758
1759 default:
1760 OMAP_BAD_REG(addr);
1761 return 0;
1762 }
1763
1764 /* Per-channel registers */
8da3ff18 1765 switch (addr) {
827df9f3
AZ		 1766 case 0x00: /* DMA4_CCR */
1767 return (ch->buf_disable << 25) |
1768 (ch->src_sync << 24) |
1769 (ch->prefetch << 23) |
1770 ((ch->sync & 0x60) << 14) |
1771 (ch->bs << 18) |
1772 (ch->transparent_copy << 17) |
1773 (ch->constant_fill << 16) |
1774 (ch->mode[1] << 14) |
1775 (ch->mode[0] << 12) |
1776 (0 << 10) | (0 << 9) |
1777 (ch->suspend << 8) |
1778 (ch->enable << 7) |
1779 (ch->priority << 6) |
1780 (ch->fs << 5) | (ch->sync & 0x1f);
1781
1782 case 0x04: /* DMA4_CLNK_CTRL */
1783 return (ch->link_enabled << 15) | ch->link_next_ch;
1784
1785 case 0x08: /* DMA4_CICR */
1786 return ch->interrupts;
1787
1788 case 0x0c: /* DMA4_CSR */
1789 return ch->cstatus;
1790
1791 case 0x10: /* DMA4_CSDP */
1792 return (ch->endian[0] << 21) |
1793 (ch->endian_lock[0] << 20) |
1794 (ch->endian[1] << 19) |
1795 (ch->endian_lock[1] << 18) |
1796 (ch->write_mode << 16) |
1797 (ch->burst[1] << 14) |
1798 (ch->pack[1] << 13) |
1799 (ch->translate[1] << 9) |
1800 (ch->burst[0] << 7) |
1801 (ch->pack[0] << 6) |
1802 (ch->translate[0] << 2) |
1803 (ch->data_type >> 1);
1804
1805 case 0x14: /* DMA4_CEN */
1806 return ch->elements;
1807
1808 case 0x18: /* DMA4_CFN */
1809 return ch->frames;
1810
1811 case 0x1c: /* DMA4_CSSA */
1812 return ch->addr[0];
1813
1814 case 0x20: /* DMA4_CDSA */
1815 return ch->addr[1];
1816
1817 case 0x24: /* DMA4_CSEI */
1818 return ch->element_index[0];
1819
1820 case 0x28: /* DMA4_CSFI */
1821 return ch->frame_index[0];
1822
1823 case 0x2c: /* DMA4_CDEI */
1824 return ch->element_index[1];
1825
1826 case 0x30: /* DMA4_CDFI */
1827 return ch->frame_index[1];
1828
1829 case 0x34: /* DMA4_CSAC */
1830 return ch->active_set.src & 0xffff;
1831
1832 case 0x38: /* DMA4_CDAC */
1833 return ch->active_set.dest & 0xffff;
1834
1835 case 0x3c: /* DMA4_CCEN */
1836 return ch->active_set.element;
1837
1838 case 0x40: /* DMA4_CCFN */
1839 return ch->active_set.frame;
1840
1841 case 0x44: /* DMA4_COLOR */
1842 /* XXX only in sDMA */
1843 return ch->color;
1844
1845 default:
1846 OMAP_BAD_REG(addr);
1847 return 0;
1848 }
1849}
1850
a8170e5e 1851static void omap_dma4_write(void *opaque, hwaddr addr,
7405165e 1852 uint64_t value, unsigned size)
827df9f3
AZ		 1853{
1854 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
8da3ff18 1855 int chnum, irqn = 0;
827df9f3
AZ		 1856 struct omap_dma_channel_s *ch;
1857
7405165e
AK		 1858 if (size == 1) {
1859 return omap_badwidth_write16(opaque, addr, value);
1860 }
1861
8da3ff18 1862 switch (addr) {
827df9f3
AZ		 1863 case 0x14: /* DMA4_IRQSTATUS_L3 */
1864 irqn ++;
be688dfb 1865 /* fall through */
827df9f3
AZ		 1866 case 0x10: /* DMA4_IRQSTATUS_L2 */
1867 irqn ++;
be688dfb 1868 /* fall through */
827df9f3
AZ		 1869 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1870 irqn ++;
be688dfb 1871 /* fall through */
827df9f3
AZ		 1872 case 0x08: /* DMA4_IRQSTATUS_L0 */
1873 s->irqstat[irqn] &= ~value;
1874 if (!s->irqstat[irqn])
1875 qemu_irq_lower(s->irq[irqn]);
1876 return;
1877
1878 case 0x24: /* DMA4_IRQENABLE_L3 */
1879 irqn ++;
be688dfb 1880 /* fall through */
827df9f3
AZ		 1881 case 0x20: /* DMA4_IRQENABLE_L2 */
1882 irqn ++;
be688dfb 1883 /* fall through */
827df9f3
AZ		 1884 case 0x1c: /* DMA4_IRQENABLE_L1 */
1885 irqn ++;
be688dfb 1886 /* fall through */
827df9f3
AZ		 1887 case 0x18: /* DMA4_IRQENABLE_L0 */
1888 s->irqen[irqn] = value;
1889 return;
1890
1891 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1892 if (value & 2) /* SOFTRESET */
afbb5194 1893 omap_dma_reset(s->dma);
827df9f3
AZ		 1894 s->ocp = value & 0x3321;
1895 if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */
1896 fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__);
1897 return;
1898
1899 case 0x78: /* DMA4_GCR */
1900 s->gcr = value & 0x00ff00ff;
1901 if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */
1902 fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__);
1903 return;
1904
1905 case 0x80 ... 0xfff:
8da3ff18
PB		 1906 addr -= 0x80;
1907 chnum = addr / 0x60;
827df9f3 1908 ch = s->ch + chnum;
8da3ff18 1909 addr -= chnum * 0x60;
827df9f3
AZ		 1910 break;
1911
1912 case 0x00: /* DMA4_REVISION */
1913 case 0x28: /* DMA4_SYSSTATUS */
1914 case 0x64: /* DMA4_CAPS_0 */
1915 case 0x6c: /* DMA4_CAPS_2 */
1916 case 0x70: /* DMA4_CAPS_3 */
1917 case 0x74: /* DMA4_CAPS_4 */
1918 OMAP_RO_REG(addr);
1919 return;
1920
1921 default:
1922 OMAP_BAD_REG(addr);
1923 return;
1924 }
1925
1926 /* Per-channel registers */
8da3ff18 1927 switch (addr) {
827df9f3
AZ		 1928 case 0x00: /* DMA4_CCR */
1929 ch->buf_disable = (value >> 25) & 1;
1930 ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
1931 if (ch->buf_disable && !ch->src_sync)
1932 fprintf(stderr, "%s: Buffering disable is not allowed in "
1933 "destination synchronised mode\n", __FUNCTION__);
1934 ch->prefetch = (value >> 23) & 1;
1935 ch->bs = (value >> 18) & 1;
1936 ch->transparent_copy = (value >> 17) & 1;
1937 ch->constant_fill = (value >> 16) & 1;
c227f099
AL		 1938 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
1939 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
827df9f3
AZ		 1940 ch->suspend = (value & 0x0100) >> 8;
1941 ch->priority = (value & 0x0040) >> 6;
1942 ch->fs = (value & 0x0020) >> 5;
1943 if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1])
1944 fprintf(stderr, "%s: For a packet transfer at least one port "
1945 "must be constant-addressed\n", __FUNCTION__);
1946 ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060);
1947 /* XXX must be 0x01 for CamDMA */
1948
1949 if (value & 0x0080)
1950 omap_dma_enable_channel(s, ch);
1951 else
1952 omap_dma_disable_channel(s, ch);
1953
1954 break;
1955
1956 case 0x04: /* DMA4_CLNK_CTRL */
1957 ch->link_enabled = (value >> 15) & 0x1;
1958 ch->link_next_ch = value & 0x1f;
1959 break;
1960
1961 case 0x08: /* DMA4_CICR */
1962 ch->interrupts = value & 0x09be;
1963 break;
1964
1965 case 0x0c: /* DMA4_CSR */
1966 ch->cstatus &= ~value;
1967 break;
1968
1969 case 0x10: /* DMA4_CSDP */
1970 ch->endian[0] =(value >> 21) & 1;
1971 ch->endian_lock[0] =(value >> 20) & 1;
1972 ch->endian[1] =(value >> 19) & 1;
1973 ch->endian_lock[1] =(value >> 18) & 1;
1974 if (ch->endian[0] != ch->endian[1])
afbb5194 1975 fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n",
827df9f3
AZ		 1976 __FUNCTION__);
1977 ch->write_mode = (value >> 16) & 3;
1978 ch->burst[1] = (value & 0xc000) >> 14;
1979 ch->pack[1] = (value & 0x2000) >> 13;
1980 ch->translate[1] = (value & 0x1e00) >> 9;
1981 ch->burst[0] = (value & 0x0180) >> 7;
1982 ch->pack[0] = (value & 0x0040) >> 6;
1983 ch->translate[0] = (value & 0x003c) >> 2;
1984 if (ch->translate[0] | ch->translate[1])
1985 fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n",
1986 __FUNCTION__);
1987 ch->data_type = 1 << (value & 3);
1988 if ((value & 3) == 3)
1989 printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
1990 break;
1991
1992 case 0x14: /* DMA4_CEN */
afbb5194 1993 ch->set_update = 1;
827df9f3
AZ		 1994 ch->elements = value & 0xffffff;
1995 break;
1996
1997 case 0x18: /* DMA4_CFN */
1998 ch->frames = value & 0xffff;
afbb5194 1999 ch->set_update = 1;
827df9f3
AZ		 2000 break;
2001
2002 case 0x1c: /* DMA4_CSSA */
a8170e5e 2003 ch->addr[0] = (hwaddr) (uint32_t) value;
afbb5194 2004 ch->set_update = 1;
827df9f3
AZ		 2005 break;
2006
2007 case 0x20: /* DMA4_CDSA */
a8170e5e 2008 ch->addr[1] = (hwaddr) (uint32_t) value;
afbb5194 2009 ch->set_update = 1;
827df9f3
AZ		 2010 break;
2011
2012 case 0x24: /* DMA4_CSEI */
2013 ch->element_index[0] = (int16_t) value;
afbb5194 2014 ch->set_update = 1;
827df9f3
AZ		 2015 break;
2016
2017 case 0x28: /* DMA4_CSFI */
2018 ch->frame_index[0] = (int32_t) value;
afbb5194 2019 ch->set_update = 1;
827df9f3
AZ		 2020 break;
2021
2022 case 0x2c: /* DMA4_CDEI */
2023 ch->element_index[1] = (int16_t) value;
afbb5194 2024 ch->set_update = 1;
827df9f3
AZ		 2025 break;
2026
2027 case 0x30: /* DMA4_CDFI */
2028 ch->frame_index[1] = (int32_t) value;
afbb5194 2029 ch->set_update = 1;
827df9f3
AZ		 2030 break;
2031
2032 case 0x44: /* DMA4_COLOR */
2033 /* XXX only in sDMA */
2034 ch->color = value;
2035 break;
2036
2037 case 0x34: /* DMA4_CSAC */
2038 case 0x38: /* DMA4_CDAC */
2039 case 0x3c: /* DMA4_CCEN */
2040 case 0x40: /* DMA4_CCFN */
2041 OMAP_RO_REG(addr);
2042 break;
2043
2044 default:
2045 OMAP_BAD_REG(addr);
2046 }
2047}
2048
7405165e
AK		 2049static const MemoryRegionOps omap_dma4_ops = {
2050 .read = omap_dma4_read,
2051 .write = omap_dma4_write,
2052 .endianness = DEVICE_NATIVE_ENDIAN,
827df9f3
AZ		 2053};
2054
a8170e5e 2055struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
7405165e 2056 MemoryRegion *sysmem,
827df9f3
AZ		 2057 struct omap_mpu_state_s *mpu, int fifo,
2058 int chans, omap_clk iclk, omap_clk fclk)
2059{
7405165e 2060 int i;
827df9f3 2061 struct omap_dma_s *s = (struct omap_dma_s *)
7267c094 2062 g_malloc0(sizeof(struct omap_dma_s));
827df9f3 2063
827df9f3
AZ		 2064 s->model = omap_dma_4;
2065 s->chans = chans;
2066 s->mpu = mpu;
2067 s->clk = fclk;
afbb5194
AZ		 2068
2069 s->dma = soc_dma_init(s->chans);
2070 s->dma->freq = omap_clk_getrate(fclk);
2071 s->dma->transfer_fn = omap_dma_transfer_generic;
2072 s->dma->setup_fn = omap_dma_transfer_setup;
2073 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64);
2074 s->dma->opaque = s;
2075 for (i = 0; i < s->chans; i ++) {
2076 s->ch[i].dma = &s->dma->ch[i];
2077 s->dma->ch[i].opaque = &s->ch[i];
2078 }
2079
827df9f3
AZ		 2080 memcpy(&s->irq, irqs, sizeof(s->irq));
2081 s->intr_update = omap_dma_interrupts_4_update;
afbb5194 2082
827df9f3 2083 omap_dma_setcaps(s);
827df9f3 2084 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
afbb5194
AZ		 2085 omap_dma_reset(s->dma);
2086 omap_dma_clk_update(s, 0, !!s->dma->freq);
827df9f3 2087
7405165e
AK		 2088 memory_region_init_io(&s->iomem, &omap_dma4_ops, s, "omap.dma4", 0x1000);
2089 memory_region_add_subregion(sysmem, base, &s->iomem);
827df9f3 2090
afbb5194
AZ		 2091 mpu->drq = s->dma->drq;
2092
2093 return s->dma;
827df9f3
AZ		 2094}
2095
afbb5194 2096struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma)
b4e3104b 2097{
afbb5194
AZ		 2098 struct omap_dma_s *s = dma->opaque;
2099
b4e3104b
AZ		 2100 return &s->lcd_ch;
2101}
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