[qemu.git] / hw / microblaze / xlnx-zynqmp-pmu.c

/*
 * Xilinx Zynq MPSoC PMU (Power Management Unit) emulation
 *
 * Copyright (C) 2017 Xilinx Inc
 * Written by Alistair Francis <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "cpu.h"
#include "boot.h"

#include "hw/intc/xlnx-zynqmp-ipi.h"
#include "hw/intc/xlnx-pmu-iomod-intc.h"

/* Define the PMU device */

#define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc"
#define XLNX_ZYNQMP_PMU_SOC(obj) OBJECT_CHECK(XlnxZynqMPPMUSoCState, (obj), \
                                              TYPE_XLNX_ZYNQMP_PMU_SOC)

#define XLNX_ZYNQMP_PMU_ROM_SIZE    0x8000
#define XLNX_ZYNQMP_PMU_ROM_ADDR    0xFFD00000
#define XLNX_ZYNQMP_PMU_RAM_ADDR    0xFFDC0000

#define XLNX_ZYNQMP_PMU_INTC_ADDR   0xFFD40000

#define XLNX_ZYNQMP_PMU_NUM_IPIS    4

static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
    0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
};
static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
    19, 20, 21, 22,
};

typedef struct XlnxZynqMPPMUSoCState {
    /*< private >*/
    DeviceState parent_obj;

    /*< public >*/
    MicroBlazeCPU cpu;
    XlnxPMUIOIntc intc;
}  XlnxZynqMPPMUSoCState;


static void xlnx_zynqmp_pmu_soc_init(Object *obj)
{
    XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);

    object_initialize_child(obj, "pmu-cpu", &s->cpu, sizeof(s->cpu),
                            TYPE_MICROBLAZE_CPU, &error_abort, NULL);

    sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
                          TYPE_XLNX_PMU_IO_INTC);
}

static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
{
    XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(dev);
    Error *err = NULL;

    object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,
                             "base-vectors", &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), true, "use-stack-protection",
                             &error_abort);
    object_property_set_uint(OBJECT(&s->cpu), 0, "use-fpu", &error_abort);
    object_property_set_uint(OBJECT(&s->cpu), 0, "use-hw-mul", &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), true, "use-barrel",
                             &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), true, "use-msr-instr",
                             &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), true, "use-pcmp-instr",
                             &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), false, "use-mmu", &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), true, "endianness",
                             &error_abort);
    object_property_set_str(OBJECT(&s->cpu), "8.40.b", "version",
                            &error_abort);
    object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    object_property_set_uint(OBJECT(&s->intc), 0x10, "intc-intr-size",
                             &error_abort);
    object_property_set_uint(OBJECT(&s->intc), 0x0, "intc-level-edge",
                             &error_abort);
    object_property_set_uint(OBJECT(&s->intc), 0xffff, "intc-positive",
                             &error_abort);
    object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
}

static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = xlnx_zynqmp_pmu_soc_realize;
}

static const TypeInfo xlnx_zynqmp_pmu_soc_type_info = {
    .name = TYPE_XLNX_ZYNQMP_PMU_SOC,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(XlnxZynqMPPMUSoCState),
    .instance_init = xlnx_zynqmp_pmu_soc_init,
    .class_init = xlnx_zynqmp_pmu_soc_class_init,
};

static void xlnx_zynqmp_pmu_soc_register_types(void)
{
    type_register_static(&xlnx_zynqmp_pmu_soc_type_info);
}

type_init(xlnx_zynqmp_pmu_soc_register_types)

/* Define the PMU Machine */

static void xlnx_zynqmp_pmu_init(MachineState *machine)
{
    XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
    MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
    XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
    qemu_irq irq[32];
    int i;

    /* Create the ROM */
    memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
                           XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
                                pmu_rom);

    /* Create the RAM */
    memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",
                           machine->ram_size, &error_fatal);
    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
                                pmu_ram);

    /* Create the PMU device */
    object_initialize(pmu, sizeof(XlnxZynqMPPMUSoCState), TYPE_XLNX_ZYNQMP_PMU_SOC);
    object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu),
                              &error_abort);
    object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);

    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i);
    }

    /* Create and connect the IPI device */
    for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
        ipi[i] = g_new0(XlnxZynqMPIPI, 1);
        object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);
        qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default());
    }

    for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
        object_property_set_bool(OBJECT(ipi[i]), true, "realized",
                                 &error_abort);
        sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
    }

    /* Load the kernel */
    microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
                           machine->ram_size,
                           machine->initrd_filename,
                           machine->dtb,
                           NULL);
}

static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
{
    mc->desc = "Xilinx ZynqMP PMU machine";
    mc->init = xlnx_zynqmp_pmu_init;
}

DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
Commit	Line	Data
4690bf4e AF	1	/*
	2	* Xilinx Zynq MPSoC PMU (Power Management Unit) emulation
	3	*
	4	* Copyright (C) 2017 Xilinx Inc
	5	* Written by Alistair Francis <[email protected]>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*/
	17
	18	#include "qemu/osdep.h"
	19	#include "qapi/error.h"
	20	#include "qemu-common.h"
133d23b3	21	#include "exec/address-spaces.h"
4690bf4e	22	#include "hw/boards.h"
133d23b3	23	#include "hw/qdev-properties.h"
4690bf4e	24	#include "cpu.h"
133d23b3	25	#include "boot.h"
4690bf4e	26
07b30201	27	#include "hw/intc/xlnx-zynqmp-ipi.h"
633a91b6 AF	28	#include "hw/intc/xlnx-pmu-iomod-intc.h"
633a91b6 AF	29
4690bf4e AF	30	/* Define the PMU device */
	31
	32	#define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc"
	33	#define XLNX_ZYNQMP_PMU_SOC(obj) OBJECT_CHECK(XlnxZynqMPPMUSoCState, (obj), \
	34	TYPE_XLNX_ZYNQMP_PMU_SOC)
	35
133d23b3 AF	36	#define XLNX_ZYNQMP_PMU_ROM_SIZE 0x8000
	37	#define XLNX_ZYNQMP_PMU_ROM_ADDR 0xFFD00000
	38	#define XLNX_ZYNQMP_PMU_RAM_ADDR 0xFFDC0000
	39
633a91b6 AF	40	#define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000
633a91b6 AF	41
07b30201 AF	42	#define XLNX_ZYNQMP_PMU_NUM_IPIS 4
	43
	44	static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
	45	0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
	46	};
	47	static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
	48	19, 20, 21, 22,
	49	};
	50
4690bf4e AF	51	typedef struct XlnxZynqMPPMUSoCState {
	52	/< private >/
	53	DeviceState parent_obj;
	54
	55	/< public >/
133d23b3	56	MicroBlazeCPU cpu;
633a91b6	57	XlnxPMUIOIntc intc;
4690bf4e AF	58	} XlnxZynqMPPMUSoCState;
4690bf4e AF	59
633a91b6	60
4690bf4e AF	61	static void xlnx_zynqmp_pmu_soc_init(Object *obj)
4690bf4e AF	62	{
133d23b3	63	XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);
4690bf4e	64
7b6d7b84 TH	65	object_initialize_child(obj, "pmu-cpu", &s->cpu, sizeof(s->cpu),
7b6d7b84 TH	66	TYPE_MICROBLAZE_CPU, &error_abort, NULL);
633a91b6	67
7b6d7b84 TH	68	sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
7b6d7b84 TH	69	TYPE_XLNX_PMU_IO_INTC);
4690bf4e AF	70	}
	71
	72	static void xlnx_zynqmp_pmu_soc_realize(DeviceState dev, Error *errp)
	73	{
133d23b3 AF	74	XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(dev);
	75	Error *err = NULL;
	76
	77	object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,
	78	"base-vectors", &error_abort);
	79	object_property_set_bool(OBJECT(&s->cpu), true, "use-stack-protection",
	80	&error_abort);
	81	object_property_set_uint(OBJECT(&s->cpu), 0, "use-fpu", &error_abort);
	82	object_property_set_uint(OBJECT(&s->cpu), 0, "use-hw-mul", &error_abort);
	83	object_property_set_bool(OBJECT(&s->cpu), true, "use-barrel",
	84	&error_abort);
	85	object_property_set_bool(OBJECT(&s->cpu), true, "use-msr-instr",
	86	&error_abort);
	87	object_property_set_bool(OBJECT(&s->cpu), true, "use-pcmp-instr",
	88	&error_abort);
	89	object_property_set_bool(OBJECT(&s->cpu), false, "use-mmu", &error_abort);
	90	object_property_set_bool(OBJECT(&s->cpu), true, "endianness",
	91	&error_abort);
	92	object_property_set_str(OBJECT(&s->cpu), "8.40.b", "version",
	93	&error_abort);
	94	object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort);
	95	object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
	96	if (err) {
	97	error_propagate(errp, err);
	98	return;
	99	}
633a91b6 AF	100
	101	object_property_set_uint(OBJECT(&s->intc), 0x10, "intc-intr-size",
	102	&error_abort);
	103	object_property_set_uint(OBJECT(&s->intc), 0x0, "intc-level-edge",
	104	&error_abort);
	105	object_property_set_uint(OBJECT(&s->intc), 0xffff, "intc-positive",
	106	&error_abort);
	107	object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
	108	if (err) {
	109	error_propagate(errp, err);
	110	return;
	111	}
	112	sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
	113	sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
	114	qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
4690bf4e AF	115	}
	116
	117	static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass oc, void data)
	118	{
	119	DeviceClass *dc = DEVICE_CLASS(oc);
	120
	121	dc->realize = xlnx_zynqmp_pmu_soc_realize;
	122	}
	123
	124	static const TypeInfo xlnx_zynqmp_pmu_soc_type_info = {
	125	.name = TYPE_XLNX_ZYNQMP_PMU_SOC,
	126	.parent = TYPE_DEVICE,
	127	.instance_size = sizeof(XlnxZynqMPPMUSoCState),
	128	.instance_init = xlnx_zynqmp_pmu_soc_init,
	129	.class_init = xlnx_zynqmp_pmu_soc_class_init,
	130	};
	131
	132	static void xlnx_zynqmp_pmu_soc_register_types(void)
	133	{
	134	type_register_static(&xlnx_zynqmp_pmu_soc_type_info);
	135	}
	136
	137	type_init(xlnx_zynqmp_pmu_soc_register_types)
	138
	139	/* Define the PMU Machine */
	140
	141	static void xlnx_zynqmp_pmu_init(MachineState *machine)
	142	{
133d23b3 AF	143	XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);
	144	MemoryRegion *address_space_mem = get_system_memory();
	145	MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
	146	MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
07b30201 AF	147	XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
	148	qemu_irq irq[32];
	149	int i;
133d23b3 AF	150
	151	/* Create the ROM */
	152	memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
	153	XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
	154	memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
	155	pmu_rom);
	156
	157	/* Create the RAM */
	158	memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",
	159	machine->ram_size, &error_fatal);
	160	memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
	161	pmu_ram);
	162
	163	/* Create the PMU device */
	164	object_initialize(pmu, sizeof(XlnxZynqMPPMUSoCState), TYPE_XLNX_ZYNQMP_PMU_SOC);
	165	object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu),
	166	&error_abort);
	167	object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
	168
07b30201 AF	169	for (i = 0; i < 32; i++) {
	170	irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i);
	171	}
	172
	173	/* Create and connect the IPI device */
	174	for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
	175	ipi[i] = g_new0(XlnxZynqMPIPI, 1);
	176	object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);
	177	qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default());
	178	}
	179
	180	for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
	181	object_property_set_bool(OBJECT(ipi[i]), true, "realized",
	182	&error_abort);
	183	sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]);
	184	sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
	185	}
	186
133d23b3 AF	187	/* Load the kernel */
	188	microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
	189	machine->ram_size,
	190	machine->initrd_filename,
	191	machine->dtb,
	192	NULL);
4690bf4e AF	193	}
	194
	195	static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
	196	{
	197	mc->desc = "Xilinx ZynqMP PMU machine";
	198	mc->init = xlnx_zynqmp_pmu_init;
	199	}
	200
	201	DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
	202