[qemu.git] / hw / sh_intc.c

/*
 * SuperH interrupt controller module
 *
 * Copyright (c) 2007 Magnus Damm
 * Based on sh_timer.c and arm_timer.c by Paul Brook
 * Copyright (c) 2005-2006 CodeSourcery.
 *
 * This code is licenced under the GPL.
 */

#include <assert.h>
#include "sh_intc.h"
#include "hw.h"
#include "sh.h"

//#define DEBUG_INTC
//#define DEBUG_INTC_SOURCES

#define INTC_A7(x) ((x) & 0x1fffffff)
#define INTC_ARRAY(x) (sizeof(x) / sizeof(x[0]))

void sh_intc_toggle_source(struct intc_source *source,
			   int enable_adj, int assert_adj)
{
    int enable_changed = 0;
    int pending_changed = 0;
    int old_pending;

    if ((source->enable_count == source->enable_max) && (enable_adj == -1))
        enable_changed = -1;

    source->enable_count += enable_adj;

    if (source->enable_count == source->enable_max)
        enable_changed = 1;

    source->asserted += assert_adj;

    old_pending = source->pending;
    source->pending = source->asserted &&
      (source->enable_count == source->enable_max);

    if (old_pending != source->pending)
        pending_changed = 1;

    if (pending_changed) {
        if (source->pending) {
            source->parent->pending++;
	    if (source->parent->pending == 1)
                cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
	}
	else {
            source->parent->pending--;
	    if (source->parent->pending == 0)
                cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
	}
    }

  if (enable_changed || assert_adj || pending_changed) {
#ifdef DEBUG_INTC_SOURCES
            printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
		   source->parent->pending,
		   source->asserted,
		   source->enable_count,
		   source->enable_max,
		   source->vect,
		   source->asserted ? "asserted " :
		   assert_adj ? "deasserted" : "",
		   enable_changed == 1 ? "enabled " :
		   enable_changed == -1 ? "disabled " : "",
		   source->pending ? "pending" : "");
#endif
  }
}

static void sh_intc_set_irq (void *opaque, int n, int level)
{
  struct intc_desc *desc = opaque;
  struct intc_source *source = &(desc->sources[n]);

  if (level && !source->asserted)
    sh_intc_toggle_source(source, 0, 1);
  else if (!level && source->asserted)
    sh_intc_toggle_source(source, 0, -1);
}

int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
{
    unsigned int i;

    /* slow: use a linked lists of pending sources instead */
    /* wrong: take interrupt priority into account (one list per priority) */

    if (imask == 0x0f) {
        return -1; /* FIXME, update code to include priority per source */
    }

    for (i = 0; i < desc->nr_sources; i++) {
        struct intc_source *source = desc->sources + i;

	if (source->pending) {
#ifdef DEBUG_INTC_SOURCES
            printf("sh_intc: (%d) returning interrupt source 0x%x\n",
		   desc->pending, source->vect);
#endif
            return source->vect;
	}
    }

    assert(0);
}

#define INTC_MODE_NONE       0
#define INTC_MODE_DUAL_SET   1
#define INTC_MODE_DUAL_CLR   2
#define INTC_MODE_ENABLE_REG 3
#define INTC_MODE_MASK_REG   4
#define INTC_MODE_IS_PRIO    8

static unsigned int sh_intc_mode(unsigned long address,
				 unsigned long set_reg, unsigned long clr_reg)
{
    if ((address != INTC_A7(set_reg)) &&
	(address != INTC_A7(clr_reg)))
        return INTC_MODE_NONE;

    if (set_reg && clr_reg) {
        if (address == INTC_A7(set_reg))
            return INTC_MODE_DUAL_SET;
	else
            return INTC_MODE_DUAL_CLR;
    }

    if (set_reg)
        return INTC_MODE_ENABLE_REG;
    else
        return INTC_MODE_MASK_REG;
}

static void sh_intc_locate(struct intc_desc *desc,
			   unsigned long address,
			   unsigned long **datap,
			   intc_enum **enums,
			   unsigned int *first,
			   unsigned int *width,
			   unsigned int *modep)
{
    unsigned int i, mode;

    /* this is slow but works for now */

    if (desc->mask_regs) {
        for (i = 0; i < desc->nr_mask_regs; i++) {
	    struct intc_mask_reg *mr = desc->mask_regs + i;

	    mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
	    if (mode == INTC_MODE_NONE)
                continue;

	    *modep = mode;
	    *datap = &mr->value;
	    *enums = mr->enum_ids;
	    *first = mr->reg_width - 1;
	    *width = 1;
	    return;
	}
    }

    if (desc->prio_regs) {
        for (i = 0; i < desc->nr_prio_regs; i++) {
	    struct intc_prio_reg *pr = desc->prio_regs + i;

	    mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
	    if (mode == INTC_MODE_NONE)
                continue;

	    *modep = mode | INTC_MODE_IS_PRIO;
	    *datap = &pr->value;
	    *enums = pr->enum_ids;
	    *first = (pr->reg_width / pr->field_width) - 1;
	    *width = pr->field_width;
	    return;
	}
    }

    assert(0);
}

static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
				int enable, int is_group)
{
    struct intc_source *source = desc->sources + id;

    if (!id)
	return;

    if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
#ifdef DEBUG_INTC_SOURCES
        printf("sh_intc: reserved interrupt source %d modified\n", id);
#endif
	return;
    }

    if (source->vect)
        sh_intc_toggle_source(source, enable ? 1 : -1, 0);

#ifdef DEBUG_INTC
    else {
        printf("setting interrupt group %d to %d\n", id, !!enable);
    }
#endif

    if ((is_group || !source->vect) && source->next_enum_id) {
        sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
    }

#ifdef DEBUG_INTC
    if (!source->vect) {
        printf("setting interrupt group %d to %d - done\n", id, !!enable);
    }
#endif
}

static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
{
    struct intc_desc *desc = opaque;
    intc_enum *enum_ids = NULL;
    unsigned int first = 0;
    unsigned int width = 0;
    unsigned int mode = 0;
    unsigned long *valuep;

#ifdef DEBUG_INTC
    printf("sh_intc_read 0x%lx\n", (unsigned long) offset);
#endif

    sh_intc_locate(desc, (unsigned long)offset, &valuep, 
		   &enum_ids, &first, &width, &mode);
    return *valuep;
}

static void sh_intc_write(void *opaque, target_phys_addr_t offset,
			  uint32_t value)
{
    struct intc_desc *desc = opaque;
    intc_enum *enum_ids = NULL;
    unsigned int first = 0;
    unsigned int width = 0;
    unsigned int mode = 0;
    unsigned int k;
    unsigned long *valuep;
    unsigned long mask;

#ifdef DEBUG_INTC
    printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
#endif

    sh_intc_locate(desc, (unsigned long)offset, &valuep, 
		   &enum_ids, &first, &width, &mode);

    switch (mode) {
    case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
    case INTC_MODE_DUAL_SET: value |= *valuep; break;
    case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
    default: assert(0);
    }

    for (k = 0; k <= first; k++) {
        mask = ((1 << width) - 1) << ((first - k) * width);

	if ((*valuep & mask) == (value & mask))
            continue;
#if 0
	printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n", 
	       k, first, enum_ids[k], (unsigned int)mask);
#endif
        sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
    }

    *valuep = value;

#ifdef DEBUG_INTC
    printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value);
#endif
}

static CPUReadMemoryFunc *sh_intc_readfn[] = {
    sh_intc_read,
    sh_intc_read,
    sh_intc_read
};

static CPUWriteMemoryFunc *sh_intc_writefn[] = {
    sh_intc_write,
    sh_intc_write,
    sh_intc_write
};

struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
{
    if (id)
        return desc->sources + id;

    return NULL;
}

static void sh_intc_register(struct intc_desc *desc, 
			     unsigned long address)
{
    if (address) {
        cpu_register_physical_memory_offset(P4ADDR(address), 4,
                                            desc->iomemtype, INTC_A7(address));
        cpu_register_physical_memory_offset(A7ADDR(address), 4,
                                            desc->iomemtype, INTC_A7(address));
    }
}

static void sh_intc_register_source(struct intc_desc *desc,
				    intc_enum source,
				    struct intc_group *groups,
				    int nr_groups)
{
    unsigned int i, k;
    struct intc_source *s;

    if (desc->mask_regs) {
        for (i = 0; i < desc->nr_mask_regs; i++) {
	    struct intc_mask_reg *mr = desc->mask_regs + i;

	    for (k = 0; k < INTC_ARRAY(mr->enum_ids); k++) {
                if (mr->enum_ids[k] != source)
                    continue;

		s = sh_intc_source(desc, mr->enum_ids[k]);
		if (s)
                    s->enable_max++;
	    }
	}
    }

    if (desc->prio_regs) {
        for (i = 0; i < desc->nr_prio_regs; i++) {
	    struct intc_prio_reg *pr = desc->prio_regs + i;

	    for (k = 0; k < INTC_ARRAY(pr->enum_ids); k++) {
                if (pr->enum_ids[k] != source)
                    continue;

		s = sh_intc_source(desc, pr->enum_ids[k]);
		if (s)
                    s->enable_max++;
	    }
	}
    }

    if (groups) {
        for (i = 0; i < nr_groups; i++) {
	    struct intc_group *gr = groups + i;

	    for (k = 0; k < INTC_ARRAY(gr->enum_ids); k++) {
                if (gr->enum_ids[k] != source)
                    continue;

		s = sh_intc_source(desc, gr->enum_ids[k]);
		if (s)
                    s->enable_max++;
	    }
	}
    }

}

void sh_intc_register_sources(struct intc_desc *desc,
			      struct intc_vect *vectors,
			      int nr_vectors,
			      struct intc_group *groups,
			      int nr_groups)
{
    unsigned int i, k;
    struct intc_source *s;

    for (i = 0; i < nr_vectors; i++) {
	struct intc_vect *vect = vectors + i;

	sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
	s = sh_intc_source(desc, vect->enum_id);
	if (s)
	    s->vect = vect->vect;

#ifdef DEBUG_INTC_SOURCES
	printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
	       vect->enum_id, s->vect, s->enable_count, s->enable_max);
#endif
    }

    if (groups) {
        for (i = 0; i < nr_groups; i++) {
	    struct intc_group *gr = groups + i;

	    s = sh_intc_source(desc, gr->enum_id);
	    s->next_enum_id = gr->enum_ids[0];

	    for (k = 1; k < INTC_ARRAY(gr->enum_ids); k++) {
                if (!gr->enum_ids[k])
                    continue;

		s = sh_intc_source(desc, gr->enum_ids[k - 1]);
		s->next_enum_id = gr->enum_ids[k];
	    }

#ifdef DEBUG_INTC_SOURCES
	    printf("sh_intc: registered group %d (%d/%d)\n",
		   gr->enum_id, s->enable_count, s->enable_max);
#endif
	}
    }
}

int sh_intc_init(struct intc_desc *desc,
		 int nr_sources,
		 struct intc_mask_reg *mask_regs,
		 int nr_mask_regs,
		 struct intc_prio_reg *prio_regs,
		 int nr_prio_regs)
{
    unsigned int i;

    desc->pending = 0;
    desc->nr_sources = nr_sources;
    desc->mask_regs = mask_regs;
    desc->nr_mask_regs = nr_mask_regs;
    desc->prio_regs = prio_regs;
    desc->nr_prio_regs = nr_prio_regs;

    i = sizeof(struct intc_source) * nr_sources;
    desc->sources = malloc(i);
    if (!desc->sources)
        return -1;

    memset(desc->sources, 0, i);
    for (i = 0; i < desc->nr_sources; i++) {
        struct intc_source *source = desc->sources + i;

        source->parent = desc;
    }

    desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
 
    desc->iomemtype = cpu_register_io_memory(0, sh_intc_readfn,
					     sh_intc_writefn, desc);
    if (desc->mask_regs) {
        for (i = 0; i < desc->nr_mask_regs; i++) {
	    struct intc_mask_reg *mr = desc->mask_regs + i;

	    sh_intc_register(desc, mr->set_reg);
	    sh_intc_register(desc, mr->clr_reg);
	}
    }

    if (desc->prio_regs) {
        for (i = 0; i < desc->nr_prio_regs; i++) {
	    struct intc_prio_reg *pr = desc->prio_regs + i;

	    sh_intc_register(desc, pr->set_reg);
	    sh_intc_register(desc, pr->clr_reg);
	}
    }

    return 0;
}

/* Assert level <n> IRL interrupt. 
   0:deassert. 1:lowest priority,... 15:highest priority. */
void sh_intc_set_irl(void *opaque, int n, int level)
{
    struct intc_source *s = opaque;
    int i, irl = level ^ 15;
    for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
	if (i == irl)
	    sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
	else
	    if (s->asserted)
	        sh_intc_toggle_source(s, 0, -1);
    }
}
Commit	Line	Data
80f515e6 AZ	1	/*
	2	* SuperH interrupt controller module
	3	*
	4	* Copyright (c) 2007 Magnus Damm
	5	* Based on sh_timer.c and arm_timer.c by Paul Brook
	6	* Copyright (c) 2005-2006 CodeSourcery.
	7	*
	8	* This code is licenced under the GPL.
	9	*/
	10
	11	#include <assert.h>
	12	#include "sh_intc.h"
87ecb68b PB	13	#include "hw.h"
87ecb68b PB	14	#include "sh.h"
80f515e6 AZ	15
80f515e6 AZ	16	//#define DEBUG_INTC
e96e2044	17	//#define DEBUG_INTC_SOURCES
80f515e6 AZ	18
	19	#define INTC_A7(x) ((x) & 0x1fffffff)
	20	#define INTC_ARRAY(x) (sizeof(x) / sizeof(x[0]))
	21
e96e2044 TS	22	void sh_intc_toggle_source(struct intc_source *source,
	23	int enable_adj, int assert_adj)
	24	{
	25	int enable_changed = 0;
	26	int pending_changed = 0;
	27	int old_pending;
	28
	29	if ((source->enable_count == source->enable_max) && (enable_adj == -1))
	30	enable_changed = -1;
	31
	32	source->enable_count += enable_adj;
	33
	34	if (source->enable_count == source->enable_max)
	35	enable_changed = 1;
	36
	37	source->asserted += assert_adj;
	38
	39	old_pending = source->pending;
	40	source->pending = source->asserted &&
	41	(source->enable_count == source->enable_max);
	42
	43	if (old_pending != source->pending)
	44	pending_changed = 1;
	45
	46	if (pending_changed) {
	47	if (source->pending) {
	48	source->parent->pending++;
	49	if (source->parent->pending == 1)
	50	cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
	51	}
	52	else {
	53	source->parent->pending--;
	54	if (source->parent->pending == 0)
	55	cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
	56	}
	57	}
	58
	59	if (enable_changed \|\| assert_adj \|\| pending_changed) {
	60	#ifdef DEBUG_INTC_SOURCES
	61	printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
	62	source->parent->pending,
	63	source->asserted,
	64	source->enable_count,
	65	source->enable_max,
	66	source->vect,
	67	source->asserted ? "asserted " :
	68	assert_adj ? "deasserted" : "",
	69	enable_changed == 1 ? "enabled " :
	70	enable_changed == -1 ? "disabled " : "",
	71	source->pending ? "pending" : "");
	72	#endif
	73	}
	74	}
	75
b79e1752	76	static void sh_intc_set_irq (void *opaque, int n, int level)
96e2fc41 AJ	77	{
	78	struct intc_desc *desc = opaque;
	79	struct intc_source *source = &(desc->sources[n]);
	80
4e7ed2d1 AJ	81	if (level && !source->asserted)
	82	sh_intc_toggle_source(source, 0, 1);
	83	else if (!level && source->asserted)
	84	sh_intc_toggle_source(source, 0, -1);
96e2fc41 AJ	85	}
96e2fc41 AJ	86
e96e2044 TS	87	int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
	88	{
	89	unsigned int i;
	90
	91	/* slow: use a linked lists of pending sources instead */
	92	/* wrong: take interrupt priority into account (one list per priority) */
	93
	94	if (imask == 0x0f) {
	95	return -1; /* FIXME, update code to include priority per source */
	96	}
	97
	98	for (i = 0; i < desc->nr_sources; i++) {
	99	struct intc_source *source = desc->sources + i;
	100
	101	if (source->pending) {
	102	#ifdef DEBUG_INTC_SOURCES
	103	printf("sh_intc: (%d) returning interrupt source 0x%x\n",
	104	desc->pending, source->vect);
	105	#endif
	106	return source->vect;
	107	}
	108	}
	109
	110	assert(0);
	111	}
	112
80f515e6 AZ	113	#define INTC_MODE_NONE 0
	114	#define INTC_MODE_DUAL_SET 1
	115	#define INTC_MODE_DUAL_CLR 2
	116	#define INTC_MODE_ENABLE_REG 3
	117	#define INTC_MODE_MASK_REG 4
	118	#define INTC_MODE_IS_PRIO 8
	119
	120	static unsigned int sh_intc_mode(unsigned long address,
	121	unsigned long set_reg, unsigned long clr_reg)
	122	{
	123	if ((address != INTC_A7(set_reg)) &&
	124	(address != INTC_A7(clr_reg)))
	125	return INTC_MODE_NONE;
	126
	127	if (set_reg && clr_reg) {
	128	if (address == INTC_A7(set_reg))
	129	return INTC_MODE_DUAL_SET;
	130	else
	131	return INTC_MODE_DUAL_CLR;
	132	}
	133
	134	if (set_reg)
	135	return INTC_MODE_ENABLE_REG;
	136	else
	137	return INTC_MODE_MASK_REG;
	138	}
	139
	140	static void sh_intc_locate(struct intc_desc *desc,
	141	unsigned long address,
	142	unsigned long **datap,
	143	intc_enum **enums,
	144	unsigned int *first,
	145	unsigned int *width,
	146	unsigned int *modep)
	147	{
	148	unsigned int i, mode;
	149
	150	/* this is slow but works for now */
	151
	152	if (desc->mask_regs) {
	153	for (i = 0; i < desc->nr_mask_regs; i++) {
	154	struct intc_mask_reg *mr = desc->mask_regs + i;
	155
	156	mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
	157	if (mode == INTC_MODE_NONE)
	158	continue;
	159
	160	*modep = mode;
	161	*datap = &mr->value;
	162	*enums = mr->enum_ids;
	163	*first = mr->reg_width - 1;
	164	*width = 1;
	165	return;
	166	}
	167	}
	168
	169	if (desc->prio_regs) {
	170	for (i = 0; i < desc->nr_prio_regs; i++) {
	171	struct intc_prio_reg *pr = desc->prio_regs + i;
	172
	173	mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
	174	if (mode == INTC_MODE_NONE)
	175	continue;
	176
177	*modep = mode \| INTC_MODE_IS_PRIO;
178	*datap = &pr->value;
179	*enums = pr->enum_ids;
180	*first = (pr->reg_width / pr->field_width) - 1;
181	*width = pr->field_width;
182	return;
183	}
184	}
185
186	assert(0);
187	}
188
e96e2044 TS	189	static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
e96e2044 TS	190	int enable, int is_group)
80f515e6 AZ	191	{
80f515e6 AZ	192	struct intc_source *source = desc->sources + id;
80f515e6 AZ	193
	194	if (!id)
	195	return;
	196
	197	if (!source->next_enum_id && (!source->enable_max \|\| !source->vect)) {
e96e2044	198	#ifdef DEBUG_INTC_SOURCES
80f515e6 AZ	199	printf("sh_intc: reserved interrupt source %d modified\n", id);
	200	#endif
	201	return;
	202	}
	203
e96e2044 TS	204	if (source->vect)
e96e2044 TS	205	sh_intc_toggle_source(source, enable ? 1 : -1, 0);
80f515e6	206
80f515e6 AZ	207	#ifdef DEBUG_INTC
	208	else {
	209	printf("setting interrupt group %d to %d\n", id, !!enable);
	210	}
	211	#endif
	212
	213	if ((is_group \|\| !source->vect) && source->next_enum_id) {
e96e2044	214	sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
80f515e6 AZ	215	}
	216
	217	#ifdef DEBUG_INTC
	218	if (!source->vect) {
	219	printf("setting interrupt group %d to %d - done\n", id, !!enable);
	220	}
	221	#endif
	222	}
	223
	224	static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
	225	{
	226	struct intc_desc *desc = opaque;
	227	intc_enum *enum_ids = NULL;
	228	unsigned int first = 0;
	229	unsigned int width = 0;
	230	unsigned int mode = 0;
	231	unsigned long *valuep;
	232
	233	#ifdef DEBUG_INTC
	234	printf("sh_intc_read 0x%lx\n", (unsigned long) offset);
	235	#endif
	236
	237	sh_intc_locate(desc, (unsigned long)offset, &valuep,
	238	&enum_ids, &first, &width, &mode);
	239	return *valuep;
	240	}
	241
	242	static void sh_intc_write(void *opaque, target_phys_addr_t offset,
	243	uint32_t value)
	244	{
	245	struct intc_desc *desc = opaque;
	246	intc_enum *enum_ids = NULL;
	247	unsigned int first = 0;
	248	unsigned int width = 0;
	249	unsigned int mode = 0;
	250	unsigned int k;
	251	unsigned long *valuep;
	252	unsigned long mask;
	253
	254	#ifdef DEBUG_INTC
	255	printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
	256	#endif
	257
	258	sh_intc_locate(desc, (unsigned long)offset, &valuep,
	259	&enum_ids, &first, &width, &mode);
	260
	261	switch (mode) {
	262	case INTC_MODE_ENABLE_REG \| INTC_MODE_IS_PRIO: break;
	263	case INTC_MODE_DUAL_SET: value \|= *valuep; break;
	264	case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
	265	default: assert(0);
	266	}
	267
	268	for (k = 0; k <= first; k++) {
	269	mask = ((1 << width) - 1) << ((first - k) * width);
	270
	271	if ((*valuep & mask) == (value & mask))
	272	continue;
	273	#if 0
	274	printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
	275	k, first, enum_ids[k], (unsigned int)mask);
	276	#endif
e96e2044	277	sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
80f515e6 AZ	278	}
	279
	280	*valuep = value;
	281
	282	#ifdef DEBUG_INTC
	283	printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value);
	284	#endif
	285	}
	286
	287	static CPUReadMemoryFunc *sh_intc_readfn[] = {
	288	sh_intc_read,
	289	sh_intc_read,
	290	sh_intc_read
	291	};
	292
	293	static CPUWriteMemoryFunc *sh_intc_writefn[] = {
	294	sh_intc_write,
	295	sh_intc_write,
	296	sh_intc_write
	297	};
	298
	299	struct intc_source sh_intc_source(struct intc_desc desc, intc_enum id)
	300	{
	301	if (id)
	302	return desc->sources + id;
	303
	304	return NULL;
	305	}
	306
	307	static void sh_intc_register(struct intc_desc *desc,
	308	unsigned long address)
	309	{
5c16736a AZ	310	if (address) {
5c16736a AZ	311	cpu_register_physical_memory_offset(P4ADDR(address), 4,
8da3ff18	312	desc->iomemtype, INTC_A7(address));
5c16736a AZ	313	cpu_register_physical_memory_offset(A7ADDR(address), 4,
	314	desc->iomemtype, INTC_A7(address));
	315	}
80f515e6 AZ	316	}
	317
	318	static void sh_intc_register_source(struct intc_desc *desc,
	319	intc_enum source,
	320	struct intc_group *groups,
	321	int nr_groups)
	322	{
	323	unsigned int i, k;
	324	struct intc_source *s;
	325
	326	if (desc->mask_regs) {
	327	for (i = 0; i < desc->nr_mask_regs; i++) {
	328	struct intc_mask_reg *mr = desc->mask_regs + i;
	329
	330	for (k = 0; k < INTC_ARRAY(mr->enum_ids); k++) {
	331	if (mr->enum_ids[k] != source)
	332	continue;
	333
	334	s = sh_intc_source(desc, mr->enum_ids[k]);
	335	if (s)
	336	s->enable_max++;
	337	}
	338	}
	339	}
	340
	341	if (desc->prio_regs) {
	342	for (i = 0; i < desc->nr_prio_regs; i++) {
	343	struct intc_prio_reg *pr = desc->prio_regs + i;
	344
	345	for (k = 0; k < INTC_ARRAY(pr->enum_ids); k++) {
	346	if (pr->enum_ids[k] != source)
	347	continue;
	348
	349	s = sh_intc_source(desc, pr->enum_ids[k]);
	350	if (s)
	351	s->enable_max++;
	352	}
	353	}
	354	}
	355
	356	if (groups) {
	357	for (i = 0; i < nr_groups; i++) {
	358	struct intc_group *gr = groups + i;
	359
	360	for (k = 0; k < INTC_ARRAY(gr->enum_ids); k++) {
	361	if (gr->enum_ids[k] != source)
	362	continue;
	363
	364	s = sh_intc_source(desc, gr->enum_ids[k]);
	365	if (s)
	366	s->enable_max++;
	367	}
	368	}
	369	}
	370
	371	}
	372
	373	void sh_intc_register_sources(struct intc_desc *desc,
	374	struct intc_vect *vectors,
	375	int nr_vectors,
	376	struct intc_group *groups,
	377	int nr_groups)
	378	{
	379	unsigned int i, k;
380	struct intc_source *s;
381
382	for (i = 0; i < nr_vectors; i++) {
383	struct intc_vect *vect = vectors + i;
384
385	sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
386	s = sh_intc_source(desc, vect->enum_id);
387	if (s)
388	s->vect = vect->vect;
389
e96e2044	390	#ifdef DEBUG_INTC_SOURCES
80f515e6 AZ	391	printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
	392	vect->enum_id, s->vect, s->enable_count, s->enable_max);
	393	#endif
	394	}
	395
	396	if (groups) {
	397	for (i = 0; i < nr_groups; i++) {
	398	struct intc_group *gr = groups + i;
	399
	400	s = sh_intc_source(desc, gr->enum_id);
	401	s->next_enum_id = gr->enum_ids[0];
	402
	403	for (k = 1; k < INTC_ARRAY(gr->enum_ids); k++) {
	404	if (!gr->enum_ids[k])
	405	continue;
	406
	407	s = sh_intc_source(desc, gr->enum_ids[k - 1]);
	408	s->next_enum_id = gr->enum_ids[k];
	409	}
	410
e96e2044	411	#ifdef DEBUG_INTC_SOURCES
80f515e6 AZ	412	printf("sh_intc: registered group %d (%d/%d)\n",
	413	gr->enum_id, s->enable_count, s->enable_max);
	414	#endif
	415	}
	416	}
	417	}
	418
	419	int sh_intc_init(struct intc_desc *desc,
	420	int nr_sources,
	421	struct intc_mask_reg *mask_regs,
	422	int nr_mask_regs,
	423	struct intc_prio_reg *prio_regs,
	424	int nr_prio_regs)
	425	{
	426	unsigned int i;
	427
e96e2044	428	desc->pending = 0;
80f515e6 AZ	429	desc->nr_sources = nr_sources;
	430	desc->mask_regs = mask_regs;
	431	desc->nr_mask_regs = nr_mask_regs;
	432	desc->prio_regs = prio_regs;
	433	desc->nr_prio_regs = nr_prio_regs;
	434
	435	i = sizeof(struct intc_source) * nr_sources;
	436	desc->sources = malloc(i);
	437	if (!desc->sources)
	438	return -1;
	439
	440	memset(desc->sources, 0, i);
e96e2044 TS	441	for (i = 0; i < desc->nr_sources; i++) {
	442	struct intc_source *source = desc->sources + i;
	443
	444	source->parent = desc;
	445	}
96e2fc41 AJ	446
96e2fc41 AJ	447	desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
80f515e6 AZ	448
	449	desc->iomemtype = cpu_register_io_memory(0, sh_intc_readfn,
	450	sh_intc_writefn, desc);
	451	if (desc->mask_regs) {
	452	for (i = 0; i < desc->nr_mask_regs; i++) {
	453	struct intc_mask_reg *mr = desc->mask_regs + i;
	454
	455	sh_intc_register(desc, mr->set_reg);
	456	sh_intc_register(desc, mr->clr_reg);
	457	}
	458	}
	459
	460	if (desc->prio_regs) {
	461	for (i = 0; i < desc->nr_prio_regs; i++) {
	462	struct intc_prio_reg *pr = desc->prio_regs + i;
	463
	464	sh_intc_register(desc, pr->set_reg);
	465	sh_intc_register(desc, pr->clr_reg);
	466	}
	467	}
	468
	469	return 0;
	470	}
c6d86a33 AZ	471
	472	/* Assert level <n> IRL interrupt.
	473	0:deassert. 1:lowest priority,... 15:highest priority. */
	474	void sh_intc_set_irl(void *opaque, int n, int level)
	475	{
	476	struct intc_source *s = opaque;
	477	int i, irl = level ^ 15;
	478	for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
	479	if (i == irl)
	480	sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
	481	else
	482	if (s->asserted)
	483	sh_intc_toggle_source(s, 0, -1);
	484	}
	485	}