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7d13299d
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1/*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
3ef693a0
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6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
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11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
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16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7d13299d 23
fbf9eeb3
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24#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
36bdbe54
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38int tb_invalidated_flag;
39
dc99065b 40//#define DEBUG_EXEC
9de5e440 41//#define DEBUG_SIGNAL
7d13299d 42
93ac68bc 43#if defined(TARGET_ARM) || defined(TARGET_SPARC)
e4533c7a
FB
44/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
50
fbf9eeb3
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51/* exit the current TB from a signal handler. The host registers are
52 restored in a state compatible with the CPU emulator
53 */
54void cpu_resume_from_signal(CPUState *env1, void *puc)
55{
56#if !defined(CONFIG_SOFTMMU)
57 struct ucontext *uc = puc;
58#endif
59
60 env = env1;
61
62 /* XXX: restore cpu registers saved in host registers */
63
64#if !defined(CONFIG_SOFTMMU)
65 if (puc) {
66 /* XXX: use siglongjmp ? */
67 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
68 }
69#endif
70 longjmp(env->jmp_env, 1);
71}
72
7d13299d
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73/* main execution loop */
74
e4533c7a 75int cpu_exec(CPUState *env1)
7d13299d 76{
e4533c7a
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77 int saved_T0, saved_T1, saved_T2;
78 CPUState *saved_env;
04369ff2
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79#ifdef reg_EAX
80 int saved_EAX;
81#endif
82#ifdef reg_ECX
83 int saved_ECX;
84#endif
85#ifdef reg_EDX
86 int saved_EDX;
87#endif
88#ifdef reg_EBX
89 int saved_EBX;
90#endif
91#ifdef reg_ESP
92 int saved_ESP;
93#endif
94#ifdef reg_EBP
95 int saved_EBP;
96#endif
97#ifdef reg_ESI
98 int saved_ESI;
99#endif
100#ifdef reg_EDI
101 int saved_EDI;
8c6939c0
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102#endif
103#ifdef __sparc__
104 int saved_i7, tmp_T0;
04369ff2 105#endif
68a79315 106 int code_gen_size, ret, interrupt_request;
7d13299d 107 void (*gen_func)(void);
9de5e440 108 TranslationBlock *tb, **ptb;
dab2ed99 109 uint8_t *tc_ptr, *cs_base, *pc;
6dbad63e 110 unsigned int flags;
8c6939c0 111
7d13299d
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112 /* first we save global registers */
113 saved_T0 = T0;
114 saved_T1 = T1;
e4533c7a 115 saved_T2 = T2;
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116 saved_env = env;
117 env = env1;
e4533c7a
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118#ifdef __sparc__
119 /* we also save i7 because longjmp may not restore it */
120 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
121#endif
122
123#if defined(TARGET_I386)
04369ff2
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124#ifdef reg_EAX
125 saved_EAX = EAX;
126 EAX = env->regs[R_EAX];
127#endif
128#ifdef reg_ECX
129 saved_ECX = ECX;
130 ECX = env->regs[R_ECX];
131#endif
132#ifdef reg_EDX
133 saved_EDX = EDX;
134 EDX = env->regs[R_EDX];
135#endif
136#ifdef reg_EBX
137 saved_EBX = EBX;
138 EBX = env->regs[R_EBX];
139#endif
140#ifdef reg_ESP
141 saved_ESP = ESP;
142 ESP = env->regs[R_ESP];
143#endif
144#ifdef reg_EBP
145 saved_EBP = EBP;
146 EBP = env->regs[R_EBP];
147#endif
148#ifdef reg_ESI
149 saved_ESI = ESI;
150 ESI = env->regs[R_ESI];
151#endif
152#ifdef reg_EDI
153 saved_EDI = EDI;
154 EDI = env->regs[R_EDI];
155#endif
7d13299d 156
9de5e440 157 /* put eflags in CPU temporary format */
fc2b4c48
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158 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
159 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 160 CC_OP = CC_OP_EFLAGS;
fc2b4c48 161 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a
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162#elif defined(TARGET_ARM)
163 {
164 unsigned int psr;
165 psr = env->cpsr;
166 env->CF = (psr >> 29) & 1;
167 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
168 env->VF = (psr << 3) & 0x80000000;
169 env->cpsr = psr & ~0xf0000000;
170 }
93ac68bc 171#elif defined(TARGET_SPARC)
67867308 172#elif defined(TARGET_PPC)
e4533c7a
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173#else
174#error unsupported target CPU
175#endif
3fb2ded1 176 env->exception_index = -1;
9d27abd9 177
7d13299d 178 /* prepare setjmp context for exception handling */
3fb2ded1
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179 for(;;) {
180 if (setjmp(env->jmp_env) == 0) {
ee8b7021 181 env->current_tb = NULL;
3fb2ded1
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182 /* if an exception is pending, we execute it here */
183 if (env->exception_index >= 0) {
184 if (env->exception_index >= EXCP_INTERRUPT) {
185 /* exit request from the cpu execution loop */
186 ret = env->exception_index;
187 break;
188 } else if (env->user_mode_only) {
189 /* if user mode only, we simulate a fake exception
190 which will be hanlded outside the cpu execution
191 loop */
83479e77 192#if defined(TARGET_I386)
3fb2ded1
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193 do_interrupt_user(env->exception_index,
194 env->exception_is_int,
195 env->error_code,
196 env->exception_next_eip);
83479e77 197#endif
3fb2ded1
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198 ret = env->exception_index;
199 break;
200 } else {
83479e77 201#if defined(TARGET_I386)
3fb2ded1
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202 /* simulate a real cpu exception. On i386, it can
203 trigger new exceptions, but we do not handle
204 double or triple faults yet. */
205 do_interrupt(env->exception_index,
206 env->exception_is_int,
207 env->error_code,
d05e66d2 208 env->exception_next_eip, 0);
ce09776b
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209#elif defined(TARGET_PPC)
210 do_interrupt(env);
83479e77 211#endif
3fb2ded1
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212 }
213 env->exception_index = -1;
214 }
3fb2ded1
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215 T0 = 0; /* force lookup of first TB */
216 for(;;) {
8c6939c0 217#ifdef __sparc__
3fb2ded1
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218 /* g1 can be modified by some libc? functions */
219 tmp_T0 = T0;
8c6939c0 220#endif
68a79315 221 interrupt_request = env->interrupt_request;
2e255c6b 222 if (__builtin_expect(interrupt_request, 0)) {
68a79315
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223#if defined(TARGET_I386)
224 /* if hardware interrupt pending, we execute it */
225 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316
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226 (env->eflags & IF_MASK) &&
227 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 228 int intno;
fbf9eeb3 229 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
a541f297 230 intno = cpu_get_pic_interrupt(env);
f193c797 231 if (loglevel & CPU_LOG_TB_IN_ASM) {
68a79315
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232 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
233 }
d05e66d2 234 do_interrupt(intno, 0, 0, 0, 1);
907a5b26
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235 /* ensure that no TB jump will be modified as
236 the program flow was changed */
237#ifdef __sparc__
238 tmp_T0 = 0;
239#else
240 T0 = 0;
241#endif
68a79315 242 }
ce09776b
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243#elif defined(TARGET_PPC)
244 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
245 do_queue_exception(EXCP_EXTERNAL);
246 if (check_exception_state(env))
247 do_interrupt(env);
248 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
249 }
68a79315 250#endif
bf3e8bf1
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251 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
252 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
253 /* ensure that no TB jump will be modified as
254 the program flow was changed */
255#ifdef __sparc__
256 tmp_T0 = 0;
257#else
258 T0 = 0;
259#endif
260 }
68a79315
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261 if (interrupt_request & CPU_INTERRUPT_EXIT) {
262 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
263 env->exception_index = EXCP_INTERRUPT;
264 cpu_loop_exit();
265 }
3fb2ded1 266 }
7d13299d 267#ifdef DEBUG_EXEC
f193c797 268 if (loglevel & CPU_LOG_EXEC) {
e4533c7a 269#if defined(TARGET_I386)
3fb2ded1
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270 /* restore flags in standard format */
271 env->regs[R_EAX] = EAX;
272 env->regs[R_EBX] = EBX;
273 env->regs[R_ECX] = ECX;
274 env->regs[R_EDX] = EDX;
275 env->regs[R_ESI] = ESI;
276 env->regs[R_EDI] = EDI;
277 env->regs[R_EBP] = EBP;
278 env->regs[R_ESP] = ESP;
279 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
68a79315 280 cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
3fb2ded1 281 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 282#elif defined(TARGET_ARM)
1b21b62a 283 env->cpsr = compute_cpsr();
3fb2ded1 284 cpu_arm_dump_state(env, logfile, 0);
1b21b62a 285 env->cpsr &= ~0xf0000000;
93ac68bc 286#elif defined(TARGET_SPARC)
93a40ea9 287 cpu_sparc_dump_state (env, logfile, 0);
67867308
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288#elif defined(TARGET_PPC)
289 cpu_ppc_dump_state(env, logfile, 0);
e4533c7a
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290#else
291#error unsupported target CPU
292#endif
3fb2ded1 293 }
7d13299d 294#endif
3f337316
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295 /* we record a subset of the CPU state. It will
296 always be the same before a given translated block
297 is executed. */
e4533c7a 298#if defined(TARGET_I386)
2e255c6b 299 flags = env->hflags;
3f337316 300 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
3fb2ded1
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301 cs_base = env->segs[R_CS].base;
302 pc = cs_base + env->eip;
e4533c7a 303#elif defined(TARGET_ARM)
3fb2ded1
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304 flags = 0;
305 cs_base = 0;
306 pc = (uint8_t *)env->regs[15];
93ac68bc 307#elif defined(TARGET_SPARC)
67867308 308 flags = 0;
ce09776b 309 cs_base = (uint8_t *)env->npc;
67867308
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310 pc = (uint8_t *) env->pc;
311#elif defined(TARGET_PPC)
312 flags = 0;
313 cs_base = 0;
314 pc = (uint8_t *)env->nip;
e4533c7a
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315#else
316#error unsupported CPU
317#endif
3fb2ded1
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318 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
319 flags);
d4e8164f 320 if (!tb) {
1376847f
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321 TranslationBlock **ptb1;
322 unsigned int h;
323 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
324
325
3fb2ded1 326 spin_lock(&tb_lock);
1376847f
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327
328 tb_invalidated_flag = 0;
329
330 /* find translated block using physical mappings */
331 phys_pc = get_phys_addr_code(env, (unsigned long)pc);
332 phys_page1 = phys_pc & TARGET_PAGE_MASK;
333 phys_page2 = -1;
334 h = tb_phys_hash_func(phys_pc);
335 ptb1 = &tb_phys_hash[h];
336 for(;;) {
337 tb = *ptb1;
338 if (!tb)
339 goto not_found;
340 if (tb->pc == (unsigned long)pc &&
341 tb->page_addr[0] == phys_page1 &&
342 tb->cs_base == (unsigned long)cs_base &&
343 tb->flags == flags) {
344 /* check next page if needed */
b516f85c
FB
345 if (tb->page_addr[1] != -1) {
346 virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) +
347 TARGET_PAGE_SIZE;
1376847f
FB
348 phys_page2 = get_phys_addr_code(env, virt_page2);
349 if (tb->page_addr[1] == phys_page2)
350 goto found;
351 } else {
352 goto found;
353 }
354 }
355 ptb1 = &tb->phys_hash_next;
356 }
357 not_found:
3fb2ded1 358 /* if no translated code available, then translate it now */
d4e8164f 359 tb = tb_alloc((unsigned long)pc);
3fb2ded1
FB
360 if (!tb) {
361 /* flush must be done */
b453b70b 362 tb_flush(env);
3fb2ded1
FB
363 /* cannot fail at this point */
364 tb = tb_alloc((unsigned long)pc);
365 /* don't forget to invalidate previous TB info */
366 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
367 T0 = 0;
368 }
369 tc_ptr = code_gen_ptr;
370 tb->tc_ptr = tc_ptr;
371 tb->cs_base = (unsigned long)cs_base;
372 tb->flags = flags;
facc68be 373 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
1376847f
FB
374 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
375
376 /* check next page if needed */
377 virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK;
378 phys_page2 = -1;
379 if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) {
380 phys_page2 = get_phys_addr_code(env, virt_page2);
381 }
382 tb_link_phys(tb, phys_pc, phys_page2);
383
384 found:
36bdbe54
FB
385 if (tb_invalidated_flag) {
386 /* as some TB could have been invalidated because
387 of memory exceptions while generating the code, we
388 must recompute the hash index here */
389 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
390 while (*ptb != NULL)
391 ptb = &(*ptb)->hash_next;
392 T0 = 0;
393 }
1376847f 394 /* we add the TB in the virtual pc hash table */
3fb2ded1
FB
395 *ptb = tb;
396 tb->hash_next = NULL;
397 tb_link(tb);
25eb4484 398 spin_unlock(&tb_lock);
9de5e440 399 }
9d27abd9 400#ifdef DEBUG_EXEC
f193c797 401 if (loglevel & CPU_LOG_EXEC) {
3fb2ded1
FB
402 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
403 (long)tb->tc_ptr, (long)tb->pc,
404 lookup_symbol((void *)tb->pc));
405 }
9d27abd9 406#endif
8c6939c0 407#ifdef __sparc__
3fb2ded1 408 T0 = tmp_T0;
8c6939c0 409#endif
facc68be 410 /* see if we can patch the calling TB. */
bf3e8bf1
FB
411 if (T0 != 0
412#if defined(TARGET_I386) && defined(USE_CODE_COPY)
413 && (tb->cflags & CF_CODE_COPY) ==
414 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
415#endif
416 ) {
3fb2ded1
FB
417 spin_lock(&tb_lock);
418 tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
97eb5b14
FB
419#if defined(USE_CODE_COPY)
420 /* propagates the FP use info */
421 ((TranslationBlock *)(T0 & ~3))->cflags |=
422 (tb->cflags & CF_FP_USED);
423#endif
3fb2ded1
FB
424 spin_unlock(&tb_lock);
425 }
3fb2ded1 426 tc_ptr = tb->tc_ptr;
83479e77 427 env->current_tb = tb;
3fb2ded1
FB
428 /* execute the generated code */
429 gen_func = (void *)tc_ptr;
8c6939c0 430#if defined(__sparc__)
3fb2ded1
FB
431 __asm__ __volatile__("call %0\n\t"
432 "mov %%o7,%%i0"
433 : /* no outputs */
434 : "r" (gen_func)
435 : "i0", "i1", "i2", "i3", "i4", "i5");
8c6939c0 436#elif defined(__arm__)
3fb2ded1
FB
437 asm volatile ("mov pc, %0\n\t"
438 ".global exec_loop\n\t"
439 "exec_loop:\n\t"
440 : /* no outputs */
441 : "r" (gen_func)
442 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bf3e8bf1
FB
443#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
444{
445 if (!(tb->cflags & CF_CODE_COPY)) {
97eb5b14
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446 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
447 save_native_fp_state(env);
448 }
bf3e8bf1
FB
449 gen_func();
450 } else {
97eb5b14
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451 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
452 restore_native_fp_state(env);
453 }
bf3e8bf1
FB
454 /* we work with native eflags */
455 CC_SRC = cc_table[CC_OP].compute_all();
456 CC_OP = CC_OP_EFLAGS;
457 asm(".globl exec_loop\n"
458 "\n"
459 "debug1:\n"
460 " pushl %%ebp\n"
461 " fs movl %10, %9\n"
462 " fs movl %11, %%eax\n"
463 " andl $0x400, %%eax\n"
464 " fs orl %8, %%eax\n"
465 " pushl %%eax\n"
466 " popf\n"
467 " fs movl %%esp, %12\n"
468 " fs movl %0, %%eax\n"
469 " fs movl %1, %%ecx\n"
470 " fs movl %2, %%edx\n"
471 " fs movl %3, %%ebx\n"
472 " fs movl %4, %%esp\n"
473 " fs movl %5, %%ebp\n"
474 " fs movl %6, %%esi\n"
475 " fs movl %7, %%edi\n"
476 " fs jmp *%9\n"
477 "exec_loop:\n"
478 " fs movl %%esp, %4\n"
479 " fs movl %12, %%esp\n"
480 " fs movl %%eax, %0\n"
481 " fs movl %%ecx, %1\n"
482 " fs movl %%edx, %2\n"
483 " fs movl %%ebx, %3\n"
484 " fs movl %%ebp, %5\n"
485 " fs movl %%esi, %6\n"
486 " fs movl %%edi, %7\n"
487 " pushf\n"
488 " popl %%eax\n"
489 " movl %%eax, %%ecx\n"
490 " andl $0x400, %%ecx\n"
491 " shrl $9, %%ecx\n"
492 " andl $0x8d5, %%eax\n"
493 " fs movl %%eax, %8\n"
494 " movl $1, %%eax\n"
495 " subl %%ecx, %%eax\n"
496 " fs movl %%eax, %11\n"
497 " fs movl %9, %%ebx\n" /* get T0 value */
498 " popl %%ebp\n"
499 :
500 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
501 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
502 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
503 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
504 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
505 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
506 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
507 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
508 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
509 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
510 "a" (gen_func),
511 "m" (*(uint8_t *)offsetof(CPUState, df)),
512 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
513 : "%ecx", "%edx"
514 );
515 }
516}
ae228531 517#else
3fb2ded1 518 gen_func();
ae228531 519#endif
83479e77 520 env->current_tb = NULL;
4cbf74b6
FB
521 /* reset soft MMU for next block (it can currently
522 only be set by a memory fault) */
523#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316
FB
524 if (env->hflags & HF_SOFTMMU_MASK) {
525 env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6
FB
526 /* do not allow linking to another block */
527 T0 = 0;
528 }
529#endif
3fb2ded1
FB
530 }
531 } else {
7d13299d 532 }
3fb2ded1
FB
533 } /* for(;;) */
534
7d13299d 535
e4533c7a 536#if defined(TARGET_I386)
97eb5b14
FB
537#if defined(USE_CODE_COPY)
538 if (env->native_fp_regs) {
539 save_native_fp_state(env);
540 }
541#endif
9de5e440 542 /* restore flags in standard format */
fc2b4c48 543 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
9de5e440 544
7d13299d 545 /* restore global registers */
04369ff2
FB
546#ifdef reg_EAX
547 EAX = saved_EAX;
548#endif
549#ifdef reg_ECX
550 ECX = saved_ECX;
551#endif
552#ifdef reg_EDX
553 EDX = saved_EDX;
554#endif
555#ifdef reg_EBX
556 EBX = saved_EBX;
557#endif
558#ifdef reg_ESP
559 ESP = saved_ESP;
560#endif
561#ifdef reg_EBP
562 EBP = saved_EBP;
563#endif
564#ifdef reg_ESI
565 ESI = saved_ESI;
566#endif
567#ifdef reg_EDI
568 EDI = saved_EDI;
8c6939c0 569#endif
e4533c7a 570#elif defined(TARGET_ARM)
1b21b62a 571 env->cpsr = compute_cpsr();
93ac68bc 572#elif defined(TARGET_SPARC)
67867308 573#elif defined(TARGET_PPC)
e4533c7a
FB
574#else
575#error unsupported target CPU
576#endif
8c6939c0
FB
577#ifdef __sparc__
578 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2 579#endif
7d13299d
FB
580 T0 = saved_T0;
581 T1 = saved_T1;
e4533c7a 582 T2 = saved_T2;
7d13299d
FB
583 env = saved_env;
584 return ret;
585}
6dbad63e 586
fbf9eeb3
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587/* must only be called from the generated code as an exception can be
588 generated */
589void tb_invalidate_page_range(target_ulong start, target_ulong end)
590{
591 target_ulong phys_addr;
592 phys_addr = get_phys_addr_code(env, start);
593 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
594}
595
1a18c71b 596#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 597
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598void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
599{
600 CPUX86State *saved_env;
601
602 saved_env = env;
603 env = s;
a412ac57 604 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 605 selector &= 0xffff;
2e255c6b
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606 cpu_x86_load_seg_cache(env, seg_reg, selector,
607 (uint8_t *)(selector << 4), 0xffff, 0);
a513fe19 608 } else {
b453b70b 609 load_seg(seg_reg, selector);
a513fe19 610 }
6dbad63e
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611 env = saved_env;
612}
9de5e440 613
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614void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
615{
616 CPUX86State *saved_env;
617
618 saved_env = env;
619 env = s;
620
621 helper_fsave(ptr, data32);
622
623 env = saved_env;
624}
625
626void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
627{
628 CPUX86State *saved_env;
629
630 saved_env = env;
631 env = s;
632
633 helper_frstor(ptr, data32);
634
635 env = saved_env;
636}
637
e4533c7a
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638#endif /* TARGET_I386 */
639
67b915a5
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640#if !defined(CONFIG_SOFTMMU)
641
3fb2ded1
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642#if defined(TARGET_I386)
643
b56dad1c 644/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
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645 the effective address of the memory exception. 'is_write' is 1 if a
646 write caused the exception and otherwise 0'. 'old_set' is the
647 signal set which should be restored */
2b413144 648static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
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649 int is_write, sigset_t *old_set,
650 void *puc)
9de5e440 651{
a513fe19
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652 TranslationBlock *tb;
653 int ret;
68a79315 654
83479e77
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655 if (cpu_single_env)
656 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 657#if defined(DEBUG_SIGNAL)
bf3e8bf1
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658 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
659 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 660#endif
25eb4484 661 /* XXX: locking issue */
fbf9eeb3 662 if (is_write && page_unprotect(address, pc, puc)) {
fd6ce8f6
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663 return 1;
664 }
fbf9eeb3 665
3fb2ded1 666 /* see if it is an MMU fault */
93a40ea9
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667 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
668 ((env->hflags & HF_CPL_MASK) == 3), 0);
3fb2ded1
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669 if (ret < 0)
670 return 0; /* not an MMU fault */
671 if (ret == 0)
672 return 1; /* the MMU fault was handled without causing real CPU fault */
673 /* now we have a real cpu fault */
a513fe19
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674 tb = tb_find_pc(pc);
675 if (tb) {
9de5e440
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676 /* the PC is inside the translated code. It means that we have
677 a virtual CPU fault */
bf3e8bf1 678 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 679 }
4cbf74b6 680 if (ret == 1) {
3fb2ded1 681#if 0
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682 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
683 env->eip, env->cr[2], env->error_code);
3fb2ded1 684#endif
4cbf74b6
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685 /* we restore the process signal mask as the sigreturn should
686 do it (XXX: use sigsetjmp) */
687 sigprocmask(SIG_SETMASK, old_set, NULL);
688 raise_exception_err(EXCP0E_PAGE, env->error_code);
689 } else {
690 /* activate soft MMU for this block */
3f337316 691 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 692 cpu_resume_from_signal(env, puc);
4cbf74b6 693 }
3fb2ded1
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694 /* never comes here */
695 return 1;
696}
697
e4533c7a 698#elif defined(TARGET_ARM)
3fb2ded1 699static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
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700 int is_write, sigset_t *old_set,
701 void *puc)
3fb2ded1
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702{
703 /* XXX: do more */
704 return 0;
705}
93ac68bc
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706#elif defined(TARGET_SPARC)
707static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
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708 int is_write, sigset_t *old_set,
709 void *puc)
93ac68bc 710{
b453b70b 711 /* XXX: locking issue */
fbf9eeb3 712 if (is_write && page_unprotect(address, pc, puc)) {
b453b70b
FB
713 return 1;
714 }
715 return 0;
93ac68bc 716}
67867308
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717#elif defined (TARGET_PPC)
718static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB
719 int is_write, sigset_t *old_set,
720 void *puc)
67867308
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721{
722 TranslationBlock *tb;
ce09776b 723 int ret;
67867308 724
ce09776b 725#if 1
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726 if (cpu_single_env)
727 env = cpu_single_env; /* XXX: find a correct solution for multithread */
728#endif
729#if defined(DEBUG_SIGNAL)
730 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
731 pc, address, is_write, *(unsigned long *)old_set);
732#endif
733 /* XXX: locking issue */
fbf9eeb3 734 if (is_write && page_unprotect(address, pc, puc)) {
67867308
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735 return 1;
736 }
737
ce09776b 738 /* see if it is an MMU fault */
7f957d28 739 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
ce09776b
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740 if (ret < 0)
741 return 0; /* not an MMU fault */
742 if (ret == 0)
743 return 1; /* the MMU fault was handled without causing real CPU fault */
744
67867308
FB
745 /* now we have a real cpu fault */
746 tb = tb_find_pc(pc);
747 if (tb) {
748 /* the PC is inside the translated code. It means that we have
749 a virtual CPU fault */
bf3e8bf1 750 cpu_restore_state(tb, env, pc, puc);
67867308 751 }
ce09776b 752 if (ret == 1) {
67867308 753#if 0
ce09776b
FB
754 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
755 env->nip, env->error_code, tb);
67867308
FB
756#endif
757 /* we restore the process signal mask as the sigreturn should
758 do it (XXX: use sigsetjmp) */
bf3e8bf1 759 sigprocmask(SIG_SETMASK, old_set, NULL);
ce09776b
FB
760 do_queue_exception_err(env->exception_index, env->error_code);
761 } else {
762 /* activate soft MMU for this block */
fbf9eeb3 763 cpu_resume_from_signal(env, puc);
ce09776b 764 }
67867308
FB
765 /* never comes here */
766 return 1;
767}
e4533c7a
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768#else
769#error unsupported target CPU
770#endif
9de5e440 771
2b413144
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772#if defined(__i386__)
773
bf3e8bf1
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774#if defined(USE_CODE_COPY)
775static void cpu_send_trap(unsigned long pc, int trap,
776 struct ucontext *uc)
777{
778 TranslationBlock *tb;
779
780 if (cpu_single_env)
781 env = cpu_single_env; /* XXX: find a correct solution for multithread */
782 /* now we have a real cpu fault */
783 tb = tb_find_pc(pc);
784 if (tb) {
785 /* the PC is inside the translated code. It means that we have
786 a virtual CPU fault */
787 cpu_restore_state(tb, env, pc, uc);
788 }
789 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
790 raise_exception_err(trap, env->error_code);
791}
792#endif
793
e4533c7a
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794int cpu_signal_handler(int host_signum, struct siginfo *info,
795 void *puc)
9de5e440 796{
9de5e440
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797 struct ucontext *uc = puc;
798 unsigned long pc;
bf3e8bf1 799 int trapno;
97eb5b14 800
d691f669
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801#ifndef REG_EIP
802/* for glibc 2.1 */
fd6ce8f6
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803#define REG_EIP EIP
804#define REG_ERR ERR
805#define REG_TRAPNO TRAPNO
d691f669 806#endif
fc2b4c48 807 pc = uc->uc_mcontext.gregs[REG_EIP];
bf3e8bf1
FB
808 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
809#if defined(TARGET_I386) && defined(USE_CODE_COPY)
810 if (trapno == 0x00 || trapno == 0x05) {
811 /* send division by zero or bound exception */
812 cpu_send_trap(pc, trapno, uc);
813 return 1;
814 } else
815#endif
816 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
817 trapno == 0xe ?
818 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
819 &uc->uc_sigmask, puc);
2b413144
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820}
821
bc51c5c9
FB
822#elif defined(__x86_64__)
823
824int cpu_signal_handler(int host_signum, struct siginfo *info,
825 void *puc)
826{
827 struct ucontext *uc = puc;
828 unsigned long pc;
829
830 pc = uc->uc_mcontext.gregs[REG_RIP];
831 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
832 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
833 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
834 &uc->uc_sigmask, puc);
835}
836
25eb4484 837#elif defined(__powerpc)
2b413144 838
e4533c7a
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839int cpu_signal_handler(int host_signum, struct siginfo *info,
840 void *puc)
2b413144 841{
25eb4484
FB
842 struct ucontext *uc = puc;
843 struct pt_regs *regs = uc->uc_mcontext.regs;
844 unsigned long pc;
25eb4484
FB
845 int is_write;
846
847 pc = regs->nip;
25eb4484
FB
848 is_write = 0;
849#if 0
850 /* ppc 4xx case */
851 if (regs->dsisr & 0x00800000)
852 is_write = 1;
853#else
854 if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
855 is_write = 1;
856#endif
857 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 858 is_write, &uc->uc_sigmask, puc);
2b413144
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859}
860
2f87c607
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861#elif defined(__alpha__)
862
e4533c7a 863int cpu_signal_handler(int host_signum, struct siginfo *info,
2f87c607
FB
864 void *puc)
865{
866 struct ucontext *uc = puc;
867 uint32_t *pc = uc->uc_mcontext.sc_pc;
868 uint32_t insn = *pc;
869 int is_write = 0;
870
8c6939c0 871 /* XXX: need kernel patch to get write flag faster */
2f87c607
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872 switch (insn >> 26) {
873 case 0x0d: // stw
874 case 0x0e: // stb
875 case 0x0f: // stq_u
876 case 0x24: // stf
877 case 0x25: // stg
878 case 0x26: // sts
879 case 0x27: // stt
880 case 0x2c: // stl
881 case 0x2d: // stq
882 case 0x2e: // stl_c
883 case 0x2f: // stq_c
884 is_write = 1;
885 }
886
887 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 888 is_write, &uc->uc_sigmask, puc);
2f87c607 889}
8c6939c0
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890#elif defined(__sparc__)
891
e4533c7a
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892int cpu_signal_handler(int host_signum, struct siginfo *info,
893 void *puc)
8c6939c0
FB
894{
895 uint32_t *regs = (uint32_t *)(info + 1);
896 void *sigmask = (regs + 20);
897 unsigned long pc;
898 int is_write;
899 uint32_t insn;
900
901 /* XXX: is there a standard glibc define ? */
902 pc = regs[1];
903 /* XXX: need kernel patch to get write flag faster */
904 is_write = 0;
905 insn = *(uint32_t *)pc;
906 if ((insn >> 30) == 3) {
907 switch((insn >> 19) & 0x3f) {
908 case 0x05: // stb
909 case 0x06: // sth
910 case 0x04: // st
911 case 0x07: // std
912 case 0x24: // stf
913 case 0x27: // stdf
914 case 0x25: // stfsr
915 is_write = 1;
916 break;
917 }
918 }
919 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 920 is_write, sigmask, NULL);
8c6939c0
FB
921}
922
923#elif defined(__arm__)
924
e4533c7a
FB
925int cpu_signal_handler(int host_signum, struct siginfo *info,
926 void *puc)
8c6939c0
FB
927{
928 struct ucontext *uc = puc;
929 unsigned long pc;
930 int is_write;
931
932 pc = uc->uc_mcontext.gregs[R15];
933 /* XXX: compute is_write */
934 is_write = 0;
935 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
936 is_write,
937 &uc->uc_sigmask);
938}
939
38e584a0
FB
940#elif defined(__mc68000)
941
942int cpu_signal_handler(int host_signum, struct siginfo *info,
943 void *puc)
944{
945 struct ucontext *uc = puc;
946 unsigned long pc;
947 int is_write;
948
949 pc = uc->uc_mcontext.gregs[16];
950 /* XXX: compute is_write */
951 is_write = 0;
952 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
953 is_write,
bf3e8bf1 954 &uc->uc_sigmask, puc);
38e584a0
FB
955}
956
9de5e440 957#else
2b413144 958
3fb2ded1 959#error host CPU specific signal handler needed
2b413144 960
9de5e440 961#endif
67b915a5
FB
962
963#endif /* !defined(CONFIG_SOFTMMU) */
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