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96d0e26c WG |
1 | /* |
2 | * NUMA parameter parsing routines | |
3 | * | |
4 | * Copyright (c) 2014 Fujitsu Ltd. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
d38ea87a | 25 | #include "qemu/osdep.h" |
e35704ba | 26 | #include "sysemu/numa.h" |
96d0e26c | 27 | #include "exec/cpu-common.h" |
0987d735 | 28 | #include "exec/ramlist.h" |
96d0e26c WG |
29 | #include "qemu/bitmap.h" |
30 | #include "qom/cpu.h" | |
2b631ec2 WG |
31 | #include "qemu/error-report.h" |
32 | #include "include/exec/cpu-common.h" /* for RAM_ADDR_FMT */ | |
0042109a WG |
33 | #include "qapi-visit.h" |
34 | #include "qapi/opts-visitor.h" | |
dfabb8b9 | 35 | #include "hw/boards.h" |
7febe36f | 36 | #include "sysemu/hostmem.h" |
76b5d850 | 37 | #include "qmp-commands.h" |
5b009e40 | 38 | #include "hw/mem/pc-dimm.h" |
7dcd1d70 EH |
39 | #include "qemu/option.h" |
40 | #include "qemu/config-file.h" | |
0042109a WG |
41 | |
42 | QemuOptsList qemu_numa_opts = { | |
43 | .name = "numa", | |
44 | .implied_opt_name = "type", | |
45 | .head = QTAILQ_HEAD_INITIALIZER(qemu_numa_opts.head), | |
46 | .desc = { { 0 } } /* validated with OptsVisitor */ | |
47 | }; | |
48 | ||
7febe36f | 49 | static int have_memdevs = -1; |
25712ffe EH |
50 | static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one. |
51 | * For all nodes, nodeid < max_numa_nodeid | |
52 | */ | |
de1a7c84 | 53 | int nb_numa_nodes; |
0f203430 | 54 | bool have_numa_distance; |
de1a7c84 | 55 | NodeInfo numa_info[MAX_NODES]; |
7febe36f | 56 | |
fa9ea81d BR |
57 | void numa_set_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node) |
58 | { | |
672558d2 | 59 | struct numa_addr_range *range; |
fa9ea81d | 60 | |
abafabd8 BR |
61 | /* |
62 | * Memory-less nodes can come here with 0 size in which case, | |
63 | * there is nothing to do. | |
64 | */ | |
65 | if (!size) { | |
66 | return; | |
67 | } | |
68 | ||
672558d2 | 69 | range = g_malloc0(sizeof(*range)); |
fa9ea81d BR |
70 | range->mem_start = addr; |
71 | range->mem_end = addr + size - 1; | |
72 | QLIST_INSERT_HEAD(&numa_info[node].addr, range, entry); | |
73 | } | |
74 | ||
75 | void numa_unset_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node) | |
76 | { | |
77 | struct numa_addr_range *range, *next; | |
78 | ||
79 | QLIST_FOREACH_SAFE(range, &numa_info[node].addr, entry, next) { | |
80 | if (addr == range->mem_start && (addr + size - 1) == range->mem_end) { | |
81 | QLIST_REMOVE(range, entry); | |
82 | g_free(range); | |
83 | return; | |
84 | } | |
85 | } | |
86 | } | |
87 | ||
abafabd8 BR |
88 | static void numa_set_mem_ranges(void) |
89 | { | |
90 | int i; | |
91 | ram_addr_t mem_start = 0; | |
92 | ||
93 | /* | |
94 | * Deduce start address of each node and use it to store | |
95 | * the address range info in numa_info address range list | |
96 | */ | |
97 | for (i = 0; i < nb_numa_nodes; i++) { | |
98 | numa_set_mem_node_id(mem_start, numa_info[i].node_mem, i); | |
99 | mem_start += numa_info[i].node_mem; | |
100 | } | |
101 | } | |
102 | ||
e75e2a14 BR |
103 | /* |
104 | * Check if @addr falls under NUMA @node. | |
105 | */ | |
106 | static bool numa_addr_belongs_to_node(ram_addr_t addr, uint32_t node) | |
107 | { | |
108 | struct numa_addr_range *range; | |
109 | ||
110 | QLIST_FOREACH(range, &numa_info[node].addr, entry) { | |
111 | if (addr >= range->mem_start && addr <= range->mem_end) { | |
112 | return true; | |
113 | } | |
114 | } | |
115 | return false; | |
116 | } | |
117 | ||
118 | /* | |
119 | * Given an address, return the index of the NUMA node to which the | |
120 | * address belongs to. | |
121 | */ | |
122 | uint32_t numa_get_node(ram_addr_t addr, Error **errp) | |
123 | { | |
124 | uint32_t i; | |
125 | ||
126 | /* For non NUMA configurations, check if the addr falls under node 0 */ | |
127 | if (!nb_numa_nodes) { | |
128 | if (numa_addr_belongs_to_node(addr, 0)) { | |
129 | return 0; | |
130 | } | |
131 | } | |
132 | ||
133 | for (i = 0; i < nb_numa_nodes; i++) { | |
134 | if (numa_addr_belongs_to_node(addr, i)) { | |
135 | return i; | |
136 | } | |
137 | } | |
138 | ||
139 | error_setg(errp, "Address 0x" RAM_ADDR_FMT " doesn't belong to any " | |
140 | "NUMA node", addr); | |
141 | return -1; | |
142 | } | |
143 | ||
64c2a8f6 IM |
144 | static void parse_numa_node(MachineState *ms, NumaNodeOptions *node, |
145 | QemuOpts *opts, Error **errp) | |
96d0e26c | 146 | { |
0042109a WG |
147 | uint16_t nodenr; |
148 | uint16List *cpus = NULL; | |
64c2a8f6 | 149 | MachineClass *mc = MACHINE_GET_CLASS(ms); |
96d0e26c | 150 | |
0042109a WG |
151 | if (node->has_nodeid) { |
152 | nodenr = node->nodeid; | |
96d0e26c | 153 | } else { |
0042109a | 154 | nodenr = nb_numa_nodes; |
96d0e26c WG |
155 | } |
156 | ||
0042109a WG |
157 | if (nodenr >= MAX_NODES) { |
158 | error_setg(errp, "Max number of NUMA nodes reached: %" | |
01bbbcf4 | 159 | PRIu16 "", nodenr); |
0042109a | 160 | return; |
96d0e26c WG |
161 | } |
162 | ||
1945b9d8 EH |
163 | if (numa_info[nodenr].present) { |
164 | error_setg(errp, "Duplicate NUMA nodeid: %" PRIu16, nodenr); | |
165 | return; | |
166 | } | |
167 | ||
64c2a8f6 IM |
168 | if (!mc->cpu_index_to_instance_props) { |
169 | error_report("NUMA is not supported by this machine-type"); | |
170 | exit(1); | |
171 | } | |
0042109a | 172 | for (cpus = node->cpus; cpus; cpus = cpus->next) { |
7c88e65d | 173 | CpuInstanceProperties props; |
8979c945 EH |
174 | if (cpus->value >= max_cpus) { |
175 | error_setg(errp, | |
176 | "CPU index (%" PRIu16 ")" | |
177 | " should be smaller than maxcpus (%d)", | |
178 | cpus->value, max_cpus); | |
0042109a WG |
179 | return; |
180 | } | |
7c88e65d IM |
181 | props = mc->cpu_index_to_instance_props(ms, cpus->value); |
182 | props.node_id = nodenr; | |
183 | props.has_node_id = true; | |
184 | machine_set_cpu_numa_node(ms, &props, &error_fatal); | |
96d0e26c WG |
185 | } |
186 | ||
7febe36f | 187 | if (node->has_mem && node->has_memdev) { |
d0e31a10 | 188 | error_setg(errp, "cannot specify both mem= and memdev="); |
7febe36f PB |
189 | return; |
190 | } | |
191 | ||
192 | if (have_memdevs == -1) { | |
193 | have_memdevs = node->has_memdev; | |
194 | } | |
195 | if (node->has_memdev != have_memdevs) { | |
d0e31a10 | 196 | error_setg(errp, "memdev option must be specified for either " |
01bbbcf4 | 197 | "all or no nodes"); |
7febe36f PB |
198 | return; |
199 | } | |
200 | ||
0042109a WG |
201 | if (node->has_mem) { |
202 | uint64_t mem_size = node->mem; | |
203 | const char *mem_str = qemu_opt_get(opts, "mem"); | |
204 | /* Fix up legacy suffix-less format */ | |
205 | if (g_ascii_isdigit(mem_str[strlen(mem_str) - 1])) { | |
206 | mem_size <<= 20; | |
207 | } | |
208 | numa_info[nodenr].node_mem = mem_size; | |
209 | } | |
7febe36f PB |
210 | if (node->has_memdev) { |
211 | Object *o; | |
212 | o = object_resolve_path_type(node->memdev, TYPE_MEMORY_BACKEND, NULL); | |
213 | if (!o) { | |
214 | error_setg(errp, "memdev=%s is ambiguous", node->memdev); | |
215 | return; | |
216 | } | |
217 | ||
218 | object_ref(o); | |
219 | numa_info[nodenr].node_mem = object_property_get_int(o, "size", NULL); | |
220 | numa_info[nodenr].node_memdev = MEMORY_BACKEND(o); | |
221 | } | |
1af878e0 EH |
222 | numa_info[nodenr].present = true; |
223 | max_numa_nodeid = MAX(max_numa_nodeid, nodenr + 1); | |
96d0e26c WG |
224 | } |
225 | ||
0f203430 HC |
226 | static void parse_numa_distance(NumaDistOptions *dist, Error **errp) |
227 | { | |
228 | uint16_t src = dist->src; | |
229 | uint16_t dst = dist->dst; | |
230 | uint8_t val = dist->val; | |
231 | ||
232 | if (src >= MAX_NODES || dst >= MAX_NODES) { | |
233 | error_setg(errp, | |
234 | "Invalid node %" PRIu16 | |
235 | ", max possible could be %" PRIu16, | |
236 | MAX(src, dst), MAX_NODES); | |
237 | return; | |
238 | } | |
239 | ||
240 | if (!numa_info[src].present || !numa_info[dst].present) { | |
241 | error_setg(errp, "Source/Destination NUMA node is missing. " | |
242 | "Please use '-numa node' option to declare it first."); | |
243 | return; | |
244 | } | |
245 | ||
246 | if (val < NUMA_DISTANCE_MIN) { | |
247 | error_setg(errp, "NUMA distance (%" PRIu8 ") is invalid, " | |
248 | "it shouldn't be less than %d.", | |
249 | val, NUMA_DISTANCE_MIN); | |
250 | return; | |
251 | } | |
252 | ||
253 | if (src == dst && val != NUMA_DISTANCE_MIN) { | |
254 | error_setg(errp, "Local distance of node %d should be %d.", | |
255 | src, NUMA_DISTANCE_MIN); | |
256 | return; | |
257 | } | |
258 | ||
259 | numa_info[src].distance[dst] = val; | |
260 | have_numa_distance = true; | |
261 | } | |
262 | ||
28d0de7a | 263 | static int parse_numa(void *opaque, QemuOpts *opts, Error **errp) |
96d0e26c | 264 | { |
0042109a | 265 | NumaOptions *object = NULL; |
64c2a8f6 | 266 | MachineState *ms = opaque; |
0042109a | 267 | Error *err = NULL; |
96d0e26c | 268 | |
0042109a | 269 | { |
09204eac EB |
270 | Visitor *v = opts_visitor_new(opts); |
271 | visit_type_NumaOptions(v, NULL, &object, &err); | |
272 | visit_free(v); | |
96d0e26c | 273 | } |
96d0e26c | 274 | |
0042109a | 275 | if (err) { |
157e94e8 | 276 | goto end; |
0042109a | 277 | } |
96d0e26c | 278 | |
1fd5d4fe | 279 | switch (object->type) { |
d081a49a | 280 | case NUMA_OPTIONS_TYPE_NODE: |
64c2a8f6 | 281 | parse_numa_node(ms, &object->u.node, opts, &err); |
0042109a | 282 | if (err) { |
157e94e8 | 283 | goto end; |
96d0e26c | 284 | } |
0042109a WG |
285 | nb_numa_nodes++; |
286 | break; | |
0f203430 HC |
287 | case NUMA_OPTIONS_TYPE_DIST: |
288 | parse_numa_distance(&object->u.dist, &err); | |
289 | if (err) { | |
290 | goto end; | |
291 | } | |
292 | break; | |
419fcdec IM |
293 | case NUMA_OPTIONS_TYPE_CPU: |
294 | if (!object->u.cpu.has_node_id) { | |
295 | error_setg(&err, "Missing mandatory node-id property"); | |
296 | goto end; | |
297 | } | |
298 | if (!numa_info[object->u.cpu.node_id].present) { | |
299 | error_setg(&err, "Invalid node-id=%" PRId64 ", NUMA node must be " | |
300 | "defined with -numa node,nodeid=ID before it's used with " | |
301 | "-numa cpu,node-id=ID", object->u.cpu.node_id); | |
302 | goto end; | |
303 | } | |
304 | ||
305 | machine_set_cpu_numa_node(ms, qapi_NumaCpuOptions_base(&object->u.cpu), | |
306 | &err); | |
307 | break; | |
0042109a WG |
308 | default: |
309 | abort(); | |
310 | } | |
96d0e26c | 311 | |
157e94e8 | 312 | end: |
96a1616c | 313 | qapi_free_NumaOptions(object); |
157e94e8 MAL |
314 | if (err) { |
315 | error_report_err(err); | |
316 | return -1; | |
317 | } | |
0042109a | 318 | |
157e94e8 | 319 | return 0; |
96d0e26c WG |
320 | } |
321 | ||
0f203430 HC |
322 | /* If all node pair distances are symmetric, then only distances |
323 | * in one direction are enough. If there is even one asymmetric | |
324 | * pair, though, then all distances must be provided. The | |
325 | * distance from a node to itself is always NUMA_DISTANCE_MIN, | |
326 | * so providing it is never necessary. | |
327 | */ | |
328 | static void validate_numa_distance(void) | |
3ef71975 | 329 | { |
0f203430 HC |
330 | int src, dst; |
331 | bool is_asymmetrical = false; | |
332 | ||
333 | for (src = 0; src < nb_numa_nodes; src++) { | |
334 | for (dst = src; dst < nb_numa_nodes; dst++) { | |
335 | if (numa_info[src].distance[dst] == 0 && | |
336 | numa_info[dst].distance[src] == 0) { | |
337 | if (src != dst) { | |
338 | error_report("The distance between node %d and %d is " | |
339 | "missing, at least one distance value " | |
340 | "between each nodes should be provided.", | |
341 | src, dst); | |
342 | exit(EXIT_FAILURE); | |
343 | } | |
344 | } | |
3ef71975 | 345 | |
0f203430 HC |
346 | if (numa_info[src].distance[dst] != 0 && |
347 | numa_info[dst].distance[src] != 0 && | |
348 | numa_info[src].distance[dst] != | |
349 | numa_info[dst].distance[src]) { | |
350 | is_asymmetrical = true; | |
351 | } | |
352 | } | |
353 | } | |
354 | ||
355 | if (is_asymmetrical) { | |
356 | for (src = 0; src < nb_numa_nodes; src++) { | |
357 | for (dst = 0; dst < nb_numa_nodes; dst++) { | |
358 | if (src != dst && numa_info[src].distance[dst] == 0) { | |
359 | error_report("At least one asymmetrical pair of " | |
360 | "distances is given, please provide distances " | |
361 | "for both directions of all node pairs."); | |
362 | exit(EXIT_FAILURE); | |
363 | } | |
364 | } | |
365 | } | |
3ef71975 | 366 | } |
3ef71975 EH |
367 | } |
368 | ||
0f203430 | 369 | static void complete_init_numa_distance(void) |
3ef71975 | 370 | { |
0f203430 | 371 | int src, dst; |
3ef71975 | 372 | |
0f203430 HC |
373 | /* Fixup NUMA distance by symmetric policy because if it is an |
374 | * asymmetric distance table, it should be a complete table and | |
375 | * there would not be any missing distance except local node, which | |
376 | * is verified by validate_numa_distance above. | |
377 | */ | |
378 | for (src = 0; src < nb_numa_nodes; src++) { | |
379 | for (dst = 0; dst < nb_numa_nodes; dst++) { | |
380 | if (numa_info[src].distance[dst] == 0) { | |
381 | if (src == dst) { | |
382 | numa_info[src].distance[dst] = NUMA_DISTANCE_MIN; | |
383 | } else { | |
384 | numa_info[src].distance[dst] = numa_info[dst].distance[src]; | |
385 | } | |
386 | } | |
3ef71975 | 387 | } |
3ef71975 | 388 | } |
0f203430 | 389 | } |
549fc54b | 390 | |
3bfe5716 LV |
391 | void numa_legacy_auto_assign_ram(MachineClass *mc, NodeInfo *nodes, |
392 | int nb_nodes, ram_addr_t size) | |
393 | { | |
394 | int i; | |
395 | uint64_t usedmem = 0; | |
396 | ||
397 | /* Align each node according to the alignment | |
398 | * requirements of the machine class | |
399 | */ | |
400 | ||
401 | for (i = 0; i < nb_nodes - 1; i++) { | |
402 | nodes[i].node_mem = (size / nb_nodes) & | |
403 | ~((1 << mc->numa_mem_align_shift) - 1); | |
404 | usedmem += nodes[i].node_mem; | |
549fc54b | 405 | } |
3bfe5716 | 406 | nodes[i].node_mem = size - usedmem; |
3ef71975 EH |
407 | } |
408 | ||
3bfe5716 LV |
409 | void numa_default_auto_assign_ram(MachineClass *mc, NodeInfo *nodes, |
410 | int nb_nodes, ram_addr_t size) | |
96d0e26c | 411 | { |
12d6e464 | 412 | int i; |
3bfe5716 LV |
413 | uint64_t usedmem = 0, node_mem; |
414 | uint64_t granularity = size / nb_nodes; | |
415 | uint64_t propagate = 0; | |
416 | ||
417 | for (i = 0; i < nb_nodes - 1; i++) { | |
418 | node_mem = (granularity + propagate) & | |
419 | ~((1 << mc->numa_mem_align_shift) - 1); | |
420 | propagate = granularity + propagate - node_mem; | |
421 | nodes[i].node_mem = node_mem; | |
422 | usedmem += node_mem; | |
423 | } | |
424 | nodes[i].node_mem = size - usedmem; | |
425 | } | |
12d6e464 | 426 | |
ea089eeb | 427 | void parse_numa_opts(MachineState *ms) |
96d0e26c | 428 | { |
12d6e464 | 429 | int i; |
af9b20e8 | 430 | const CPUArchIdList *possible_cpus; |
ea089eeb | 431 | MachineClass *mc = MACHINE_GET_CLASS(ms); |
cdda2018 | 432 | |
64c2a8f6 | 433 | if (qemu_opts_foreach(qemu_find_opts("numa"), parse_numa, ms, NULL)) { |
7dcd1d70 EH |
434 | exit(1); |
435 | } | |
436 | ||
12d6e464 EH |
437 | assert(max_numa_nodeid <= MAX_NODES); |
438 | ||
439 | /* No support for sparse NUMA node IDs yet: */ | |
440 | for (i = max_numa_nodeid - 1; i >= 0; i--) { | |
441 | /* Report large node IDs first, to make mistakes easier to spot */ | |
442 | if (!numa_info[i].present) { | |
443 | error_report("numa: Node ID missing: %d", i); | |
444 | exit(1); | |
445 | } | |
446 | } | |
447 | ||
448 | /* This must be always true if all nodes are present: */ | |
449 | assert(nb_numa_nodes == max_numa_nodeid); | |
450 | ||
96d0e26c | 451 | if (nb_numa_nodes > 0) { |
2b631ec2 | 452 | uint64_t numa_total; |
96d0e26c WG |
453 | |
454 | if (nb_numa_nodes > MAX_NODES) { | |
455 | nb_numa_nodes = MAX_NODES; | |
456 | } | |
457 | ||
9851d0fe | 458 | /* If no memory size is given for any node, assume the default case |
96d0e26c WG |
459 | * and distribute the available memory equally across all nodes |
460 | */ | |
461 | for (i = 0; i < nb_numa_nodes; i++) { | |
8c85901e | 462 | if (numa_info[i].node_mem != 0) { |
96d0e26c WG |
463 | break; |
464 | } | |
465 | } | |
466 | if (i == nb_numa_nodes) { | |
3bfe5716 LV |
467 | assert(mc->numa_auto_assign_ram); |
468 | mc->numa_auto_assign_ram(mc, numa_info, nb_numa_nodes, ram_size); | |
96d0e26c WG |
469 | } |
470 | ||
2b631ec2 WG |
471 | numa_total = 0; |
472 | for (i = 0; i < nb_numa_nodes; i++) { | |
8c85901e | 473 | numa_total += numa_info[i].node_mem; |
2b631ec2 WG |
474 | } |
475 | if (numa_total != ram_size) { | |
c68233ae HT |
476 | error_report("total memory for NUMA nodes (0x%" PRIx64 ")" |
477 | " should equal RAM size (0x" RAM_ADDR_FMT ")", | |
2b631ec2 WG |
478 | numa_total, ram_size); |
479 | exit(1); | |
480 | } | |
481 | ||
fa9ea81d BR |
482 | for (i = 0; i < nb_numa_nodes; i++) { |
483 | QLIST_INIT(&numa_info[i].addr); | |
484 | } | |
485 | ||
abafabd8 BR |
486 | numa_set_mem_ranges(); |
487 | ||
ea089eeb | 488 | /* assign CPUs to nodes using board provided default mapping */ |
af9b20e8 | 489 | if (!mc->cpu_index_to_instance_props || !mc->possible_cpu_arch_ids) { |
ea089eeb IM |
490 | error_report("default CPUs to NUMA node mapping isn't supported"); |
491 | exit(1); | |
492 | } | |
af9b20e8 IM |
493 | |
494 | possible_cpus = mc->possible_cpu_arch_ids(ms); | |
495 | for (i = 0; i < possible_cpus->len; i++) { | |
496 | if (possible_cpus->cpus[i].props.has_node_id) { | |
96d0e26c WG |
497 | break; |
498 | } | |
499 | } | |
af9b20e8 IM |
500 | |
501 | /* no CPUs are assigned to NUMA nodes */ | |
502 | if (i == possible_cpus->len) { | |
96d0e26c | 503 | for (i = 0; i < max_cpus; i++) { |
ea089eeb | 504 | CpuInstanceProperties props; |
7c88e65d | 505 | /* fetch default mapping from board and enable it */ |
ea089eeb | 506 | props = mc->cpu_index_to_instance_props(ms, i); |
7c88e65d | 507 | props.has_node_id = true; |
57924bcd | 508 | |
7c88e65d | 509 | machine_set_cpu_numa_node(ms, &props, &error_fatal); |
96d0e26c WG |
510 | } |
511 | } | |
3ef71975 | 512 | |
0f203430 HC |
513 | /* QEMU needs at least all unique node pair distances to build |
514 | * the whole NUMA distance table. QEMU treats the distance table | |
515 | * as symmetric by default, i.e. distance A->B == distance B->A. | |
516 | * Thus, QEMU is able to complete the distance table | |
517 | * initialization even though only distance A->B is provided and | |
518 | * distance B->A is not. QEMU knows the distance of a node to | |
519 | * itself is always 10, so A->A distances may be omitted. When | |
520 | * the distances of two nodes of a pair differ, i.e. distance | |
521 | * A->B != distance B->A, then that means the distance table is | |
522 | * asymmetric. In this case, the distances for both directions | |
523 | * of all node pairs are required. | |
524 | */ | |
525 | if (have_numa_distance) { | |
526 | /* Validate enough NUMA distance information was provided. */ | |
527 | validate_numa_distance(); | |
96d0e26c | 528 | |
0f203430 HC |
529 | /* Validation succeeded, now fill in any missing distances. */ |
530 | complete_init_numa_distance(); | |
96d0e26c | 531 | } |
abafabd8 BR |
532 | } else { |
533 | numa_set_mem_node_id(0, ram_size, 0); | |
96d0e26c WG |
534 | } |
535 | } | |
dfabb8b9 | 536 | |
7febe36f PB |
537 | static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner, |
538 | const char *name, | |
539 | uint64_t ram_size) | |
540 | { | |
0b183fc8 PB |
541 | if (mem_path) { |
542 | #ifdef __linux__ | |
7f56e740 | 543 | Error *err = NULL; |
dbcb8981 | 544 | memory_region_init_ram_from_file(mr, owner, name, ram_size, false, |
7f56e740 | 545 | mem_path, &err); |
c3ba3095 | 546 | if (err) { |
29b762f5 | 547 | error_report_err(err); |
fae947b0 LC |
548 | if (mem_prealloc) { |
549 | exit(1); | |
550 | } | |
551 | ||
552 | /* Legacy behavior: if allocation failed, fall back to | |
553 | * regular RAM allocation. | |
554 | */ | |
f8ed85ac | 555 | memory_region_init_ram(mr, owner, name, ram_size, &error_fatal); |
7f56e740 | 556 | } |
0b183fc8 PB |
557 | #else |
558 | fprintf(stderr, "-mem-path not supported on this host\n"); | |
559 | exit(1); | |
560 | #endif | |
561 | } else { | |
f8ed85ac | 562 | memory_region_init_ram(mr, owner, name, ram_size, &error_fatal); |
0b183fc8 | 563 | } |
7febe36f PB |
564 | vmstate_register_ram_global(mr); |
565 | } | |
566 | ||
dfabb8b9 PB |
567 | void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner, |
568 | const char *name, | |
569 | uint64_t ram_size) | |
570 | { | |
7febe36f PB |
571 | uint64_t addr = 0; |
572 | int i; | |
573 | ||
574 | if (nb_numa_nodes == 0 || !have_memdevs) { | |
575 | allocate_system_memory_nonnuma(mr, owner, name, ram_size); | |
576 | return; | |
577 | } | |
578 | ||
579 | memory_region_init(mr, owner, name, ram_size); | |
580 | for (i = 0; i < MAX_NODES; i++) { | |
7febe36f PB |
581 | uint64_t size = numa_info[i].node_mem; |
582 | HostMemoryBackend *backend = numa_info[i].node_memdev; | |
583 | if (!backend) { | |
584 | continue; | |
585 | } | |
007b0657 MA |
586 | MemoryRegion *seg = host_memory_backend_get_memory(backend, |
587 | &error_fatal); | |
7febe36f | 588 | |
0462faee HT |
589 | if (memory_region_is_mapped(seg)) { |
590 | char *path = object_get_canonical_path_component(OBJECT(backend)); | |
591 | error_report("memory backend %s is used multiple times. Each " | |
592 | "-numa option must use a different memdev value.", | |
593 | path); | |
594 | exit(1); | |
595 | } | |
596 | ||
0b217571 | 597 | host_memory_backend_set_mapped(backend, true); |
7febe36f PB |
598 | memory_region_add_subregion(mr, addr, seg); |
599 | vmstate_register_ram_global(seg); | |
600 | addr += size; | |
601 | } | |
dfabb8b9 | 602 | } |
76b5d850 | 603 | |
5b009e40 HZ |
604 | static void numa_stat_memory_devices(uint64_t node_mem[]) |
605 | { | |
606 | MemoryDeviceInfoList *info_list = NULL; | |
607 | MemoryDeviceInfoList **prev = &info_list; | |
608 | MemoryDeviceInfoList *info; | |
609 | ||
610 | qmp_pc_dimm_device_list(qdev_get_machine(), &prev); | |
611 | for (info = info_list; info; info = info->next) { | |
612 | MemoryDeviceInfo *value = info->value; | |
613 | ||
614 | if (value) { | |
1fd5d4fe | 615 | switch (value->type) { |
5b009e40 | 616 | case MEMORY_DEVICE_INFO_KIND_DIMM: |
32bafa8f | 617 | node_mem[value->u.dimm.data->node] += value->u.dimm.data->size; |
5b009e40 HZ |
618 | break; |
619 | default: | |
620 | break; | |
621 | } | |
622 | } | |
623 | } | |
624 | qapi_free_MemoryDeviceInfoList(info_list); | |
625 | } | |
626 | ||
627 | void query_numa_node_mem(uint64_t node_mem[]) | |
628 | { | |
629 | int i; | |
630 | ||
631 | if (nb_numa_nodes <= 0) { | |
632 | return; | |
633 | } | |
634 | ||
635 | numa_stat_memory_devices(node_mem); | |
636 | for (i = 0; i < nb_numa_nodes; i++) { | |
637 | node_mem[i] += numa_info[i].node_mem; | |
638 | } | |
639 | } | |
640 | ||
76b5d850 HT |
641 | static int query_memdev(Object *obj, void *opaque) |
642 | { | |
643 | MemdevList **list = opaque; | |
b0e90181 | 644 | MemdevList *m = NULL; |
76b5d850 HT |
645 | |
646 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
b0e90181 | 647 | m = g_malloc0(sizeof(*m)); |
76b5d850 HT |
648 | |
649 | m->value = g_malloc0(sizeof(*m->value)); | |
650 | ||
e1ff3c67 IM |
651 | m->value->id = object_property_get_str(obj, "id", NULL); |
652 | m->value->has_id = !!m->value->id; | |
653 | ||
76b5d850 | 654 | m->value->size = object_property_get_int(obj, "size", |
2f6f826e | 655 | &error_abort); |
76b5d850 | 656 | m->value->merge = object_property_get_bool(obj, "merge", |
2f6f826e | 657 | &error_abort); |
76b5d850 | 658 | m->value->dump = object_property_get_bool(obj, "dump", |
2f6f826e | 659 | &error_abort); |
76b5d850 | 660 | m->value->prealloc = object_property_get_bool(obj, |
2f6f826e MA |
661 | "prealloc", |
662 | &error_abort); | |
76b5d850 HT |
663 | m->value->policy = object_property_get_enum(obj, |
664 | "policy", | |
a3590dac | 665 | "HostMemPolicy", |
2f6f826e | 666 | &error_abort); |
76b5d850 | 667 | object_property_get_uint16List(obj, "host-nodes", |
2f6f826e MA |
668 | &m->value->host_nodes, |
669 | &error_abort); | |
76b5d850 HT |
670 | |
671 | m->next = *list; | |
672 | *list = m; | |
673 | } | |
674 | ||
675 | return 0; | |
76b5d850 HT |
676 | } |
677 | ||
678 | MemdevList *qmp_query_memdev(Error **errp) | |
679 | { | |
2f6f826e | 680 | Object *obj = object_get_objects_root(); |
ecaf54a0 | 681 | MemdevList *list = NULL; |
76b5d850 | 682 | |
2f6f826e | 683 | object_child_foreach(obj, query_memdev, &list); |
76b5d850 | 684 | return list; |
76b5d850 | 685 | } |
6bea1ddf | 686 | |
0987d735 PB |
687 | void ram_block_notifier_add(RAMBlockNotifier *n) |
688 | { | |
689 | QLIST_INSERT_HEAD(&ram_list.ramblock_notifiers, n, next); | |
690 | } | |
691 | ||
692 | void ram_block_notifier_remove(RAMBlockNotifier *n) | |
693 | { | |
694 | QLIST_REMOVE(n, next); | |
695 | } | |
696 | ||
697 | void ram_block_notify_add(void *host, size_t size) | |
698 | { | |
699 | RAMBlockNotifier *notifier; | |
700 | ||
701 | QLIST_FOREACH(notifier, &ram_list.ramblock_notifiers, next) { | |
702 | notifier->ram_block_added(notifier, host, size); | |
703 | } | |
704 | } | |
705 | ||
706 | void ram_block_notify_remove(void *host, size_t size) | |
707 | { | |
708 | RAMBlockNotifier *notifier; | |
709 | ||
710 | QLIST_FOREACH(notifier, &ram_list.ramblock_notifiers, next) { | |
711 | notifier->ram_block_removed(notifier, host, size); | |
712 | } | |
713 | } |