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tcg: Improve vector tail clearing
[qemu.git] / tcg / tcg-op-gvec.c
CommitLineData
db432672
RH		 1/*
2 * Generic vector operation expansion
3 *
4 * Copyright (c) 2018 Linaro
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
fb0343d5 9 * version 2.1 of the License, or (at your option) any later version.
db432672
RH		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
dcb32f1d
PMD		 21#include "tcg/tcg.h"
22#include "tcg/tcg-op.h"
23#include "tcg/tcg-op-gvec.h"
db725815 24#include "qemu/main-loop.h"
dcb32f1d 25#include "tcg/tcg-gvec-desc.h"
db432672
RH		 26
27#define MAX_UNROLL 4
28
53229a77
RH		 29#ifdef CONFIG_DEBUG_TCG
30static const TCGOpcode vecop_list_empty[1] = { 0 };
31#else
32#define vecop_list_empty NULL
33#endif
34
35
db432672
RH		 36/* Verify vector size and alignment rules. OFS should be the OR of all
37 of the operand offsets so that we can check them all at once. */
38static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
39{
40 uint32_t opr_align = oprsz >= 16 ? 15 : 7;
41 uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7;
42 tcg_debug_assert(oprsz > 0);
43 tcg_debug_assert(oprsz <= maxsz);
44 tcg_debug_assert((oprsz & opr_align) == 0);
45 tcg_debug_assert((maxsz & max_align) == 0);
46 tcg_debug_assert((ofs & max_align) == 0);
47}
48
49/* Verify vector overlap rules for two operands. */
50static void check_overlap_2(uint32_t d, uint32_t a, uint32_t s)
51{
52 tcg_debug_assert(d == a || d + s <= a || a + s <= d);
53}
54
55/* Verify vector overlap rules for three operands. */
56static void check_overlap_3(uint32_t d, uint32_t a, uint32_t b, uint32_t s)
57{
58 check_overlap_2(d, a, s);
59 check_overlap_2(d, b, s);
60 check_overlap_2(a, b, s);
61}
62
63/* Verify vector overlap rules for four operands. */
64static void check_overlap_4(uint32_t d, uint32_t a, uint32_t b,
65 uint32_t c, uint32_t s)
66{
67 check_overlap_2(d, a, s);
68 check_overlap_2(d, b, s);
69 check_overlap_2(d, c, s);
70 check_overlap_2(a, b, s);
71 check_overlap_2(a, c, s);
72 check_overlap_2(b, c, s);
73}
74
75/* Create a descriptor from components. */
76uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
77{
78 uint32_t desc = 0;
79
80 assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
81 assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
82 assert(data == sextract32(data, 0, SIMD_DATA_BITS));
83
84 oprsz = (oprsz / 8) - 1;
85 maxsz = (maxsz / 8) - 1;
86 desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
87 desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
88 desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
89
90 return desc;
91}
92
93/* Generate a call to a gvec-style helper with two vector operands. */
94void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
95 uint32_t oprsz, uint32_t maxsz, int32_t data,
96 gen_helper_gvec_2 *fn)
97{
98 TCGv_ptr a0, a1;
99 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
100
101 a0 = tcg_temp_new_ptr();
102 a1 = tcg_temp_new_ptr();
103
104 tcg_gen_addi_ptr(a0, cpu_env, dofs);
105 tcg_gen_addi_ptr(a1, cpu_env, aofs);
106
107 fn(a0, a1, desc);
108
109 tcg_temp_free_ptr(a0);
110 tcg_temp_free_ptr(a1);
111 tcg_temp_free_i32(desc);
112}
113
22fc3527
RH		 114/* Generate a call to a gvec-style helper with two vector operands
115 and one scalar operand. */
116void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c,
117 uint32_t oprsz, uint32_t maxsz, int32_t data,
118 gen_helper_gvec_2i *fn)
119{
120 TCGv_ptr a0, a1;
121 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
122
123 a0 = tcg_temp_new_ptr();
124 a1 = tcg_temp_new_ptr();
125
126 tcg_gen_addi_ptr(a0, cpu_env, dofs);
127 tcg_gen_addi_ptr(a1, cpu_env, aofs);
128
129 fn(a0, a1, c, desc);
130
131 tcg_temp_free_ptr(a0);
132 tcg_temp_free_ptr(a1);
133 tcg_temp_free_i32(desc);
134}
135
db432672
RH		 136/* Generate a call to a gvec-style helper with three vector operands. */
137void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
138 uint32_t oprsz, uint32_t maxsz, int32_t data,
139 gen_helper_gvec_3 *fn)
140{
141 TCGv_ptr a0, a1, a2;
142 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
143
144 a0 = tcg_temp_new_ptr();
145 a1 = tcg_temp_new_ptr();
146 a2 = tcg_temp_new_ptr();
147
148 tcg_gen_addi_ptr(a0, cpu_env, dofs);
149 tcg_gen_addi_ptr(a1, cpu_env, aofs);
150 tcg_gen_addi_ptr(a2, cpu_env, bofs);
151
152 fn(a0, a1, a2, desc);
153
154 tcg_temp_free_ptr(a0);
155 tcg_temp_free_ptr(a1);
156 tcg_temp_free_ptr(a2);
157 tcg_temp_free_i32(desc);
158}
159
160/* Generate a call to a gvec-style helper with four vector operands. */
161void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
162 uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
163 int32_t data, gen_helper_gvec_4 *fn)
164{
165 TCGv_ptr a0, a1, a2, a3;
166 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
167
168 a0 = tcg_temp_new_ptr();
169 a1 = tcg_temp_new_ptr();
170 a2 = tcg_temp_new_ptr();
171 a3 = tcg_temp_new_ptr();
172
173 tcg_gen_addi_ptr(a0, cpu_env, dofs);
174 tcg_gen_addi_ptr(a1, cpu_env, aofs);
175 tcg_gen_addi_ptr(a2, cpu_env, bofs);
176 tcg_gen_addi_ptr(a3, cpu_env, cofs);
177
178 fn(a0, a1, a2, a3, desc);
179
180 tcg_temp_free_ptr(a0);
181 tcg_temp_free_ptr(a1);
182 tcg_temp_free_ptr(a2);
183 tcg_temp_free_ptr(a3);
184 tcg_temp_free_i32(desc);
185}
186
187/* Generate a call to a gvec-style helper with five vector operands. */
188void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
189 uint32_t cofs, uint32_t xofs, uint32_t oprsz,
190 uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn)
191{
192 TCGv_ptr a0, a1, a2, a3, a4;
193 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
194
195 a0 = tcg_temp_new_ptr();
196 a1 = tcg_temp_new_ptr();
197 a2 = tcg_temp_new_ptr();
198 a3 = tcg_temp_new_ptr();
199 a4 = tcg_temp_new_ptr();
200
201 tcg_gen_addi_ptr(a0, cpu_env, dofs);
202 tcg_gen_addi_ptr(a1, cpu_env, aofs);
203 tcg_gen_addi_ptr(a2, cpu_env, bofs);
204 tcg_gen_addi_ptr(a3, cpu_env, cofs);
205 tcg_gen_addi_ptr(a4, cpu_env, xofs);
206
207 fn(a0, a1, a2, a3, a4, desc);
208
209 tcg_temp_free_ptr(a0);
210 tcg_temp_free_ptr(a1);
211 tcg_temp_free_ptr(a2);
212 tcg_temp_free_ptr(a3);
213 tcg_temp_free_ptr(a4);
214 tcg_temp_free_i32(desc);
215}
216
217/* Generate a call to a gvec-style helper with three vector operands
218 and an extra pointer operand. */
219void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
220 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
221 int32_t data, gen_helper_gvec_2_ptr *fn)
222{
223 TCGv_ptr a0, a1;
224 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
225
226 a0 = tcg_temp_new_ptr();
227 a1 = tcg_temp_new_ptr();
228
229 tcg_gen_addi_ptr(a0, cpu_env, dofs);
230 tcg_gen_addi_ptr(a1, cpu_env, aofs);
231
232 fn(a0, a1, ptr, desc);
233
234 tcg_temp_free_ptr(a0);
235 tcg_temp_free_ptr(a1);
236 tcg_temp_free_i32(desc);
237}
238
239/* Generate a call to a gvec-style helper with three vector operands
240 and an extra pointer operand. */
241void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
242 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
243 int32_t data, gen_helper_gvec_3_ptr *fn)
244{
245 TCGv_ptr a0, a1, a2;
246 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
247
248 a0 = tcg_temp_new_ptr();
249 a1 = tcg_temp_new_ptr();
250 a2 = tcg_temp_new_ptr();
251
252 tcg_gen_addi_ptr(a0, cpu_env, dofs);
253 tcg_gen_addi_ptr(a1, cpu_env, aofs);
254 tcg_gen_addi_ptr(a2, cpu_env, bofs);
255
256 fn(a0, a1, a2, ptr, desc);
257
258 tcg_temp_free_ptr(a0);
259 tcg_temp_free_ptr(a1);
260 tcg_temp_free_ptr(a2);
261 tcg_temp_free_i32(desc);
262}
263
264/* Generate a call to a gvec-style helper with four vector operands
265 and an extra pointer operand. */
266void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
267 uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
268 uint32_t maxsz, int32_t data,
269 gen_helper_gvec_4_ptr *fn)
270{
271 TCGv_ptr a0, a1, a2, a3;
272 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
273
274 a0 = tcg_temp_new_ptr();
275 a1 = tcg_temp_new_ptr();
276 a2 = tcg_temp_new_ptr();
277 a3 = tcg_temp_new_ptr();
278
279 tcg_gen_addi_ptr(a0, cpu_env, dofs);
280 tcg_gen_addi_ptr(a1, cpu_env, aofs);
281 tcg_gen_addi_ptr(a2, cpu_env, bofs);
282 tcg_gen_addi_ptr(a3, cpu_env, cofs);
283
284 fn(a0, a1, a2, a3, ptr, desc);
285
286 tcg_temp_free_ptr(a0);
287 tcg_temp_free_ptr(a1);
288 tcg_temp_free_ptr(a2);
289 tcg_temp_free_ptr(a3);
290 tcg_temp_free_i32(desc);
291}
292
24459716
RH		 293/* Generate a call to a gvec-style helper with five vector operands
294 and an extra pointer operand. */
295void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
296 uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
297 uint32_t oprsz, uint32_t maxsz, int32_t data,
298 gen_helper_gvec_5_ptr *fn)
299{
300 TCGv_ptr a0, a1, a2, a3, a4;
301 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
302
303 a0 = tcg_temp_new_ptr();
304 a1 = tcg_temp_new_ptr();
305 a2 = tcg_temp_new_ptr();
306 a3 = tcg_temp_new_ptr();
307 a4 = tcg_temp_new_ptr();
308
309 tcg_gen_addi_ptr(a0, cpu_env, dofs);
310 tcg_gen_addi_ptr(a1, cpu_env, aofs);
311 tcg_gen_addi_ptr(a2, cpu_env, bofs);
312 tcg_gen_addi_ptr(a3, cpu_env, cofs);
313 tcg_gen_addi_ptr(a4, cpu_env, eofs);
314
315 fn(a0, a1, a2, a3, a4, ptr, desc);
316
317 tcg_temp_free_ptr(a0);
318 tcg_temp_free_ptr(a1);
319 tcg_temp_free_ptr(a2);
320 tcg_temp_free_ptr(a3);
321 tcg_temp_free_ptr(a4);
322 tcg_temp_free_i32(desc);
323}
324
db432672
RH		 325/* Return true if we want to implement something of OPRSZ bytes
326 in units of LNSZ. This limits the expansion of inline code. */
327static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
328{
f47db80c
RH		 329 uint32_t q, r;
330
331 if (oprsz < lnsz) {
332 return false;
333 }
334
335 q = oprsz / lnsz;
336 r = oprsz % lnsz;
337 tcg_debug_assert((r & 7) == 0);
338
339 if (lnsz < 16) {
340 /* For sizes below 16, accept no remainder. */
341 if (r != 0) {
342 return false;
343 }
344 } else {
345 /*
346 * Recall that ARM SVE allows vector sizes that are not a
347 * power of 2, but always a multiple of 16. The intent is
348 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
349 * In addition, expand_clr needs to handle a multiple of 8.
350 * Thus we can handle the tail with one more operation per
351 * diminishing power of 2.
352 */
353 q += ctpop32(r);
499748d7 354 }
f47db80c
RH		 355
356 return q <= MAX_UNROLL;
db432672
RH		 357}
358
359static void expand_clr(uint32_t dofs, uint32_t maxsz);
360
361/* Duplicate C as per VECE. */
362uint64_t (dup_const)(unsigned vece, uint64_t c)
363{
364 switch (vece) {
365 case MO_8:
366 return 0x0101010101010101ull * (uint8_t)c;
367 case MO_16:
368 return 0x0001000100010001ull * (uint16_t)c;
369 case MO_32:
370 return 0x0000000100000001ull * (uint32_t)c;
371 case MO_64:
372 return c;
373 default:
374 g_assert_not_reached();
375 }
376}
377
378/* Duplicate IN into OUT as per VECE. */
379static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in)
380{
381 switch (vece) {
382 case MO_8:
383 tcg_gen_ext8u_i32(out, in);
384 tcg_gen_muli_i32(out, out, 0x01010101);
385 break;
386 case MO_16:
387 tcg_gen_deposit_i32(out, in, in, 16, 16);
388 break;
389 case MO_32:
390 tcg_gen_mov_i32(out, in);
391 break;
392 default:
393 g_assert_not_reached();
394 }
395}
396
397static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in)
398{
399 switch (vece) {
400 case MO_8:
401 tcg_gen_ext8u_i64(out, in);
402 tcg_gen_muli_i64(out, out, 0x0101010101010101ull);
403 break;
404 case MO_16:
405 tcg_gen_ext16u_i64(out, in);
406 tcg_gen_muli_i64(out, out, 0x0001000100010001ull);
407 break;
408 case MO_32:
409 tcg_gen_deposit_i64(out, in, in, 32, 32);
410 break;
411 case MO_64:
412 tcg_gen_mov_i64(out, in);
413 break;
414 default:
415 g_assert_not_reached();
416 }
417}
418
adb196cb
RH		 419/* Select a supported vector type for implementing an operation on SIZE
420 * bytes. If OP is 0, assume that the real operation to be performed is
421 * required by all backends. Otherwise, make sure than OP can be performed
422 * on elements of size VECE in the selected type. Do not select V64 if
423 * PREFER_I64 is true. Return 0 if no vector type is selected.
424 */
53229a77
RH		 425static TCGType choose_vector_type(const TCGOpcode *list, unsigned vece,
426 uint32_t size, bool prefer_i64)
adb196cb 427{
f47db80c
RH		 428 /*
429 * Recall that ARM SVE allows vector sizes that are not a
430 * power of 2, but always a multiple of 16. The intent is
431 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
432 * It is hard to imagine a case in which v256 is supported
433 * but v128 is not, but check anyway.
434 * In addition, expand_clr needs to handle a multiple of 8.
435 */
436 if (TCG_TARGET_HAS_v256 &&
437 check_size_impl(size, 32) &&
438 tcg_can_emit_vecop_list(list, TCG_TYPE_V256, vece) &&
439 (!(size & 16) ||
440 (TCG_TARGET_HAS_v128 &&
441 tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece))) &&
442 (!(size & 8) ||
443 (TCG_TARGET_HAS_v64 &&
444 tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)))) {
445 return TCG_TYPE_V256;
adb196cb 446 }
f47db80c
RH		 447 if (TCG_TARGET_HAS_v128 &&
448 check_size_impl(size, 16) &&
449 tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece) &&
450 (!(size & 8) ||
451 (TCG_TARGET_HAS_v64 &&
452 tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)))) {
adb196cb
RH		 453 return TCG_TYPE_V128;
454 }
455 if (TCG_TARGET_HAS_v64 && !prefer_i64 && check_size_impl(size, 8)
53229a77 456 && tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)) {
adb196cb
RH		 457 return TCG_TYPE_V64;
458 }
459 return 0;
460}
461
37ee55a0
RH		 462static void do_dup_store(TCGType type, uint32_t dofs, uint32_t oprsz,
463 uint32_t maxsz, TCGv_vec t_vec)
464{
465 uint32_t i = 0;
466
f47db80c
RH		 467 tcg_debug_assert(oprsz >= 8);
468
469 /*
470 * This may be expand_clr for the tail of an operation, e.g.
471 * oprsz == 8 && maxsz == 64. The first 8 bytes of this store
472 * are misaligned wrt the maximum vector size, so do that first.
473 */
474 if (dofs & 8) {
475 tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64);
476 i += 8;
477 }
478
37ee55a0
RH		 479 switch (type) {
480 case TCG_TYPE_V256:
481 /*
482 * Recall that ARM SVE allows vector sizes that are not a
483 * power of 2, but always a multiple of 16. The intent is
484 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
485 */
486 for (; i + 32 <= oprsz; i += 32) {
487 tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256);
488 }
489 /* fallthru */
490 case TCG_TYPE_V128:
491 for (; i + 16 <= oprsz; i += 16) {
492 tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128);
493 }
494 break;
495 case TCG_TYPE_V64:
496 for (; i < oprsz; i += 8) {
497 tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64);
498 }
499 break;
500 default:
501 g_assert_not_reached();
502 }
503
504 if (oprsz < maxsz) {
505 expand_clr(dofs + oprsz, maxsz - oprsz);
506 }
507}
508
db432672
RH		 509/* Set OPRSZ bytes at DOFS to replications of IN_32, IN_64 or IN_C.
510 * Only one of IN_32 or IN_64 may be set;
511 * IN_C is used if IN_32 and IN_64 are unset.
512 */
513static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,
514 uint32_t maxsz, TCGv_i32 in_32, TCGv_i64 in_64,
515 uint64_t in_c)
516{
517 TCGType type;
518 TCGv_i64 t_64;
519 TCGv_i32 t_32, t_desc;
520 TCGv_ptr t_ptr;
521 uint32_t i;
522
523 assert(vece <= (in_32 ? MO_32 : MO_64));
524 assert(in_32 == NULL || in_64 == NULL);
525
526 /* If we're storing 0, expand oprsz to maxsz. */
527 if (in_32 == NULL && in_64 == NULL) {
528 in_c = dup_const(vece, in_c);
529 if (in_c == 0) {
530 oprsz = maxsz;
531 }
532 }
533
adb196cb
RH		 534 /* Implement inline with a vector type, if possible.
535 * Prefer integer when 64-bit host and no variable dup.
536 */
53229a77 537 type = choose_vector_type(NULL, vece, oprsz,
adb196cb
RH		 538 (TCG_TARGET_REG_BITS == 64 && in_32 == NULL
539 && (in_64 == NULL || vece == MO_64)));
db432672
RH		 540 if (type != 0) {
541 TCGv_vec t_vec = tcg_temp_new_vec(type);
542
543 if (in_32) {
544 tcg_gen_dup_i32_vec(vece, t_vec, in_32);
545 } else if (in_64) {
546 tcg_gen_dup_i64_vec(vece, t_vec, in_64);
547 } else {
37ee55a0 548 tcg_gen_dupi_vec(vece, t_vec, in_c);
db432672 549 }
37ee55a0 550 do_dup_store(type, dofs, oprsz, maxsz, t_vec);
db432672 551 tcg_temp_free_vec(t_vec);
37ee55a0 552 return;
db432672
RH		 553 }
554
555 /* Otherwise, inline with an integer type, unless "large". */
556 if (check_size_impl(oprsz, TCG_TARGET_REG_BITS / 8)) {
557 t_64 = NULL;
558 t_32 = NULL;
559
560 if (in_32) {
561 /* We are given a 32-bit variable input. For a 64-bit host,
562 use a 64-bit operation unless the 32-bit operation would
563 be simple enough. */
564 if (TCG_TARGET_REG_BITS == 64
565 && (vece != MO_32 || !check_size_impl(oprsz, 4))) {
566 t_64 = tcg_temp_new_i64();
567 tcg_gen_extu_i32_i64(t_64, in_32);
568 gen_dup_i64(vece, t_64, t_64);
569 } else {
570 t_32 = tcg_temp_new_i32();
571 gen_dup_i32(vece, t_32, in_32);
572 }
573 } else if (in_64) {
574 /* We are given a 64-bit variable input. */
575 t_64 = tcg_temp_new_i64();
576 gen_dup_i64(vece, t_64, in_64);
577 } else {
578 /* We are given a constant input. */
579 /* For 64-bit hosts, use 64-bit constants for "simple" constants
580 or when we'd need too many 32-bit stores, or when a 64-bit
581 constant is really required. */
582 if (vece == MO_64
583 || (TCG_TARGET_REG_BITS == 64
584 && (in_c == 0 || in_c == -1
585 || !check_size_impl(oprsz, 4)))) {
586 t_64 = tcg_const_i64(in_c);
587 } else {
588 t_32 = tcg_const_i32(in_c);
589 }
590 }
591
592 /* Implement inline if we picked an implementation size above. */
593 if (t_32) {
594 for (i = 0; i < oprsz; i += 4) {
595 tcg_gen_st_i32(t_32, cpu_env, dofs + i);
596 }
597 tcg_temp_free_i32(t_32);
598 goto done;
599 }
600 if (t_64) {
601 for (i = 0; i < oprsz; i += 8) {
602 tcg_gen_st_i64(t_64, cpu_env, dofs + i);
603 }
604 tcg_temp_free_i64(t_64);
605 goto done;
adb196cb 606 }
db432672
RH		 607 }
608
609 /* Otherwise implement out of line. */
610 t_ptr = tcg_temp_new_ptr();
611 tcg_gen_addi_ptr(t_ptr, cpu_env, dofs);
612 t_desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0));
613
614 if (vece == MO_64) {
615 if (in_64) {
616 gen_helper_gvec_dup64(t_ptr, t_desc, in_64);
617 } else {
618 t_64 = tcg_const_i64(in_c);
619 gen_helper_gvec_dup64(t_ptr, t_desc, t_64);
620 tcg_temp_free_i64(t_64);
621 }
622 } else {
623 typedef void dup_fn(TCGv_ptr, TCGv_i32, TCGv_i32);
624 static dup_fn * const fns[3] = {
625 gen_helper_gvec_dup8,
626 gen_helper_gvec_dup16,
627 gen_helper_gvec_dup32
628 };
629
630 if (in_32) {
631 fns[vece](t_ptr, t_desc, in_32);
632 } else {
633 t_32 = tcg_temp_new_i32();
634 if (in_64) {
635 tcg_gen_extrl_i64_i32(t_32, in_64);
636 } else if (vece == MO_8) {
637 tcg_gen_movi_i32(t_32, in_c & 0xff);
638 } else if (vece == MO_16) {
639 tcg_gen_movi_i32(t_32, in_c & 0xffff);
640 } else {
641 tcg_gen_movi_i32(t_32, in_c);
642 }
643 fns[vece](t_ptr, t_desc, t_32);
644 tcg_temp_free_i32(t_32);
645 }
646 }
647
648 tcg_temp_free_ptr(t_ptr);
649 tcg_temp_free_i32(t_desc);
650 return;
651
652 done:
653 if (oprsz < maxsz) {
654 expand_clr(dofs + oprsz, maxsz - oprsz);
655 }
656}
657
658/* Likewise, but with zero. */
659static void expand_clr(uint32_t dofs, uint32_t maxsz)
660{
661 do_dup(MO_8, dofs, maxsz, maxsz, NULL, NULL, 0);
662}
663
664/* Expand OPSZ bytes worth of two-operand operations using i32 elements. */
665static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
666 void (*fni)(TCGv_i32, TCGv_i32))
667{
668 TCGv_i32 t0 = tcg_temp_new_i32();
669 uint32_t i;
670
671 for (i = 0; i < oprsz; i += 4) {
672 tcg_gen_ld_i32(t0, cpu_env, aofs + i);
673 fni(t0, t0);
674 tcg_gen_st_i32(t0, cpu_env, dofs + i);
675 }
676 tcg_temp_free_i32(t0);
677}
678
d0ec9796
RH		 679static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
680 int32_t c, bool load_dest,
681 void (*fni)(TCGv_i32, TCGv_i32, int32_t))
682{
683 TCGv_i32 t0 = tcg_temp_new_i32();
684 TCGv_i32 t1 = tcg_temp_new_i32();
685 uint32_t i;
686
687 for (i = 0; i < oprsz; i += 4) {
688 tcg_gen_ld_i32(t0, cpu_env, aofs + i);
689 if (load_dest) {
690 tcg_gen_ld_i32(t1, cpu_env, dofs + i);
691 }
692 fni(t1, t0, c);
693 tcg_gen_st_i32(t1, cpu_env, dofs + i);
694 }
695 tcg_temp_free_i32(t0);
696 tcg_temp_free_i32(t1);
697}
698
22fc3527
RH		 699static void expand_2s_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
700 TCGv_i32 c, bool scalar_first,
701 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32))
702{
703 TCGv_i32 t0 = tcg_temp_new_i32();
704 TCGv_i32 t1 = tcg_temp_new_i32();
705 uint32_t i;
706
707 for (i = 0; i < oprsz; i += 4) {
708 tcg_gen_ld_i32(t0, cpu_env, aofs + i);
709 if (scalar_first) {
710 fni(t1, c, t0);
711 } else {
712 fni(t1, t0, c);
713 }
714 tcg_gen_st_i32(t1, cpu_env, dofs + i);
715 }
716 tcg_temp_free_i32(t0);
717 tcg_temp_free_i32(t1);
718}
719
db432672
RH		 720/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
721static void expand_3_i32(uint32_t dofs, uint32_t aofs,
722 uint32_t bofs, uint32_t oprsz, bool load_dest,
723 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32))
724{
725 TCGv_i32 t0 = tcg_temp_new_i32();
726 TCGv_i32 t1 = tcg_temp_new_i32();
727 TCGv_i32 t2 = tcg_temp_new_i32();
728 uint32_t i;
729
730 for (i = 0; i < oprsz; i += 4) {
731 tcg_gen_ld_i32(t0, cpu_env, aofs + i);
732 tcg_gen_ld_i32(t1, cpu_env, bofs + i);
733 if (load_dest) {
734 tcg_gen_ld_i32(t2, cpu_env, dofs + i);
735 }
736 fni(t2, t0, t1);
737 tcg_gen_st_i32(t2, cpu_env, dofs + i);
738 }
739 tcg_temp_free_i32(t2);
740 tcg_temp_free_i32(t1);
741 tcg_temp_free_i32(t0);
742}
743
e1227bb6
DH		 744static void expand_3i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
745 uint32_t oprsz, int32_t c, bool load_dest,
746 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t))
747{
748 TCGv_i32 t0 = tcg_temp_new_i32();
749 TCGv_i32 t1 = tcg_temp_new_i32();
750 TCGv_i32 t2 = tcg_temp_new_i32();
751 uint32_t i;
752
753 for (i = 0; i < oprsz; i += 4) {
754 tcg_gen_ld_i32(t0, cpu_env, aofs + i);
755 tcg_gen_ld_i32(t1, cpu_env, bofs + i);
756 if (load_dest) {
757 tcg_gen_ld_i32(t2, cpu_env, dofs + i);
758 }
759 fni(t2, t0, t1, c);
760 tcg_gen_st_i32(t2, cpu_env, dofs + i);
761 }
762 tcg_temp_free_i32(t0);
763 tcg_temp_free_i32(t1);
764 tcg_temp_free_i32(t2);
765}
766
db432672
RH		 767/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
768static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
5d6acdd4 769 uint32_t cofs, uint32_t oprsz, bool write_aofs,
db432672
RH		 770 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32))
771{
772 TCGv_i32 t0 = tcg_temp_new_i32();
773 TCGv_i32 t1 = tcg_temp_new_i32();
774 TCGv_i32 t2 = tcg_temp_new_i32();
775 TCGv_i32 t3 = tcg_temp_new_i32();
776 uint32_t i;
777
778 for (i = 0; i < oprsz; i += 4) {
779 tcg_gen_ld_i32(t1, cpu_env, aofs + i);
780 tcg_gen_ld_i32(t2, cpu_env, bofs + i);
781 tcg_gen_ld_i32(t3, cpu_env, cofs + i);
782 fni(t0, t1, t2, t3);
783 tcg_gen_st_i32(t0, cpu_env, dofs + i);
5d6acdd4
RH		 784 if (write_aofs) {
785 tcg_gen_st_i32(t1, cpu_env, aofs + i);
786 }
db432672
RH		 787 }
788 tcg_temp_free_i32(t3);
789 tcg_temp_free_i32(t2);
790 tcg_temp_free_i32(t1);
791 tcg_temp_free_i32(t0);
792}
793
794/* Expand OPSZ bytes worth of two-operand operations using i64 elements. */
795static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
796 void (*fni)(TCGv_i64, TCGv_i64))
797{
798 TCGv_i64 t0 = tcg_temp_new_i64();
799 uint32_t i;
800
801 for (i = 0; i < oprsz; i += 8) {
802 tcg_gen_ld_i64(t0, cpu_env, aofs + i);
803 fni(t0, t0);
804 tcg_gen_st_i64(t0, cpu_env, dofs + i);
805 }
806 tcg_temp_free_i64(t0);
807}
808
d0ec9796
RH		 809static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
810 int64_t c, bool load_dest,
811 void (*fni)(TCGv_i64, TCGv_i64, int64_t))
812{
813 TCGv_i64 t0 = tcg_temp_new_i64();
814 TCGv_i64 t1 = tcg_temp_new_i64();
815 uint32_t i;
816
817 for (i = 0; i < oprsz; i += 8) {
818 tcg_gen_ld_i64(t0, cpu_env, aofs + i);
819 if (load_dest) {
820 tcg_gen_ld_i64(t1, cpu_env, dofs + i);
821 }
822 fni(t1, t0, c);
823 tcg_gen_st_i64(t1, cpu_env, dofs + i);
824 }
825 tcg_temp_free_i64(t0);
826 tcg_temp_free_i64(t1);
827}
828
22fc3527
RH		 829static void expand_2s_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
830 TCGv_i64 c, bool scalar_first,
831 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64))
832{
833 TCGv_i64 t0 = tcg_temp_new_i64();
834 TCGv_i64 t1 = tcg_temp_new_i64();
835 uint32_t i;
836
837 for (i = 0; i < oprsz; i += 8) {
838 tcg_gen_ld_i64(t0, cpu_env, aofs + i);
839 if (scalar_first) {
840 fni(t1, c, t0);
841 } else {
842 fni(t1, t0, c);
843 }
844 tcg_gen_st_i64(t1, cpu_env, dofs + i);
845 }
846 tcg_temp_free_i64(t0);
847 tcg_temp_free_i64(t1);
848}
849
db432672
RH		 850/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
851static void expand_3_i64(uint32_t dofs, uint32_t aofs,
852 uint32_t bofs, uint32_t oprsz, bool load_dest,
853 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64))
854{
855 TCGv_i64 t0 = tcg_temp_new_i64();
856 TCGv_i64 t1 = tcg_temp_new_i64();
857 TCGv_i64 t2 = tcg_temp_new_i64();
858 uint32_t i;
859
860 for (i = 0; i < oprsz; i += 8) {
861 tcg_gen_ld_i64(t0, cpu_env, aofs + i);
862 tcg_gen_ld_i64(t1, cpu_env, bofs + i);
863 if (load_dest) {
864 tcg_gen_ld_i64(t2, cpu_env, dofs + i);
865 }
866 fni(t2, t0, t1);
867 tcg_gen_st_i64(t2, cpu_env, dofs + i);
868 }
869 tcg_temp_free_i64(t2);
870 tcg_temp_free_i64(t1);
871 tcg_temp_free_i64(t0);
872}
873
e1227bb6
DH		 874static void expand_3i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
875 uint32_t oprsz, int64_t c, bool load_dest,
876 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t))
877{
878 TCGv_i64 t0 = tcg_temp_new_i64();
879 TCGv_i64 t1 = tcg_temp_new_i64();
880 TCGv_i64 t2 = tcg_temp_new_i64();
881 uint32_t i;
882
883 for (i = 0; i < oprsz; i += 8) {
884 tcg_gen_ld_i64(t0, cpu_env, aofs + i);
885 tcg_gen_ld_i64(t1, cpu_env, bofs + i);
886 if (load_dest) {
887 tcg_gen_ld_i64(t2, cpu_env, dofs + i);
888 }
889 fni(t2, t0, t1, c);
890 tcg_gen_st_i64(t2, cpu_env, dofs + i);
891 }
892 tcg_temp_free_i64(t0);
893 tcg_temp_free_i64(t1);
894 tcg_temp_free_i64(t2);
895}
896
db432672
RH		 897/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
898static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
5d6acdd4 899 uint32_t cofs, uint32_t oprsz, bool write_aofs,
db432672
RH		 900 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
901{
902 TCGv_i64 t0 = tcg_temp_new_i64();
903 TCGv_i64 t1 = tcg_temp_new_i64();
904 TCGv_i64 t2 = tcg_temp_new_i64();
905 TCGv_i64 t3 = tcg_temp_new_i64();
906 uint32_t i;
907
908 for (i = 0; i < oprsz; i += 8) {
909 tcg_gen_ld_i64(t1, cpu_env, aofs + i);
910 tcg_gen_ld_i64(t2, cpu_env, bofs + i);
911 tcg_gen_ld_i64(t3, cpu_env, cofs + i);
912 fni(t0, t1, t2, t3);
913 tcg_gen_st_i64(t0, cpu_env, dofs + i);
5d6acdd4
RH		 914 if (write_aofs) {
915 tcg_gen_st_i64(t1, cpu_env, aofs + i);
916 }
db432672
RH		 917 }
918 tcg_temp_free_i64(t3);
919 tcg_temp_free_i64(t2);
920 tcg_temp_free_i64(t1);
921 tcg_temp_free_i64(t0);
922}
923
924/* Expand OPSZ bytes worth of two-operand operations using host vectors. */
925static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
926 uint32_t oprsz, uint32_t tysz, TCGType type,
927 void (*fni)(unsigned, TCGv_vec, TCGv_vec))
928{
929 TCGv_vec t0 = tcg_temp_new_vec(type);
930 uint32_t i;
931
932 for (i = 0; i < oprsz; i += tysz) {
933 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
934 fni(vece, t0, t0);
935 tcg_gen_st_vec(t0, cpu_env, dofs + i);
936 }
937 tcg_temp_free_vec(t0);
938}
939
d0ec9796
RH		 940/* Expand OPSZ bytes worth of two-vector operands and an immediate operand
941 using host vectors. */
942static void expand_2i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
943 uint32_t oprsz, uint32_t tysz, TCGType type,
944 int64_t c, bool load_dest,
945 void (*fni)(unsigned, TCGv_vec, TCGv_vec, int64_t))
946{
947 TCGv_vec t0 = tcg_temp_new_vec(type);
948 TCGv_vec t1 = tcg_temp_new_vec(type);
949 uint32_t i;
950
951 for (i = 0; i < oprsz; i += tysz) {
952 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
953 if (load_dest) {
954 tcg_gen_ld_vec(t1, cpu_env, dofs + i);
955 }
956 fni(vece, t1, t0, c);
957 tcg_gen_st_vec(t1, cpu_env, dofs + i);
958 }
959 tcg_temp_free_vec(t0);
960 tcg_temp_free_vec(t1);
961}
962
22fc3527
RH		 963static void expand_2s_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
964 uint32_t oprsz, uint32_t tysz, TCGType type,
965 TCGv_vec c, bool scalar_first,
966 void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
967{
968 TCGv_vec t0 = tcg_temp_new_vec(type);
969 TCGv_vec t1 = tcg_temp_new_vec(type);
970 uint32_t i;
971
972 for (i = 0; i < oprsz; i += tysz) {
973 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
974 if (scalar_first) {
975 fni(vece, t1, c, t0);
976 } else {
977 fni(vece, t1, t0, c);
978 }
979 tcg_gen_st_vec(t1, cpu_env, dofs + i);
980 }
981 tcg_temp_free_vec(t0);
982 tcg_temp_free_vec(t1);
983}
984
db432672
RH		 985/* Expand OPSZ bytes worth of three-operand operations using host vectors. */
986static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
987 uint32_t bofs, uint32_t oprsz,
988 uint32_t tysz, TCGType type, bool load_dest,
989 void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
990{
991 TCGv_vec t0 = tcg_temp_new_vec(type);
992 TCGv_vec t1 = tcg_temp_new_vec(type);
993 TCGv_vec t2 = tcg_temp_new_vec(type);
994 uint32_t i;
995
996 for (i = 0; i < oprsz; i += tysz) {
997 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
998 tcg_gen_ld_vec(t1, cpu_env, bofs + i);
999 if (load_dest) {
1000 tcg_gen_ld_vec(t2, cpu_env, dofs + i);
1001 }
1002 fni(vece, t2, t0, t1);
1003 tcg_gen_st_vec(t2, cpu_env, dofs + i);
1004 }
1005 tcg_temp_free_vec(t2);
1006 tcg_temp_free_vec(t1);
1007 tcg_temp_free_vec(t0);
1008}
1009
e1227bb6
DH		 1010/*
1011 * Expand OPSZ bytes worth of three-vector operands and an immediate operand
1012 * using host vectors.
1013 */
1014static void expand_3i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
1015 uint32_t bofs, uint32_t oprsz, uint32_t tysz,
1016 TCGType type, int64_t c, bool load_dest,
1017 void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec,
1018 int64_t))
1019{
1020 TCGv_vec t0 = tcg_temp_new_vec(type);
1021 TCGv_vec t1 = tcg_temp_new_vec(type);
1022 TCGv_vec t2 = tcg_temp_new_vec(type);
1023 uint32_t i;
1024
1025 for (i = 0; i < oprsz; i += tysz) {
1026 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
1027 tcg_gen_ld_vec(t1, cpu_env, bofs + i);
1028 if (load_dest) {
1029 tcg_gen_ld_vec(t2, cpu_env, dofs + i);
1030 }
1031 fni(vece, t2, t0, t1, c);
1032 tcg_gen_st_vec(t2, cpu_env, dofs + i);
1033 }
1034 tcg_temp_free_vec(t0);
1035 tcg_temp_free_vec(t1);
1036 tcg_temp_free_vec(t2);
1037}
1038
db432672
RH		 1039/* Expand OPSZ bytes worth of four-operand operations using host vectors. */
1040static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
1041 uint32_t bofs, uint32_t cofs, uint32_t oprsz,
5d6acdd4 1042 uint32_t tysz, TCGType type, bool write_aofs,
db432672
RH		 1043 void (*fni)(unsigned, TCGv_vec, TCGv_vec,
1044 TCGv_vec, TCGv_vec))
1045{
1046 TCGv_vec t0 = tcg_temp_new_vec(type);
1047 TCGv_vec t1 = tcg_temp_new_vec(type);
1048 TCGv_vec t2 = tcg_temp_new_vec(type);
1049 TCGv_vec t3 = tcg_temp_new_vec(type);
1050 uint32_t i;
1051
1052 for (i = 0; i < oprsz; i += tysz) {
1053 tcg_gen_ld_vec(t1, cpu_env, aofs + i);
1054 tcg_gen_ld_vec(t2, cpu_env, bofs + i);
1055 tcg_gen_ld_vec(t3, cpu_env, cofs + i);
1056 fni(vece, t0, t1, t2, t3);
1057 tcg_gen_st_vec(t0, cpu_env, dofs + i);
5d6acdd4
RH		 1058 if (write_aofs) {
1059 tcg_gen_st_vec(t1, cpu_env, aofs + i);
1060 }
db432672
RH		 1061 }
1062 tcg_temp_free_vec(t3);
1063 tcg_temp_free_vec(t2);
1064 tcg_temp_free_vec(t1);
1065 tcg_temp_free_vec(t0);
1066}
1067
1068/* Expand a vector two-operand operation. */
1069void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
1070 uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g)
1071{
53229a77
RH		 1072 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
1073 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
adb196cb
RH		 1074 TCGType type;
1075 uint32_t some;
1076
db432672
RH		 1077 check_size_align(oprsz, maxsz, dofs | aofs);
1078 check_overlap_2(dofs, aofs, maxsz);
1079
adb196cb
RH		 1080 type = 0;
1081 if (g->fniv) {
53229a77 1082 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
adb196cb
RH		 1083 }
1084 switch (type) {
1085 case TCG_TYPE_V256:
1086 /* Recall that ARM SVE allows vector sizes that are not a
1087 * power of 2, but always a multiple of 16. The intent is
1088 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
1089 */
1090 some = QEMU_ALIGN_DOWN(oprsz, 32);
db432672
RH		 1091 expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, g->fniv);
1092 if (some == oprsz) {
adb196cb 1093 break;
db432672
RH		 1094 }
1095 dofs += some;
1096 aofs += some;
1097 oprsz -= some;
1098 maxsz -= some;
adb196cb
RH		 1099 /* fallthru */
1100 case TCG_TYPE_V128:
db432672 1101 expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, g->fniv);
adb196cb
RH		 1102 break;
1103 case TCG_TYPE_V64:
db432672 1104 expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, g->fniv);
adb196cb
RH		 1105 break;
1106
1107 case 0:
1108 if (g->fni8 && check_size_impl(oprsz, 8)) {
1109 expand_2_i64(dofs, aofs, oprsz, g->fni8);
1110 } else if (g->fni4 && check_size_impl(oprsz, 4)) {
1111 expand_2_i32(dofs, aofs, oprsz, g->fni4);
1112 } else {
1113 assert(g->fno != NULL);
1114 tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno);
53229a77 1115 oprsz = maxsz;
adb196cb
RH		 1116 }
1117 break;
1118
1119 default:
1120 g_assert_not_reached();
db432672 1121 }
53229a77 1122 tcg_swap_vecop_list(hold_list);
db432672 1123
db432672
RH		 1124 if (oprsz < maxsz) {
1125 expand_clr(dofs + oprsz, maxsz - oprsz);
1126 }
1127}
1128
22fc3527 1129/* Expand a vector operation with two vectors and an immediate. */
d0ec9796
RH		 1130void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
1131 uint32_t maxsz, int64_t c, const GVecGen2i *g)
1132{
53229a77
RH		 1133 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
1134 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
adb196cb
RH		 1135 TCGType type;
1136 uint32_t some;
1137
d0ec9796
RH		 1138 check_size_align(oprsz, maxsz, dofs | aofs);
1139 check_overlap_2(dofs, aofs, maxsz);
1140
adb196cb
RH		 1141 type = 0;
1142 if (g->fniv) {
53229a77 1143 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
adb196cb
RH		 1144 }
1145 switch (type) {
1146 case TCG_TYPE_V256:
1147 /* Recall that ARM SVE allows vector sizes that are not a
1148 * power of 2, but always a multiple of 16. The intent is
1149 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
1150 */
1151 some = QEMU_ALIGN_DOWN(oprsz, 32);
d0ec9796
RH		 1152 expand_2i_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256,
1153 c, g->load_dest, g->fniv);
1154 if (some == oprsz) {
adb196cb 1155 break;
d0ec9796
RH		 1156 }
1157 dofs += some;
1158 aofs += some;
1159 oprsz -= some;
1160 maxsz -= some;
adb196cb
RH		 1161 /* fallthru */
1162 case TCG_TYPE_V128:
d0ec9796
RH		 1163 expand_2i_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
1164 c, g->load_dest, g->fniv);
adb196cb
RH		 1165 break;
1166 case TCG_TYPE_V64:
d0ec9796
RH		 1167 expand_2i_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
1168 c, g->load_dest, g->fniv);
adb196cb
RH		 1169 break;
1170
1171 case 0:
1172 if (g->fni8 && check_size_impl(oprsz, 8)) {
1173 expand_2i_i64(dofs, aofs, oprsz, c, g->load_dest, g->fni8);
1174 } else if (g->fni4 && check_size_impl(oprsz, 4)) {
1175 expand_2i_i32(dofs, aofs, oprsz, c, g->load_dest, g->fni4);
22fc3527 1176 } else {
adb196cb
RH		 1177 if (g->fno) {
1178 tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno);
1179 } else {
1180 TCGv_i64 tcg_c = tcg_const_i64(c);
1181 tcg_gen_gvec_2i_ool(dofs, aofs, tcg_c, oprsz,
1182 maxsz, c, g->fnoi);
1183 tcg_temp_free_i64(tcg_c);
1184 }
53229a77 1185 oprsz = maxsz;
22fc3527 1186 }
adb196cb
RH		 1187 break;
1188
1189 default:
1190 g_assert_not_reached();
d0ec9796 1191 }
53229a77 1192 tcg_swap_vecop_list(hold_list);
d0ec9796 1193
d0ec9796
RH		 1194 if (oprsz < maxsz) {
1195 expand_clr(dofs + oprsz, maxsz - oprsz);
1196 }
1197}
1198
22fc3527
RH		 1199/* Expand a vector operation with two vectors and a scalar. */
1200void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
1201 uint32_t maxsz, TCGv_i64 c, const GVecGen2s *g)
1202{
1203 TCGType type;
1204
1205 check_size_align(oprsz, maxsz, dofs | aofs);
1206 check_overlap_2(dofs, aofs, maxsz);
1207
1208 type = 0;
1209 if (g->fniv) {
53229a77 1210 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
22fc3527
RH		 1211 }
1212 if (type != 0) {
53229a77
RH		 1213 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
1214 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
22fc3527 1215 TCGv_vec t_vec = tcg_temp_new_vec(type);
adb196cb 1216 uint32_t some;
22fc3527
RH		 1217
1218 tcg_gen_dup_i64_vec(g->vece, t_vec, c);
1219
22fc3527
RH		 1220 switch (type) {
1221 case TCG_TYPE_V256:
adb196cb
RH		 1222 /* Recall that ARM SVE allows vector sizes that are not a
1223 * power of 2, but always a multiple of 16. The intent is
1224 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
1225 */
1226 some = QEMU_ALIGN_DOWN(oprsz, 32);
1227 expand_2s_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256,
1228 t_vec, g->scalar_first, g->fniv);
1229 if (some == oprsz) {
1230 break;
22fc3527 1231 }
adb196cb
RH		 1232 dofs += some;
1233 aofs += some;
1234 oprsz -= some;
1235 maxsz -= some;
22fc3527
RH		 1236 /* fallthru */
1237
1238 case TCG_TYPE_V128:
1239 expand_2s_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
1240 t_vec, g->scalar_first, g->fniv);
1241 break;
1242
1243 case TCG_TYPE_V64:
1244 expand_2s_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
1245 t_vec, g->scalar_first, g->fniv);
1246 break;
1247
1248 default:
1249 g_assert_not_reached();
1250 }
1251 tcg_temp_free_vec(t_vec);
53229a77 1252 tcg_swap_vecop_list(hold_list);
22fc3527
RH		 1253 } else if (g->fni8 && check_size_impl(oprsz, 8)) {
1254 TCGv_i64 t64 = tcg_temp_new_i64();
1255
1256 gen_dup_i64(g->vece, t64, c);
1257 expand_2s_i64(dofs, aofs, oprsz, t64, g->scalar_first, g->fni8);
1258 tcg_temp_free_i64(t64);
1259 } else if (g->fni4 && check_size_impl(oprsz, 4)) {
1260 TCGv_i32 t32 = tcg_temp_new_i32();
1261
1262 tcg_gen_extrl_i64_i32(t32, c);
1263 gen_dup_i32(g->vece, t32, t32);
1264 expand_2s_i32(dofs, aofs, oprsz, t32, g->scalar_first, g->fni4);
1265 tcg_temp_free_i32(t32);
1266 } else {
1267 tcg_gen_gvec_2i_ool(dofs, aofs, c, oprsz, maxsz, 0, g->fno);
1268 return;
1269 }
1270
1271 if (oprsz < maxsz) {
1272 expand_clr(dofs + oprsz, maxsz - oprsz);
1273 }
1274}
1275
db432672
RH		 1276/* Expand a vector three-operand operation. */
1277void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
1278 uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
1279{
53229a77
RH		 1280 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
1281 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
adb196cb
RH		 1282 TCGType type;
1283 uint32_t some;
1284
db432672
RH		 1285 check_size_align(oprsz, maxsz, dofs | aofs | bofs);
1286 check_overlap_3(dofs, aofs, bofs, maxsz);
1287
adb196cb
RH		 1288 type = 0;
1289 if (g->fniv) {
53229a77 1290 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
adb196cb
RH		 1291 }
1292 switch (type) {
1293 case TCG_TYPE_V256:
1294 /* Recall that ARM SVE allows vector sizes that are not a
1295 * power of 2, but always a multiple of 16. The intent is
1296 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
1297 */
1298 some = QEMU_ALIGN_DOWN(oprsz, 32);
db432672
RH		 1299 expand_3_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256,
1300 g->load_dest, g->fniv);
1301 if (some == oprsz) {
adb196cb 1302 break;
db432672
RH		 1303 }
1304 dofs += some;
1305 aofs += some;
1306 bofs += some;
1307 oprsz -= some;
1308 maxsz -= some;
adb196cb
RH		 1309 /* fallthru */
1310 case TCG_TYPE_V128:
db432672
RH		 1311 expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
1312 g->load_dest, g->fniv);
adb196cb
RH		 1313 break;
1314 case TCG_TYPE_V64:
db432672
RH		 1315 expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
1316 g->load_dest, g->fniv);
adb196cb
RH		 1317 break;
1318
1319 case 0:
1320 if (g->fni8 && check_size_impl(oprsz, 8)) {
1321 expand_3_i64(dofs, aofs, bofs, oprsz, g->load_dest, g->fni8);
1322 } else if (g->fni4 && check_size_impl(oprsz, 4)) {
1323 expand_3_i32(dofs, aofs, bofs, oprsz, g->load_dest, g->fni4);
1324 } else {
1325 assert(g->fno != NULL);
1326 tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz,
1327 maxsz, g->data, g->fno);
53229a77 1328 oprsz = maxsz;
adb196cb
RH		 1329 }
1330 break;
1331
1332 default:
1333 g_assert_not_reached();
db432672 1334 }
53229a77 1335 tcg_swap_vecop_list(hold_list);
db432672 1336
db432672
RH		 1337 if (oprsz < maxsz) {
1338 expand_clr(dofs + oprsz, maxsz - oprsz);
1339 }
1340}
1341
e1227bb6
DH		 1342/* Expand a vector operation with three vectors and an immediate. */
1343void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
1344 uint32_t oprsz, uint32_t maxsz, int64_t c,
1345 const GVecGen3i *g)
1346{
53229a77
RH		 1347 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
1348 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
e1227bb6
DH		 1349 TCGType type;
1350 uint32_t some;
1351
1352 check_size_align(oprsz, maxsz, dofs | aofs | bofs);
1353 check_overlap_3(dofs, aofs, bofs, maxsz);
1354
1355 type = 0;
1356 if (g->fniv) {
53229a77 1357 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
e1227bb6
DH		 1358 }
1359 switch (type) {
1360 case TCG_TYPE_V256:
1361 /*
1362 * Recall that ARM SVE allows vector sizes that are not a
1363 * power of 2, but always a multiple of 16. The intent is
1364 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
1365 */
1366 some = QEMU_ALIGN_DOWN(oprsz, 32);
1367 expand_3i_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256,
1368 c, g->load_dest, g->fniv);
1369 if (some == oprsz) {
1370 break;
1371 }
1372 dofs += some;
1373 aofs += some;
1374 bofs += some;
1375 oprsz -= some;
1376 maxsz -= some;
1377 /* fallthru */
1378 case TCG_TYPE_V128:
1379 expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
1380 c, g->load_dest, g->fniv);
1381 break;
1382 case TCG_TYPE_V64:
1383 expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
1384 c, g->load_dest, g->fniv);
1385 break;
1386
1387 case 0:
1388 if (g->fni8 && check_size_impl(oprsz, 8)) {
1389 expand_3i_i64(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni8);
1390 } else if (g->fni4 && check_size_impl(oprsz, 4)) {
1391 expand_3i_i32(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni4);
1392 } else {
1393 assert(g->fno != NULL);
1394 tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, c, g->fno);
53229a77 1395 oprsz = maxsz;
e1227bb6
DH		 1396 }
1397 break;
1398
1399 default:
1400 g_assert_not_reached();
1401 }
53229a77 1402 tcg_swap_vecop_list(hold_list);
e1227bb6
DH		 1403
1404 if (oprsz < maxsz) {
1405 expand_clr(dofs + oprsz, maxsz - oprsz);
1406 }
1407}
1408
db432672
RH		 1409/* Expand a vector four-operand operation. */
1410void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
1411 uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g)
1412{
53229a77
RH		 1413 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
1414 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
adb196cb
RH		 1415 TCGType type;
1416 uint32_t some;
1417
db432672
RH		 1418 check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs);
1419 check_overlap_4(dofs, aofs, bofs, cofs, maxsz);
1420
adb196cb
RH		 1421 type = 0;
1422 if (g->fniv) {
53229a77 1423 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
adb196cb
RH		 1424 }
1425 switch (type) {
1426 case TCG_TYPE_V256:
1427 /* Recall that ARM SVE allows vector sizes that are not a
1428 * power of 2, but always a multiple of 16. The intent is
1429 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
1430 */
1431 some = QEMU_ALIGN_DOWN(oprsz, 32);
db432672 1432 expand_4_vec(g->vece, dofs, aofs, bofs, cofs, some,
5d6acdd4 1433 32, TCG_TYPE_V256, g->write_aofs, g->fniv);
db432672 1434 if (some == oprsz) {
adb196cb 1435 break;
db432672
RH		 1436 }
1437 dofs += some;
1438 aofs += some;
1439 bofs += some;
1440 cofs += some;
1441 oprsz -= some;
1442 maxsz -= some;
adb196cb
RH		 1443 /* fallthru */
1444 case TCG_TYPE_V128:
db432672 1445 expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
5d6acdd4 1446 16, TCG_TYPE_V128, g->write_aofs, g->fniv);
adb196cb
RH		 1447 break;
1448 case TCG_TYPE_V64:
db432672 1449 expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
5d6acdd4 1450 8, TCG_TYPE_V64, g->write_aofs, g->fniv);
adb196cb
RH		 1451 break;
1452
1453 case 0:
1454 if (g->fni8 && check_size_impl(oprsz, 8)) {
5d6acdd4
RH		 1455 expand_4_i64(dofs, aofs, bofs, cofs, oprsz,
1456 g->write_aofs, g->fni8);
adb196cb 1457 } else if (g->fni4 && check_size_impl(oprsz, 4)) {
5d6acdd4
RH		 1458 expand_4_i32(dofs, aofs, bofs, cofs, oprsz,
1459 g->write_aofs, g->fni4);
adb196cb
RH		 1460 } else {
1461 assert(g->fno != NULL);
1462 tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs,
1463 oprsz, maxsz, g->data, g->fno);
53229a77 1464 oprsz = maxsz;
adb196cb
RH		 1465 }
1466 break;
1467
1468 default:
1469 g_assert_not_reached();
db432672 1470 }
53229a77 1471 tcg_swap_vecop_list(hold_list);
db432672 1472
db432672
RH		 1473 if (oprsz < maxsz) {
1474 expand_clr(dofs + oprsz, maxsz - oprsz);
1475 }
1476}
1477
1478/*
1479 * Expand specific vector operations.
1480 */
1481
1482static void vec_mov2(unsigned vece, TCGv_vec a, TCGv_vec b)
1483{
1484 tcg_gen_mov_vec(a, b);
1485}
1486
1487void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs,
1488 uint32_t oprsz, uint32_t maxsz)
1489{
1490 static const GVecGen2 g = {
1491 .fni8 = tcg_gen_mov_i64,
1492 .fniv = vec_mov2,
1493 .fno = gen_helper_gvec_mov,
1494 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1495 };
1496 if (dofs != aofs) {
1497 tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g);
1498 } else {
1499 check_size_align(oprsz, maxsz, dofs);
1500 if (oprsz < maxsz) {
1501 expand_clr(dofs + oprsz, maxsz - oprsz);
1502 }
1503 }
1504}
1505
1506void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz,
1507 uint32_t maxsz, TCGv_i32 in)
1508{
1509 check_size_align(oprsz, maxsz, dofs);
1510 tcg_debug_assert(vece <= MO_32);
1511 do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0);
1512}
1513
1514void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz,
1515 uint32_t maxsz, TCGv_i64 in)
1516{
1517 check_size_align(oprsz, maxsz, dofs);
1518 tcg_debug_assert(vece <= MO_64);
1519 do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0);
1520}
1521
1522void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
1523 uint32_t oprsz, uint32_t maxsz)
1524{
532ba368 1525 check_size_align(oprsz, maxsz, dofs);
37ee55a0 1526 if (vece <= MO_64) {
532ba368 1527 TCGType type = choose_vector_type(NULL, vece, oprsz, 0);
37ee55a0
RH		 1528 if (type != 0) {
1529 TCGv_vec t_vec = tcg_temp_new_vec(type);
1530 tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs);
1531 do_dup_store(type, dofs, oprsz, maxsz, t_vec);
1532 tcg_temp_free_vec(t_vec);
532ba368
RH		 1533 } else if (vece <= MO_32) {
1534 TCGv_i32 in = tcg_temp_new_i32();
1535 switch (vece) {
1536 case MO_8:
1537 tcg_gen_ld8u_i32(in, cpu_env, aofs);
1538 break;
1539 case MO_16:
1540 tcg_gen_ld16u_i32(in, cpu_env, aofs);
1541 break;
1542 default:
1543 tcg_gen_ld_i32(in, cpu_env, aofs);
1544 break;
1545 }
1546 do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0);
1547 tcg_temp_free_i32(in);
1548 } else {
1549 TCGv_i64 in = tcg_temp_new_i64();
1550 tcg_gen_ld_i64(in, cpu_env, aofs);
1551 do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0);
1552 tcg_temp_free_i64(in);
db432672 1553 }
db432672
RH		 1554 } else {
1555 /* 128-bit duplicate. */
1556 /* ??? Dup to 256-bit vector. */
1557 int i;
1558
1559 tcg_debug_assert(vece == 4);
1560 tcg_debug_assert(oprsz >= 16);
1561 if (TCG_TARGET_HAS_v128) {
1562 TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V128);
1563
1564 tcg_gen_ld_vec(in, cpu_env, aofs);
1565 for (i = 0; i < oprsz; i += 16) {
1566 tcg_gen_st_vec(in, cpu_env, dofs + i);
1567 }
1568 tcg_temp_free_vec(in);
1569 } else {
1570 TCGv_i64 in0 = tcg_temp_new_i64();
1571 TCGv_i64 in1 = tcg_temp_new_i64();
1572
1573 tcg_gen_ld_i64(in0, cpu_env, aofs);
1574 tcg_gen_ld_i64(in1, cpu_env, aofs + 8);
1575 for (i = 0; i < oprsz; i += 16) {
1576 tcg_gen_st_i64(in0, cpu_env, dofs + i);
1577 tcg_gen_st_i64(in1, cpu_env, dofs + i + 8);
1578 }
1579 tcg_temp_free_i64(in0);
1580 tcg_temp_free_i64(in1);
1581 }
532ba368
RH		 1582 if (oprsz < maxsz) {
1583 expand_clr(dofs + oprsz, maxsz - oprsz);
1584 }
db432672
RH		 1585 }
1586}
1587
44c94677
RH		 1588void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz,
1589 uint32_t maxsz, uint64_t x)
1590{
1591 check_size_align(oprsz, maxsz, dofs);
1592 do_dup(vece, dofs, oprsz, maxsz, NULL, NULL, x);
1593}
1594
db432672
RH		 1595void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
1596 uint32_t oprsz, uint32_t maxsz)
1597{
1598 static const GVecGen2 g = {
1599 .fni8 = tcg_gen_not_i64,
1600 .fniv = tcg_gen_not_vec,
1601 .fno = gen_helper_gvec_not,
1602 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1603 };
1604 tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g);
1605}
1606
1607/* Perform a vector addition using normal addition and a mask. The mask
1608 should be the sign bit of each lane. This 6-operation form is more
1609 efficient than separate additions when there are 4 or more lanes in
1610 the 64-bit operation. */
1611static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
1612{
1613 TCGv_i64 t1 = tcg_temp_new_i64();
1614 TCGv_i64 t2 = tcg_temp_new_i64();
1615 TCGv_i64 t3 = tcg_temp_new_i64();
1616
1617 tcg_gen_andc_i64(t1, a, m);
1618 tcg_gen_andc_i64(t2, b, m);
1619 tcg_gen_xor_i64(t3, a, b);
1620 tcg_gen_add_i64(d, t1, t2);
1621 tcg_gen_and_i64(t3, t3, m);
1622 tcg_gen_xor_i64(d, d, t3);
1623
1624 tcg_temp_free_i64(t1);
1625 tcg_temp_free_i64(t2);
1626 tcg_temp_free_i64(t3);
1627}
1628
1629void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1630{
1631 TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));
1632 gen_addv_mask(d, a, b, m);
1633 tcg_temp_free_i64(m);
1634}
1635
1636void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1637{
1638 TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));
1639 gen_addv_mask(d, a, b, m);
1640 tcg_temp_free_i64(m);
1641}
1642
1643void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1644{
1645 TCGv_i64 t1 = tcg_temp_new_i64();
1646 TCGv_i64 t2 = tcg_temp_new_i64();
1647
1648 tcg_gen_andi_i64(t1, a, ~0xffffffffull);
1649 tcg_gen_add_i64(t2, a, b);
1650 tcg_gen_add_i64(t1, t1, b);
1651 tcg_gen_deposit_i64(d, t1, t2, 0, 32);
1652
1653 tcg_temp_free_i64(t1);
1654 tcg_temp_free_i64(t2);
1655}
1656
53229a77
RH		 1657static const TCGOpcode vecop_list_add[] = { INDEX_op_add_vec, 0 };
1658
db432672
RH		 1659void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
1660 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1661{
1662 static const GVecGen3 g[4] = {
1663 { .fni8 = tcg_gen_vec_add8_i64,
1664 .fniv = tcg_gen_add_vec,
1665 .fno = gen_helper_gvec_add8,
53229a77 1666 .opt_opc = vecop_list_add,
db432672
RH		 1667 .vece = MO_8 },
1668 { .fni8 = tcg_gen_vec_add16_i64,
1669 .fniv = tcg_gen_add_vec,
1670 .fno = gen_helper_gvec_add16,
53229a77 1671 .opt_opc = vecop_list_add,
db432672
RH		 1672 .vece = MO_16 },
1673 { .fni4 = tcg_gen_add_i32,
1674 .fniv = tcg_gen_add_vec,
1675 .fno = gen_helper_gvec_add32,
53229a77 1676 .opt_opc = vecop_list_add,
db432672
RH		 1677 .vece = MO_32 },
1678 { .fni8 = tcg_gen_add_i64,
1679 .fniv = tcg_gen_add_vec,
1680 .fno = gen_helper_gvec_add64,
53229a77 1681 .opt_opc = vecop_list_add,
db432672
RH		 1682 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1683 .vece = MO_64 },
1684 };
1685
1686 tcg_debug_assert(vece <= MO_64);
1687 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
1688}
1689
22fc3527
RH		 1690void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,
1691 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
1692{
1693 static const GVecGen2s g[4] = {
1694 { .fni8 = tcg_gen_vec_add8_i64,
1695 .fniv = tcg_gen_add_vec,
1696 .fno = gen_helper_gvec_adds8,
53229a77 1697 .opt_opc = vecop_list_add,
22fc3527
RH		 1698 .vece = MO_8 },
1699 { .fni8 = tcg_gen_vec_add16_i64,
1700 .fniv = tcg_gen_add_vec,
1701 .fno = gen_helper_gvec_adds16,
53229a77 1702 .opt_opc = vecop_list_add,
22fc3527
RH		 1703 .vece = MO_16 },
1704 { .fni4 = tcg_gen_add_i32,
1705 .fniv = tcg_gen_add_vec,
1706 .fno = gen_helper_gvec_adds32,
53229a77 1707 .opt_opc = vecop_list_add,
22fc3527
RH		 1708 .vece = MO_32 },
1709 { .fni8 = tcg_gen_add_i64,
1710 .fniv = tcg_gen_add_vec,
1711 .fno = gen_helper_gvec_adds64,
53229a77 1712 .opt_opc = vecop_list_add,
22fc3527
RH		 1713 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1714 .vece = MO_64 },
1715 };
1716
1717 tcg_debug_assert(vece <= MO_64);
1718 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);
1719}
1720
1721void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs,
1722 int64_t c, uint32_t oprsz, uint32_t maxsz)
1723{
1724 TCGv_i64 tmp = tcg_const_i64(c);
1725 tcg_gen_gvec_adds(vece, dofs, aofs, tmp, oprsz, maxsz);
1726 tcg_temp_free_i64(tmp);
1727}
1728
53229a77
RH		 1729static const TCGOpcode vecop_list_sub[] = { INDEX_op_sub_vec, 0 };
1730
22fc3527
RH		 1731void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,
1732 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
1733{
1734 static const GVecGen2s g[4] = {
1735 { .fni8 = tcg_gen_vec_sub8_i64,
1736 .fniv = tcg_gen_sub_vec,
1737 .fno = gen_helper_gvec_subs8,
53229a77 1738 .opt_opc = vecop_list_sub,
22fc3527
RH		 1739 .vece = MO_8 },
1740 { .fni8 = tcg_gen_vec_sub16_i64,
1741 .fniv = tcg_gen_sub_vec,
1742 .fno = gen_helper_gvec_subs16,
53229a77 1743 .opt_opc = vecop_list_sub,
22fc3527
RH		 1744 .vece = MO_16 },
1745 { .fni4 = tcg_gen_sub_i32,
1746 .fniv = tcg_gen_sub_vec,
1747 .fno = gen_helper_gvec_subs32,
53229a77 1748 .opt_opc = vecop_list_sub,
22fc3527
RH		 1749 .vece = MO_32 },
1750 { .fni8 = tcg_gen_sub_i64,
1751 .fniv = tcg_gen_sub_vec,
1752 .fno = gen_helper_gvec_subs64,
53229a77 1753 .opt_opc = vecop_list_sub,
22fc3527
RH		 1754 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1755 .vece = MO_64 },
1756 };
1757
1758 tcg_debug_assert(vece <= MO_64);
1759 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);
1760}
1761
db432672
RH		 1762/* Perform a vector subtraction using normal subtraction and a mask.
1763 Compare gen_addv_mask above. */
1764static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
1765{
1766 TCGv_i64 t1 = tcg_temp_new_i64();
1767 TCGv_i64 t2 = tcg_temp_new_i64();
1768 TCGv_i64 t3 = tcg_temp_new_i64();
1769
1770 tcg_gen_or_i64(t1, a, m);
1771 tcg_gen_andc_i64(t2, b, m);
1772 tcg_gen_eqv_i64(t3, a, b);
1773 tcg_gen_sub_i64(d, t1, t2);
1774 tcg_gen_and_i64(t3, t3, m);
1775 tcg_gen_xor_i64(d, d, t3);
1776
1777 tcg_temp_free_i64(t1);
1778 tcg_temp_free_i64(t2);
1779 tcg_temp_free_i64(t3);
1780}
1781
1782void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1783{
1784 TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));
1785 gen_subv_mask(d, a, b, m);
1786 tcg_temp_free_i64(m);
1787}
1788
1789void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1790{
1791 TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));
1792 gen_subv_mask(d, a, b, m);
1793 tcg_temp_free_i64(m);
1794}
1795
1796void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1797{
1798 TCGv_i64 t1 = tcg_temp_new_i64();
1799 TCGv_i64 t2 = tcg_temp_new_i64();
1800
1801 tcg_gen_andi_i64(t1, b, ~0xffffffffull);
1802 tcg_gen_sub_i64(t2, a, b);
1803 tcg_gen_sub_i64(t1, a, t1);
1804 tcg_gen_deposit_i64(d, t1, t2, 0, 32);
1805
1806 tcg_temp_free_i64(t1);
1807 tcg_temp_free_i64(t2);
1808}
1809
1810void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
1811 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1812{
1813 static const GVecGen3 g[4] = {
1814 { .fni8 = tcg_gen_vec_sub8_i64,
1815 .fniv = tcg_gen_sub_vec,
1816 .fno = gen_helper_gvec_sub8,
53229a77 1817 .opt_opc = vecop_list_sub,
db432672
RH		 1818 .vece = MO_8 },
1819 { .fni8 = tcg_gen_vec_sub16_i64,
1820 .fniv = tcg_gen_sub_vec,
1821 .fno = gen_helper_gvec_sub16,
53229a77 1822 .opt_opc = vecop_list_sub,
db432672
RH		 1823 .vece = MO_16 },
1824 { .fni4 = tcg_gen_sub_i32,
1825 .fniv = tcg_gen_sub_vec,
1826 .fno = gen_helper_gvec_sub32,
53229a77 1827 .opt_opc = vecop_list_sub,
db432672
RH		 1828 .vece = MO_32 },
1829 { .fni8 = tcg_gen_sub_i64,
1830 .fniv = tcg_gen_sub_vec,
1831 .fno = gen_helper_gvec_sub64,
53229a77 1832 .opt_opc = vecop_list_sub,
db432672
RH		 1833 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1834 .vece = MO_64 },
1835 };
1836
1837 tcg_debug_assert(vece <= MO_64);
1838 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
1839}
1840
53229a77
RH		 1841static const TCGOpcode vecop_list_mul[] = { INDEX_op_mul_vec, 0 };
1842
3774030a
RH		 1843void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
1844 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1845{
1846 static const GVecGen3 g[4] = {
1847 { .fniv = tcg_gen_mul_vec,
1848 .fno = gen_helper_gvec_mul8,
53229a77 1849 .opt_opc = vecop_list_mul,
3774030a
RH		 1850 .vece = MO_8 },
1851 { .fniv = tcg_gen_mul_vec,
1852 .fno = gen_helper_gvec_mul16,
53229a77 1853 .opt_opc = vecop_list_mul,
3774030a
RH		 1854 .vece = MO_16 },
1855 { .fni4 = tcg_gen_mul_i32,
1856 .fniv = tcg_gen_mul_vec,
1857 .fno = gen_helper_gvec_mul32,
53229a77 1858 .opt_opc = vecop_list_mul,
3774030a
RH		 1859 .vece = MO_32 },
1860 { .fni8 = tcg_gen_mul_i64,
1861 .fniv = tcg_gen_mul_vec,
1862 .fno = gen_helper_gvec_mul64,
53229a77 1863 .opt_opc = vecop_list_mul,
3774030a
RH		 1864 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1865 .vece = MO_64 },
1866 };
1867
1868 tcg_debug_assert(vece <= MO_64);
1869 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
1870}
1871
22fc3527
RH		 1872void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,
1873 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
1874{
1875 static const GVecGen2s g[4] = {
1876 { .fniv = tcg_gen_mul_vec,
1877 .fno = gen_helper_gvec_muls8,
53229a77 1878 .opt_opc = vecop_list_mul,
22fc3527
RH		 1879 .vece = MO_8 },
1880 { .fniv = tcg_gen_mul_vec,
1881 .fno = gen_helper_gvec_muls16,
53229a77 1882 .opt_opc = vecop_list_mul,
22fc3527
RH		 1883 .vece = MO_16 },
1884 { .fni4 = tcg_gen_mul_i32,
1885 .fniv = tcg_gen_mul_vec,
1886 .fno = gen_helper_gvec_muls32,
53229a77 1887 .opt_opc = vecop_list_mul,
22fc3527
RH		 1888 .vece = MO_32 },
1889 { .fni8 = tcg_gen_mul_i64,
1890 .fniv = tcg_gen_mul_vec,
1891 .fno = gen_helper_gvec_muls64,
53229a77 1892 .opt_opc = vecop_list_mul,
22fc3527
RH		 1893 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1894 .vece = MO_64 },
1895 };
1896
1897 tcg_debug_assert(vece <= MO_64);
1898 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);
1899}
1900
1901void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs,
1902 int64_t c, uint32_t oprsz, uint32_t maxsz)
1903{
1904 TCGv_i64 tmp = tcg_const_i64(c);
1905 tcg_gen_gvec_muls(vece, dofs, aofs, tmp, oprsz, maxsz);
1906 tcg_temp_free_i64(tmp);
1907}
1908
f49b12c6
RH		 1909void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
1910 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1911{
53229a77 1912 static const TCGOpcode vecop_list[] = { INDEX_op_ssadd_vec, 0 };
f49b12c6 1913 static const GVecGen3 g[4] = {
8afaf050
RH		 1914 { .fniv = tcg_gen_ssadd_vec,
1915 .fno = gen_helper_gvec_ssadd8,
53229a77 1916 .opt_opc = vecop_list,
8afaf050
RH		 1917 .vece = MO_8 },
1918 { .fniv = tcg_gen_ssadd_vec,
1919 .fno = gen_helper_gvec_ssadd16,
53229a77 1920 .opt_opc = vecop_list,
8afaf050
RH		 1921 .vece = MO_16 },
1922 { .fniv = tcg_gen_ssadd_vec,
1923 .fno = gen_helper_gvec_ssadd32,
53229a77 1924 .opt_opc = vecop_list,
8afaf050
RH		 1925 .vece = MO_32 },
1926 { .fniv = tcg_gen_ssadd_vec,
1927 .fno = gen_helper_gvec_ssadd64,
53229a77 1928 .opt_opc = vecop_list,
8afaf050 1929 .vece = MO_64 },
f49b12c6
RH		 1930 };
1931 tcg_debug_assert(vece <= MO_64);
1932 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
1933}
1934
1935void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,
1936 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1937{
53229a77 1938 static const TCGOpcode vecop_list[] = { INDEX_op_sssub_vec, 0 };
f49b12c6 1939 static const GVecGen3 g[4] = {
8afaf050
RH		 1940 { .fniv = tcg_gen_sssub_vec,
1941 .fno = gen_helper_gvec_sssub8,
53229a77 1942 .opt_opc = vecop_list,
8afaf050
RH		 1943 .vece = MO_8 },
1944 { .fniv = tcg_gen_sssub_vec,
1945 .fno = gen_helper_gvec_sssub16,
53229a77 1946 .opt_opc = vecop_list,
8afaf050
RH		 1947 .vece = MO_16 },
1948 { .fniv = tcg_gen_sssub_vec,
1949 .fno = gen_helper_gvec_sssub32,
53229a77 1950 .opt_opc = vecop_list,
8afaf050
RH		 1951 .vece = MO_32 },
1952 { .fniv = tcg_gen_sssub_vec,
1953 .fno = gen_helper_gvec_sssub64,
53229a77 1954 .opt_opc = vecop_list,
8afaf050 1955 .vece = MO_64 },
f49b12c6
RH		 1956 };
1957 tcg_debug_assert(vece <= MO_64);
1958 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
1959}
1960
8afaf050 1961static void tcg_gen_usadd_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
f49b12c6
RH		 1962{
1963 TCGv_i32 max = tcg_const_i32(-1);
1964 tcg_gen_add_i32(d, a, b);
1965 tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d);
1966 tcg_temp_free_i32(max);
1967}
1968
8afaf050 1969static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
f49b12c6
RH		 1970{
1971 TCGv_i64 max = tcg_const_i64(-1);
1972 tcg_gen_add_i64(d, a, b);
1973 tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d);
1974 tcg_temp_free_i64(max);
1975}
1976
1977void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,
1978 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1979{
53229a77 1980 static const TCGOpcode vecop_list[] = { INDEX_op_usadd_vec, 0 };
f49b12c6 1981 static const GVecGen3 g[4] = {
8afaf050
RH		 1982 { .fniv = tcg_gen_usadd_vec,
1983 .fno = gen_helper_gvec_usadd8,
53229a77 1984 .opt_opc = vecop_list,
8afaf050
RH		 1985 .vece = MO_8 },
1986 { .fniv = tcg_gen_usadd_vec,
1987 .fno = gen_helper_gvec_usadd16,
53229a77 1988 .opt_opc = vecop_list,
8afaf050
RH		 1989 .vece = MO_16 },
1990 { .fni4 = tcg_gen_usadd_i32,
1991 .fniv = tcg_gen_usadd_vec,
f49b12c6 1992 .fno = gen_helper_gvec_usadd32,
53229a77 1993 .opt_opc = vecop_list,
f49b12c6 1994 .vece = MO_32 },
8afaf050
RH		 1995 { .fni8 = tcg_gen_usadd_i64,
1996 .fniv = tcg_gen_usadd_vec,
f49b12c6 1997 .fno = gen_helper_gvec_usadd64,
53229a77 1998 .opt_opc = vecop_list,
f49b12c6
RH		 1999 .vece = MO_64 }
2000 };
2001 tcg_debug_assert(vece <= MO_64);
2002 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
2003}
2004
8afaf050 2005static void tcg_gen_ussub_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
f49b12c6
RH		 2006{
2007 TCGv_i32 min = tcg_const_i32(0);
2008 tcg_gen_sub_i32(d, a, b);
2009 tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d);
2010 tcg_temp_free_i32(min);
2011}
2012
8afaf050 2013static void tcg_gen_ussub_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
f49b12c6
RH		 2014{
2015 TCGv_i64 min = tcg_const_i64(0);
2016 tcg_gen_sub_i64(d, a, b);
2017 tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d);
2018 tcg_temp_free_i64(min);
2019}
2020
2021void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,
2022 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2023{
53229a77 2024 static const TCGOpcode vecop_list[] = { INDEX_op_ussub_vec, 0 };
f49b12c6 2025 static const GVecGen3 g[4] = {
8afaf050
RH		 2026 { .fniv = tcg_gen_ussub_vec,
2027 .fno = gen_helper_gvec_ussub8,
53229a77 2028 .opt_opc = vecop_list,
8afaf050
RH		 2029 .vece = MO_8 },
2030 { .fniv = tcg_gen_ussub_vec,
2031 .fno = gen_helper_gvec_ussub16,
53229a77 2032 .opt_opc = vecop_list,
8afaf050
RH		 2033 .vece = MO_16 },
2034 { .fni4 = tcg_gen_ussub_i32,
2035 .fniv = tcg_gen_ussub_vec,
f49b12c6 2036 .fno = gen_helper_gvec_ussub32,
53229a77 2037 .opt_opc = vecop_list,
f49b12c6 2038 .vece = MO_32 },
8afaf050
RH		 2039 { .fni8 = tcg_gen_ussub_i64,
2040 .fniv = tcg_gen_ussub_vec,
f49b12c6 2041 .fno = gen_helper_gvec_ussub64,
53229a77 2042 .opt_opc = vecop_list,
f49b12c6
RH		 2043 .vece = MO_64 }
2044 };
2045 tcg_debug_assert(vece <= MO_64);
2046 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
dd0a0fcd
RH		 2047}
2048
2049void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,
2050 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2051{
53229a77 2052 static const TCGOpcode vecop_list[] = { INDEX_op_smin_vec, 0 };
dd0a0fcd
RH		 2053 static const GVecGen3 g[4] = {
2054 { .fniv = tcg_gen_smin_vec,
2055 .fno = gen_helper_gvec_smin8,
53229a77 2056 .opt_opc = vecop_list,
dd0a0fcd
RH		 2057 .vece = MO_8 },
2058 { .fniv = tcg_gen_smin_vec,
2059 .fno = gen_helper_gvec_smin16,
53229a77 2060 .opt_opc = vecop_list,
dd0a0fcd
RH		 2061 .vece = MO_16 },
2062 { .fni4 = tcg_gen_smin_i32,
2063 .fniv = tcg_gen_smin_vec,
2064 .fno = gen_helper_gvec_smin32,
53229a77 2065 .opt_opc = vecop_list,
dd0a0fcd
RH		 2066 .vece = MO_32 },
2067 { .fni8 = tcg_gen_smin_i64,
2068 .fniv = tcg_gen_smin_vec,
2069 .fno = gen_helper_gvec_smin64,
53229a77 2070 .opt_opc = vecop_list,
dd0a0fcd
RH		 2071 .vece = MO_64 }
2072 };
2073 tcg_debug_assert(vece <= MO_64);
2074 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
2075}
2076
2077void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,
2078 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2079{
53229a77 2080 static const TCGOpcode vecop_list[] = { INDEX_op_umin_vec, 0 };
dd0a0fcd
RH		 2081 static const GVecGen3 g[4] = {
2082 { .fniv = tcg_gen_umin_vec,
2083 .fno = gen_helper_gvec_umin8,
53229a77 2084 .opt_opc = vecop_list,
dd0a0fcd
RH		 2085 .vece = MO_8 },
2086 { .fniv = tcg_gen_umin_vec,
2087 .fno = gen_helper_gvec_umin16,
53229a77 2088 .opt_opc = vecop_list,
dd0a0fcd
RH		 2089 .vece = MO_16 },
2090 { .fni4 = tcg_gen_umin_i32,
2091 .fniv = tcg_gen_umin_vec,
2092 .fno = gen_helper_gvec_umin32,
53229a77 2093 .opt_opc = vecop_list,
dd0a0fcd
RH		 2094 .vece = MO_32 },
2095 { .fni8 = tcg_gen_umin_i64,
2096 .fniv = tcg_gen_umin_vec,
2097 .fno = gen_helper_gvec_umin64,
53229a77 2098 .opt_opc = vecop_list,
dd0a0fcd
RH		 2099 .vece = MO_64 }
2100 };
2101 tcg_debug_assert(vece <= MO_64);
2102 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
2103}
2104
2105void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,
2106 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2107{
53229a77 2108 static const TCGOpcode vecop_list[] = { INDEX_op_smax_vec, 0 };
dd0a0fcd
RH		 2109 static const GVecGen3 g[4] = {
2110 { .fniv = tcg_gen_smax_vec,
2111 .fno = gen_helper_gvec_smax8,
53229a77 2112 .opt_opc = vecop_list,
dd0a0fcd
RH		 2113 .vece = MO_8 },
2114 { .fniv = tcg_gen_smax_vec,
2115 .fno = gen_helper_gvec_smax16,
53229a77 2116 .opt_opc = vecop_list,
dd0a0fcd
RH		 2117 .vece = MO_16 },
2118 { .fni4 = tcg_gen_smax_i32,
2119 .fniv = tcg_gen_smax_vec,
2120 .fno = gen_helper_gvec_smax32,
53229a77 2121 .opt_opc = vecop_list,
dd0a0fcd
RH		 2122 .vece = MO_32 },
2123 { .fni8 = tcg_gen_smax_i64,
2124 .fniv = tcg_gen_smax_vec,
2125 .fno = gen_helper_gvec_smax64,
53229a77 2126 .opt_opc = vecop_list,
dd0a0fcd
RH		 2127 .vece = MO_64 }
2128 };
2129 tcg_debug_assert(vece <= MO_64);
2130 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
2131}
2132
2133void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,
2134 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2135{
53229a77 2136 static const TCGOpcode vecop_list[] = { INDEX_op_umax_vec, 0 };
dd0a0fcd
RH		 2137 static const GVecGen3 g[4] = {
2138 { .fniv = tcg_gen_umax_vec,
2139 .fno = gen_helper_gvec_umax8,
53229a77 2140 .opt_opc = vecop_list,
dd0a0fcd
RH		 2141 .vece = MO_8 },
2142 { .fniv = tcg_gen_umax_vec,
2143 .fno = gen_helper_gvec_umax16,
53229a77 2144 .opt_opc = vecop_list,
dd0a0fcd
RH		 2145 .vece = MO_16 },
2146 { .fni4 = tcg_gen_umax_i32,
2147 .fniv = tcg_gen_umax_vec,
2148 .fno = gen_helper_gvec_umax32,
53229a77 2149 .opt_opc = vecop_list,
dd0a0fcd
RH		 2150 .vece = MO_32 },
2151 { .fni8 = tcg_gen_umax_i64,
2152 .fniv = tcg_gen_umax_vec,
2153 .fno = gen_helper_gvec_umax64,
53229a77 2154 .opt_opc = vecop_list,
dd0a0fcd
RH		 2155 .vece = MO_64 }
2156 };
2157 tcg_debug_assert(vece <= MO_64);
2158 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
f49b12c6
RH		 2159}
2160
db432672
RH		 2161/* Perform a vector negation using normal negation and a mask.
2162 Compare gen_subv_mask above. */
2163static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
2164{
2165 TCGv_i64 t2 = tcg_temp_new_i64();
2166 TCGv_i64 t3 = tcg_temp_new_i64();
2167
2168 tcg_gen_andc_i64(t3, m, b);
2169 tcg_gen_andc_i64(t2, b, m);
2170 tcg_gen_sub_i64(d, m, t2);
2171 tcg_gen_xor_i64(d, d, t3);
2172
2173 tcg_temp_free_i64(t2);
2174 tcg_temp_free_i64(t3);
2175}
2176
2177void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b)
2178{
2179 TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));
2180 gen_negv_mask(d, b, m);
2181 tcg_temp_free_i64(m);
2182}
2183
2184void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 b)
2185{
2186 TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));
2187 gen_negv_mask(d, b, m);
2188 tcg_temp_free_i64(m);
2189}
2190
2191void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 b)
2192{
2193 TCGv_i64 t1 = tcg_temp_new_i64();
2194 TCGv_i64 t2 = tcg_temp_new_i64();
2195
2196 tcg_gen_andi_i64(t1, b, ~0xffffffffull);
2197 tcg_gen_neg_i64(t2, b);
2198 tcg_gen_neg_i64(t1, t1);
2199 tcg_gen_deposit_i64(d, t1, t2, 0, 32);
2200
2201 tcg_temp_free_i64(t1);
2202 tcg_temp_free_i64(t2);
2203}
2204
2205void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,
2206 uint32_t oprsz, uint32_t maxsz)
2207{
53229a77 2208 static const TCGOpcode vecop_list[] = { INDEX_op_neg_vec, 0 };
db432672
RH		 2209 static const GVecGen2 g[4] = {
2210 { .fni8 = tcg_gen_vec_neg8_i64,
2211 .fniv = tcg_gen_neg_vec,
2212 .fno = gen_helper_gvec_neg8,
53229a77 2213 .opt_opc = vecop_list,
db432672
RH		 2214 .vece = MO_8 },
2215 { .fni8 = tcg_gen_vec_neg16_i64,
2216 .fniv = tcg_gen_neg_vec,
2217 .fno = gen_helper_gvec_neg16,
53229a77 2218 .opt_opc = vecop_list,
db432672
RH		 2219 .vece = MO_16 },
2220 { .fni4 = tcg_gen_neg_i32,
2221 .fniv = tcg_gen_neg_vec,
2222 .fno = gen_helper_gvec_neg32,
53229a77 2223 .opt_opc = vecop_list,
db432672
RH		 2224 .vece = MO_32 },
2225 { .fni8 = tcg_gen_neg_i64,
2226 .fniv = tcg_gen_neg_vec,
2227 .fno = gen_helper_gvec_neg64,
53229a77 2228 .opt_opc = vecop_list,
db432672
RH		 2229 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2230 .vece = MO_64 },
2231 };
2232
2233 tcg_debug_assert(vece <= MO_64);
2234 tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]);
2235}
2236
bcefc902
RH		 2237static void gen_absv_mask(TCGv_i64 d, TCGv_i64 b, unsigned vece)
2238{
2239 TCGv_i64 t = tcg_temp_new_i64();
2240 int nbit = 8 << vece;
2241
2242 /* Create -1 for each negative element. */
2243 tcg_gen_shri_i64(t, b, nbit - 1);
2244 tcg_gen_andi_i64(t, t, dup_const(vece, 1));
2245 tcg_gen_muli_i64(t, t, (1 << nbit) - 1);
2246
2247 /*
2248 * Invert (via xor -1) and add one (via sub -1).
2249 * Because of the ordering the msb is cleared,
2250 * so we never have carry into the next element.
2251 */
2252 tcg_gen_xor_i64(d, b, t);
2253 tcg_gen_sub_i64(d, d, t);
2254
2255 tcg_temp_free_i64(t);
2256}
2257
2258static void tcg_gen_vec_abs8_i64(TCGv_i64 d, TCGv_i64 b)
2259{
2260 gen_absv_mask(d, b, MO_8);
2261}
2262
2263static void tcg_gen_vec_abs16_i64(TCGv_i64 d, TCGv_i64 b)
2264{
2265 gen_absv_mask(d, b, MO_16);
2266}
2267
2268void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,
2269 uint32_t oprsz, uint32_t maxsz)
2270{
2271 static const TCGOpcode vecop_list[] = { INDEX_op_abs_vec, 0 };
2272 static const GVecGen2 g[4] = {
2273 { .fni8 = tcg_gen_vec_abs8_i64,
2274 .fniv = tcg_gen_abs_vec,
2275 .fno = gen_helper_gvec_abs8,
2276 .opt_opc = vecop_list,
2277 .vece = MO_8 },
2278 { .fni8 = tcg_gen_vec_abs16_i64,
2279 .fniv = tcg_gen_abs_vec,
2280 .fno = gen_helper_gvec_abs16,
2281 .opt_opc = vecop_list,
2282 .vece = MO_16 },
2283 { .fni4 = tcg_gen_abs_i32,
2284 .fniv = tcg_gen_abs_vec,
2285 .fno = gen_helper_gvec_abs32,
2286 .opt_opc = vecop_list,
2287 .vece = MO_32 },
2288 { .fni8 = tcg_gen_abs_i64,
2289 .fniv = tcg_gen_abs_vec,
2290 .fno = gen_helper_gvec_abs64,
2291 .opt_opc = vecop_list,
2292 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2293 .vece = MO_64 },
2294 };
2295
2296 tcg_debug_assert(vece <= MO_64);
2297 tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]);
2298}
2299
db432672
RH		 2300void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
2301 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2302{
2303 static const GVecGen3 g = {
2304 .fni8 = tcg_gen_and_i64,
2305 .fniv = tcg_gen_and_vec,
2306 .fno = gen_helper_gvec_and,
db432672
RH		 2307 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2308 };
9a9eda78
RH		 2309
2310 if (aofs == bofs) {
2311 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
2312 } else {
2313 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2314 }
db432672
RH		 2315}
2316
2317void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
2318 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2319{
2320 static const GVecGen3 g = {
2321 .fni8 = tcg_gen_or_i64,
2322 .fniv = tcg_gen_or_vec,
2323 .fno = gen_helper_gvec_or,
db432672
RH		 2324 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2325 };
9a9eda78
RH		 2326
2327 if (aofs == bofs) {
2328 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
2329 } else {
2330 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2331 }
db432672
RH		 2332}
2333
2334void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
2335 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2336{
2337 static const GVecGen3 g = {
2338 .fni8 = tcg_gen_xor_i64,
2339 .fniv = tcg_gen_xor_vec,
2340 .fno = gen_helper_gvec_xor,
db432672
RH		 2341 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2342 };
9a9eda78
RH		 2343
2344 if (aofs == bofs) {
03ddb6f3 2345 tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0);
9a9eda78
RH		 2346 } else {
2347 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2348 }
db432672
RH		 2349}
2350
2351void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
2352 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2353{
2354 static const GVecGen3 g = {
2355 .fni8 = tcg_gen_andc_i64,
2356 .fniv = tcg_gen_andc_vec,
2357 .fno = gen_helper_gvec_andc,
db432672
RH		 2358 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2359 };
9a9eda78
RH		 2360
2361 if (aofs == bofs) {
03ddb6f3 2362 tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0);
9a9eda78
RH		 2363 } else {
2364 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2365 }
db432672
RH		 2366}
2367
2368void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
2369 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2370{
2371 static const GVecGen3 g = {
2372 .fni8 = tcg_gen_orc_i64,
2373 .fniv = tcg_gen_orc_vec,
2374 .fno = gen_helper_gvec_orc,
db432672
RH		 2375 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2376 };
9a9eda78
RH		 2377
2378 if (aofs == bofs) {
03ddb6f3 2379 tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1);
9a9eda78 2380 } else {
f550805d
RH		 2381 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2382 }
2383}
2384
2385void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs,
2386 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2387{
2388 static const GVecGen3 g = {
2389 .fni8 = tcg_gen_nand_i64,
2390 .fniv = tcg_gen_nand_vec,
2391 .fno = gen_helper_gvec_nand,
2392 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2393 };
2394
2395 if (aofs == bofs) {
2396 tcg_gen_gvec_not(vece, dofs, aofs, oprsz, maxsz);
2397 } else {
2398 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2399 }
2400}
2401
2402void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs,
2403 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2404{
2405 static const GVecGen3 g = {
2406 .fni8 = tcg_gen_nor_i64,
2407 .fniv = tcg_gen_nor_vec,
2408 .fno = gen_helper_gvec_nor,
2409 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2410 };
2411
2412 if (aofs == bofs) {
2413 tcg_gen_gvec_not(vece, dofs, aofs, oprsz, maxsz);
2414 } else {
2415 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2416 }
2417}
2418
2419void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs,
2420 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2421{
2422 static const GVecGen3 g = {
2423 .fni8 = tcg_gen_eqv_i64,
2424 .fniv = tcg_gen_eqv_vec,
2425 .fno = gen_helper_gvec_eqv,
2426 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2427 };
2428
2429 if (aofs == bofs) {
03ddb6f3 2430 tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1);
f550805d 2431 } else {
9a9eda78
RH		 2432 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2433 }
db432672 2434}
d0ec9796 2435
22fc3527
RH		 2436static const GVecGen2s gop_ands = {
2437 .fni8 = tcg_gen_and_i64,
2438 .fniv = tcg_gen_and_vec,
2439 .fno = gen_helper_gvec_ands,
22fc3527
RH		 2440 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2441 .vece = MO_64
2442};
2443
2444void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs,
2445 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
2446{
2447 TCGv_i64 tmp = tcg_temp_new_i64();
2448 gen_dup_i64(vece, tmp, c);
2449 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands);
2450 tcg_temp_free_i64(tmp);
2451}
2452
2453void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs,
2454 int64_t c, uint32_t oprsz, uint32_t maxsz)
2455{
2456 TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c));
2457 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands);
2458 tcg_temp_free_i64(tmp);
2459}
2460
2461static const GVecGen2s gop_xors = {
2462 .fni8 = tcg_gen_xor_i64,
2463 .fniv = tcg_gen_xor_vec,
2464 .fno = gen_helper_gvec_xors,
22fc3527
RH		 2465 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2466 .vece = MO_64
2467};
2468
2469void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs,
2470 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
2471{
2472 TCGv_i64 tmp = tcg_temp_new_i64();
2473 gen_dup_i64(vece, tmp, c);
2474 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors);
2475 tcg_temp_free_i64(tmp);
2476}
2477
2478void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs,
2479 int64_t c, uint32_t oprsz, uint32_t maxsz)
2480{
2481 TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c));
2482 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors);
2483 tcg_temp_free_i64(tmp);
2484}
2485
2486static const GVecGen2s gop_ors = {
2487 .fni8 = tcg_gen_or_i64,
2488 .fniv = tcg_gen_or_vec,
2489 .fno = gen_helper_gvec_ors,
22fc3527
RH		 2490 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2491 .vece = MO_64
2492};
2493
2494void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,
2495 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
2496{
2497 TCGv_i64 tmp = tcg_temp_new_i64();
2498 gen_dup_i64(vece, tmp, c);
2499 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors);
2500 tcg_temp_free_i64(tmp);
2501}
2502
2503void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs,
2504 int64_t c, uint32_t oprsz, uint32_t maxsz)
2505{
2506 TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c));
2507 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors);
2508 tcg_temp_free_i64(tmp);
2509}
2510
d0ec9796
RH		 2511void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
2512{
2513 uint64_t mask = dup_const(MO_8, 0xff << c);
2514 tcg_gen_shli_i64(d, a, c);
2515 tcg_gen_andi_i64(d, d, mask);
2516}
2517
2518void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
2519{
2520 uint64_t mask = dup_const(MO_16, 0xffff << c);
2521 tcg_gen_shli_i64(d, a, c);
2522 tcg_gen_andi_i64(d, d, mask);
2523}
2524
2525void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
2526 int64_t shift, uint32_t oprsz, uint32_t maxsz)
2527{
53229a77 2528 static const TCGOpcode vecop_list[] = { INDEX_op_shli_vec, 0 };
d0ec9796
RH		 2529 static const GVecGen2i g[4] = {
2530 { .fni8 = tcg_gen_vec_shl8i_i64,
2531 .fniv = tcg_gen_shli_vec,
2532 .fno = gen_helper_gvec_shl8i,
53229a77 2533 .opt_opc = vecop_list,
d0ec9796
RH		 2534 .vece = MO_8 },
2535 { .fni8 = tcg_gen_vec_shl16i_i64,
2536 .fniv = tcg_gen_shli_vec,
2537 .fno = gen_helper_gvec_shl16i,
53229a77 2538 .opt_opc = vecop_list,
d0ec9796
RH		 2539 .vece = MO_16 },
2540 { .fni4 = tcg_gen_shli_i32,
2541 .fniv = tcg_gen_shli_vec,
2542 .fno = gen_helper_gvec_shl32i,
53229a77 2543 .opt_opc = vecop_list,
d0ec9796
RH		 2544 .vece = MO_32 },
2545 { .fni8 = tcg_gen_shli_i64,
2546 .fniv = tcg_gen_shli_vec,
2547 .fno = gen_helper_gvec_shl64i,
53229a77 2548 .opt_opc = vecop_list,
d0ec9796
RH		 2549 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2550 .vece = MO_64 },
2551 };
2552
2553 tcg_debug_assert(vece <= MO_64);
2554 tcg_debug_assert(shift >= 0 && shift < (8 << vece));
2555 if (shift == 0) {
2556 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
2557 } else {
2558 tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]);
2559 }
2560}
2561
2562void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
2563{
2564 uint64_t mask = dup_const(MO_8, 0xff >> c);
2565 tcg_gen_shri_i64(d, a, c);
2566 tcg_gen_andi_i64(d, d, mask);
2567}
2568
2569void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
2570{
2571 uint64_t mask = dup_const(MO_16, 0xffff >> c);
2572 tcg_gen_shri_i64(d, a, c);
2573 tcg_gen_andi_i64(d, d, mask);
2574}
2575
2576void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
2577 int64_t shift, uint32_t oprsz, uint32_t maxsz)
2578{
53229a77 2579 static const TCGOpcode vecop_list[] = { INDEX_op_shri_vec, 0 };
d0ec9796
RH		 2580 static const GVecGen2i g[4] = {
2581 { .fni8 = tcg_gen_vec_shr8i_i64,
2582 .fniv = tcg_gen_shri_vec,
2583 .fno = gen_helper_gvec_shr8i,
53229a77 2584 .opt_opc = vecop_list,
d0ec9796
RH		 2585 .vece = MO_8 },
2586 { .fni8 = tcg_gen_vec_shr16i_i64,
2587 .fniv = tcg_gen_shri_vec,
2588 .fno = gen_helper_gvec_shr16i,
53229a77 2589 .opt_opc = vecop_list,
d0ec9796
RH		 2590 .vece = MO_16 },
2591 { .fni4 = tcg_gen_shri_i32,
2592 .fniv = tcg_gen_shri_vec,
2593 .fno = gen_helper_gvec_shr32i,
53229a77 2594 .opt_opc = vecop_list,
d0ec9796
RH		 2595 .vece = MO_32 },
2596 { .fni8 = tcg_gen_shri_i64,
2597 .fniv = tcg_gen_shri_vec,
2598 .fno = gen_helper_gvec_shr64i,
53229a77 2599 .opt_opc = vecop_list,
d0ec9796
RH		 2600 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2601 .vece = MO_64 },
2602 };
2603
2604 tcg_debug_assert(vece <= MO_64);
2605 tcg_debug_assert(shift >= 0 && shift < (8 << vece));
2606 if (shift == 0) {
2607 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
2608 } else {
2609 tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]);
2610 }
2611}
2612
2613void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
2614{
2615 uint64_t s_mask = dup_const(MO_8, 0x80 >> c);
2616 uint64_t c_mask = dup_const(MO_8, 0xff >> c);
2617 TCGv_i64 s = tcg_temp_new_i64();
2618
2619 tcg_gen_shri_i64(d, a, c);
2620 tcg_gen_andi_i64(s, d, s_mask); /* isolate (shifted) sign bit */
2621 tcg_gen_muli_i64(s, s, (2 << c) - 2); /* replicate isolated signs */
2622 tcg_gen_andi_i64(d, d, c_mask); /* clear out bits above sign */
2623 tcg_gen_or_i64(d, d, s); /* include sign extension */
2624 tcg_temp_free_i64(s);
2625}
2626
2627void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
2628{
2629 uint64_t s_mask = dup_const(MO_16, 0x8000 >> c);
2630 uint64_t c_mask = dup_const(MO_16, 0xffff >> c);
2631 TCGv_i64 s = tcg_temp_new_i64();
2632
2633 tcg_gen_shri_i64(d, a, c);
2634 tcg_gen_andi_i64(s, d, s_mask); /* isolate (shifted) sign bit */
2635 tcg_gen_andi_i64(d, d, c_mask); /* clear out bits above sign */
2636 tcg_gen_muli_i64(s, s, (2 << c) - 2); /* replicate isolated signs */
2637 tcg_gen_or_i64(d, d, s); /* include sign extension */
2638 tcg_temp_free_i64(s);
2639}
2640
2641void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
2642 int64_t shift, uint32_t oprsz, uint32_t maxsz)
2643{
53229a77 2644 static const TCGOpcode vecop_list[] = { INDEX_op_sari_vec, 0 };
d0ec9796
RH		 2645 static const GVecGen2i g[4] = {
2646 { .fni8 = tcg_gen_vec_sar8i_i64,
2647 .fniv = tcg_gen_sari_vec,
2648 .fno = gen_helper_gvec_sar8i,
53229a77 2649 .opt_opc = vecop_list,
d0ec9796
RH		 2650 .vece = MO_8 },
2651 { .fni8 = tcg_gen_vec_sar16i_i64,
2652 .fniv = tcg_gen_sari_vec,
2653 .fno = gen_helper_gvec_sar16i,
53229a77 2654 .opt_opc = vecop_list,
d0ec9796
RH		 2655 .vece = MO_16 },
2656 { .fni4 = tcg_gen_sari_i32,
2657 .fniv = tcg_gen_sari_vec,
2658 .fno = gen_helper_gvec_sar32i,
53229a77 2659 .opt_opc = vecop_list,
d0ec9796
RH		 2660 .vece = MO_32 },
2661 { .fni8 = tcg_gen_sari_i64,
2662 .fniv = tcg_gen_sari_vec,
2663 .fno = gen_helper_gvec_sar64i,
53229a77 2664 .opt_opc = vecop_list,
d0ec9796
RH		 2665 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2666 .vece = MO_64 },
2667 };
2668
2669 tcg_debug_assert(vece <= MO_64);
2670 tcg_debug_assert(shift >= 0 && shift < (8 << vece));
2671 if (shift == 0) {
2672 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
2673 } else {
2674 tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]);
2675 }
2676}
212be173 2677
b4578cd9
RH		 2678/*
2679 * Specialized generation vector shifts by a non-constant scalar.
2680 */
2681
2682typedef struct {
2683 void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32);
2684 void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64);
2685 void (*fniv_s)(unsigned, TCGv_vec, TCGv_vec, TCGv_i32);
2686 void (*fniv_v)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
2687 gen_helper_gvec_2 *fno[4];
2688 TCGOpcode s_list[2];
2689 TCGOpcode v_list[2];
2690} GVecGen2sh;
2691
2692static void expand_2sh_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
2693 uint32_t oprsz, uint32_t tysz, TCGType type,
2694 TCGv_i32 shift,
2695 void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_i32))
2696{
2697 TCGv_vec t0 = tcg_temp_new_vec(type);
2698 uint32_t i;
2699
2700 for (i = 0; i < oprsz; i += tysz) {
2701 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
2702 fni(vece, t0, t0, shift);
2703 tcg_gen_st_vec(t0, cpu_env, dofs + i);
2704 }
2705 tcg_temp_free_vec(t0);
2706}
2707
2708static void
2709do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,
2710 uint32_t oprsz, uint32_t maxsz, const GVecGen2sh *g)
2711{
2712 TCGType type;
2713 uint32_t some;
2714
2715 check_size_align(oprsz, maxsz, dofs | aofs);
2716 check_overlap_2(dofs, aofs, maxsz);
2717
2718 /* If the backend has a scalar expansion, great. */
2719 type = choose_vector_type(g->s_list, vece, oprsz, vece == MO_64);
2720 if (type) {
2721 const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
2722 switch (type) {
2723 case TCG_TYPE_V256:
2724 some = QEMU_ALIGN_DOWN(oprsz, 32);
2725 expand_2sh_vec(vece, dofs, aofs, some, 32,
2726 TCG_TYPE_V256, shift, g->fniv_s);
2727 if (some == oprsz) {
2728 break;
2729 }
2730 dofs += some;
2731 aofs += some;
2732 oprsz -= some;
2733 maxsz -= some;
2734 /* fallthru */
2735 case TCG_TYPE_V128:
2736 expand_2sh_vec(vece, dofs, aofs, oprsz, 16,
2737 TCG_TYPE_V128, shift, g->fniv_s);
2738 break;
2739 case TCG_TYPE_V64:
2740 expand_2sh_vec(vece, dofs, aofs, oprsz, 8,
2741 TCG_TYPE_V64, shift, g->fniv_s);
2742 break;
2743 default:
2744 g_assert_not_reached();
2745 }
2746 tcg_swap_vecop_list(hold_list);
2747 goto clear_tail;
2748 }
2749
2750 /* If the backend supports variable vector shifts, also cool. */
2751 type = choose_vector_type(g->v_list, vece, oprsz, vece == MO_64);
2752 if (type) {
2753 const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
2754 TCGv_vec v_shift = tcg_temp_new_vec(type);
2755
2756 if (vece == MO_64) {
2757 TCGv_i64 sh64 = tcg_temp_new_i64();
2758 tcg_gen_extu_i32_i64(sh64, shift);
2759 tcg_gen_dup_i64_vec(MO_64, v_shift, sh64);
2760 tcg_temp_free_i64(sh64);
2761 } else {
2762 tcg_gen_dup_i32_vec(vece, v_shift, shift);
2763 }
2764
2765 switch (type) {
2766 case TCG_TYPE_V256:
2767 some = QEMU_ALIGN_DOWN(oprsz, 32);
2768 expand_2s_vec(vece, dofs, aofs, some, 32, TCG_TYPE_V256,
2769 v_shift, false, g->fniv_v);
2770 if (some == oprsz) {
2771 break;
2772 }
2773 dofs += some;
2774 aofs += some;
2775 oprsz -= some;
2776 maxsz -= some;
2777 /* fallthru */
2778 case TCG_TYPE_V128:
2779 expand_2s_vec(vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
2780 v_shift, false, g->fniv_v);
2781 break;
2782 case TCG_TYPE_V64:
2783 expand_2s_vec(vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
2784 v_shift, false, g->fniv_v);
2785 break;
2786 default:
2787 g_assert_not_reached();
2788 }
2789 tcg_temp_free_vec(v_shift);
2790 tcg_swap_vecop_list(hold_list);
2791 goto clear_tail;
2792 }
2793
2794 /* Otherwise fall back to integral... */
2795 if (vece == MO_32 && check_size_impl(oprsz, 4)) {
2796 expand_2s_i32(dofs, aofs, oprsz, shift, false, g->fni4);
2797 } else if (vece == MO_64 && check_size_impl(oprsz, 8)) {
2798 TCGv_i64 sh64 = tcg_temp_new_i64();
2799 tcg_gen_extu_i32_i64(sh64, shift);
2800 expand_2s_i64(dofs, aofs, oprsz, sh64, false, g->fni8);
2801 tcg_temp_free_i64(sh64);
2802 } else {
2803 TCGv_ptr a0 = tcg_temp_new_ptr();
2804 TCGv_ptr a1 = tcg_temp_new_ptr();
2805 TCGv_i32 desc = tcg_temp_new_i32();
2806
2807 tcg_gen_shli_i32(desc, shift, SIMD_DATA_SHIFT);
2808 tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0));
2809 tcg_gen_addi_ptr(a0, cpu_env, dofs);
2810 tcg_gen_addi_ptr(a1, cpu_env, aofs);
2811
2812 g->fno[vece](a0, a1, desc);
2813
2814 tcg_temp_free_ptr(a0);
2815 tcg_temp_free_ptr(a1);
2816 tcg_temp_free_i32(desc);
2817 return;
2818 }
2819
2820 clear_tail:
2821 if (oprsz < maxsz) {
2822 expand_clr(dofs + oprsz, maxsz - oprsz);
2823 }
2824}
2825
2826void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs,
2827 TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
2828{
2829 static const GVecGen2sh g = {
2830 .fni4 = tcg_gen_shl_i32,
2831 .fni8 = tcg_gen_shl_i64,
2832 .fniv_s = tcg_gen_shls_vec,
2833 .fniv_v = tcg_gen_shlv_vec,
2834 .fno = {
2835 gen_helper_gvec_shl8i,
2836 gen_helper_gvec_shl16i,
2837 gen_helper_gvec_shl32i,
2838 gen_helper_gvec_shl64i,
2839 },
2840 .s_list = { INDEX_op_shls_vec, 0 },
2841 .v_list = { INDEX_op_shlv_vec, 0 },
2842 };
2843
2844 tcg_debug_assert(vece <= MO_64);
2845 do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);
2846}
2847
2848void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs,
2849 TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
2850{
2851 static const GVecGen2sh g = {
2852 .fni4 = tcg_gen_shr_i32,
2853 .fni8 = tcg_gen_shr_i64,
2854 .fniv_s = tcg_gen_shrs_vec,
2855 .fniv_v = tcg_gen_shrv_vec,
2856 .fno = {
2857 gen_helper_gvec_shr8i,
2858 gen_helper_gvec_shr16i,
2859 gen_helper_gvec_shr32i,
2860 gen_helper_gvec_shr64i,
2861 },
2862 .s_list = { INDEX_op_shrs_vec, 0 },
2863 .v_list = { INDEX_op_shrv_vec, 0 },
2864 };
2865
2866 tcg_debug_assert(vece <= MO_64);
2867 do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);
2868}
2869
2870void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs,
2871 TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
2872{
2873 static const GVecGen2sh g = {
2874 .fni4 = tcg_gen_sar_i32,
2875 .fni8 = tcg_gen_sar_i64,
2876 .fniv_s = tcg_gen_sars_vec,
2877 .fniv_v = tcg_gen_sarv_vec,
2878 .fno = {
2879 gen_helper_gvec_sar8i,
2880 gen_helper_gvec_sar16i,
2881 gen_helper_gvec_sar32i,
2882 gen_helper_gvec_sar64i,
2883 },
2884 .s_list = { INDEX_op_sars_vec, 0 },
2885 .v_list = { INDEX_op_sarv_vec, 0 },
2886 };
2887
2888 tcg_debug_assert(vece <= MO_64);
2889 do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);
2890}
2891
5ee5c14c
RH		 2892/*
2893 * Expand D = A << (B % element bits)
2894 *
2895 * Unlike scalar shifts, where it is easy for the target front end
2896 * to include the modulo as part of the expansion. If the target
2897 * naturally includes the modulo as part of the operation, great!
2898 * If the target has some other behaviour from out-of-range shifts,
2899 * then it could not use this function anyway, and would need to
2900 * do it's own expansion with custom functions.
2901 */
2902static void tcg_gen_shlv_mod_vec(unsigned vece, TCGv_vec d,
2903 TCGv_vec a, TCGv_vec b)
2904{
2905 TCGv_vec t = tcg_temp_new_vec_matching(d);
2906
2907 tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
2908 tcg_gen_and_vec(vece, t, t, b);
2909 tcg_gen_shlv_vec(vece, d, a, t);
2910 tcg_temp_free_vec(t);
2911}
2912
2913static void tcg_gen_shl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
2914{
2915 TCGv_i32 t = tcg_temp_new_i32();
2916
2917 tcg_gen_andi_i32(t, b, 31);
2918 tcg_gen_shl_i32(d, a, t);
2919 tcg_temp_free_i32(t);
2920}
2921
2922static void tcg_gen_shl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
2923{
2924 TCGv_i64 t = tcg_temp_new_i64();
2925
2926 tcg_gen_andi_i64(t, b, 63);
2927 tcg_gen_shl_i64(d, a, t);
2928 tcg_temp_free_i64(t);
2929}
2930
2931void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,
2932 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2933{
2934 static const TCGOpcode vecop_list[] = { INDEX_op_shlv_vec, 0 };
2935 static const GVecGen3 g[4] = {
2936 { .fniv = tcg_gen_shlv_mod_vec,
2937 .fno = gen_helper_gvec_shl8v,
2938 .opt_opc = vecop_list,
2939 .vece = MO_8 },
2940 { .fniv = tcg_gen_shlv_mod_vec,
2941 .fno = gen_helper_gvec_shl16v,
2942 .opt_opc = vecop_list,
2943 .vece = MO_16 },
2944 { .fni4 = tcg_gen_shl_mod_i32,
2945 .fniv = tcg_gen_shlv_mod_vec,
2946 .fno = gen_helper_gvec_shl32v,
2947 .opt_opc = vecop_list,
2948 .vece = MO_32 },
2949 { .fni8 = tcg_gen_shl_mod_i64,
2950 .fniv = tcg_gen_shlv_mod_vec,
2951 .fno = gen_helper_gvec_shl64v,
2952 .opt_opc = vecop_list,
2953 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2954 .vece = MO_64 },
2955 };
2956
2957 tcg_debug_assert(vece <= MO_64);
2958 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
2959}
2960
2961/*
2962 * Similarly for logical right shifts.
2963 */
2964
2965static void tcg_gen_shrv_mod_vec(unsigned vece, TCGv_vec d,
2966 TCGv_vec a, TCGv_vec b)
2967{
2968 TCGv_vec t = tcg_temp_new_vec_matching(d);
2969
2970 tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
2971 tcg_gen_and_vec(vece, t, t, b);
2972 tcg_gen_shrv_vec(vece, d, a, t);
2973 tcg_temp_free_vec(t);
2974}
2975
2976static void tcg_gen_shr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
2977{
2978 TCGv_i32 t = tcg_temp_new_i32();
2979
2980 tcg_gen_andi_i32(t, b, 31);
2981 tcg_gen_shr_i32(d, a, t);
2982 tcg_temp_free_i32(t);
2983}
2984
2985static void tcg_gen_shr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
2986{
2987 TCGv_i64 t = tcg_temp_new_i64();
2988
2989 tcg_gen_andi_i64(t, b, 63);
2990 tcg_gen_shr_i64(d, a, t);
2991 tcg_temp_free_i64(t);
2992}
2993
2994void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,
2995 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2996{
2997 static const TCGOpcode vecop_list[] = { INDEX_op_shrv_vec, 0 };
2998 static const GVecGen3 g[4] = {
2999 { .fniv = tcg_gen_shrv_mod_vec,
3000 .fno = gen_helper_gvec_shr8v,
3001 .opt_opc = vecop_list,
3002 .vece = MO_8 },
3003 { .fniv = tcg_gen_shrv_mod_vec,
3004 .fno = gen_helper_gvec_shr16v,
3005 .opt_opc = vecop_list,
3006 .vece = MO_16 },
3007 { .fni4 = tcg_gen_shr_mod_i32,
3008 .fniv = tcg_gen_shrv_mod_vec,
3009 .fno = gen_helper_gvec_shr32v,
3010 .opt_opc = vecop_list,
3011 .vece = MO_32 },
3012 { .fni8 = tcg_gen_shr_mod_i64,
3013 .fniv = tcg_gen_shrv_mod_vec,
3014 .fno = gen_helper_gvec_shr64v,
3015 .opt_opc = vecop_list,
3016 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
3017 .vece = MO_64 },
3018 };
3019
3020 tcg_debug_assert(vece <= MO_64);
3021 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
3022}
3023
3024/*
3025 * Similarly for arithmetic right shifts.
3026 */
3027
3028static void tcg_gen_sarv_mod_vec(unsigned vece, TCGv_vec d,
3029 TCGv_vec a, TCGv_vec b)
3030{
3031 TCGv_vec t = tcg_temp_new_vec_matching(d);
3032
3033 tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
3034 tcg_gen_and_vec(vece, t, t, b);
3035 tcg_gen_sarv_vec(vece, d, a, t);
3036 tcg_temp_free_vec(t);
3037}
3038
3039static void tcg_gen_sar_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
3040{
3041 TCGv_i32 t = tcg_temp_new_i32();
3042
3043 tcg_gen_andi_i32(t, b, 31);
3044 tcg_gen_sar_i32(d, a, t);
3045 tcg_temp_free_i32(t);
3046}
3047
3048static void tcg_gen_sar_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
3049{
3050 TCGv_i64 t = tcg_temp_new_i64();
3051
3052 tcg_gen_andi_i64(t, b, 63);
3053 tcg_gen_sar_i64(d, a, t);
3054 tcg_temp_free_i64(t);
3055}
3056
3057void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,
3058 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
3059{
3060 static const TCGOpcode vecop_list[] = { INDEX_op_sarv_vec, 0 };
3061 static const GVecGen3 g[4] = {
3062 { .fniv = tcg_gen_sarv_mod_vec,
3063 .fno = gen_helper_gvec_sar8v,
3064 .opt_opc = vecop_list,
3065 .vece = MO_8 },
3066 { .fniv = tcg_gen_sarv_mod_vec,
3067 .fno = gen_helper_gvec_sar16v,
3068 .opt_opc = vecop_list,
3069 .vece = MO_16 },
3070 { .fni4 = tcg_gen_sar_mod_i32,
3071 .fniv = tcg_gen_sarv_mod_vec,
3072 .fno = gen_helper_gvec_sar32v,
3073 .opt_opc = vecop_list,
3074 .vece = MO_32 },
3075 { .fni8 = tcg_gen_sar_mod_i64,
3076 .fniv = tcg_gen_sarv_mod_vec,
3077 .fno = gen_helper_gvec_sar64v,
3078 .opt_opc = vecop_list,
3079 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
3080 .vece = MO_64 },
3081 };
3082
3083 tcg_debug_assert(vece <= MO_64);
3084 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
3085}
3086
212be173
RH		 3087/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
3088static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
3089 uint32_t oprsz, TCGCond cond)
3090{
3091 TCGv_i32 t0 = tcg_temp_new_i32();
3092 TCGv_i32 t1 = tcg_temp_new_i32();
3093 uint32_t i;
3094
3095 for (i = 0; i < oprsz; i += 4) {
3096 tcg_gen_ld_i32(t0, cpu_env, aofs + i);
3097 tcg_gen_ld_i32(t1, cpu_env, bofs + i);
3098 tcg_gen_setcond_i32(cond, t0, t0, t1);
3099 tcg_gen_neg_i32(t0, t0);
3100 tcg_gen_st_i32(t0, cpu_env, dofs + i);
3101 }
3102 tcg_temp_free_i32(t1);
3103 tcg_temp_free_i32(t0);
3104}
3105
3106static void expand_cmp_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
3107 uint32_t oprsz, TCGCond cond)
3108{
3109 TCGv_i64 t0 = tcg_temp_new_i64();
3110 TCGv_i64 t1 = tcg_temp_new_i64();
3111 uint32_t i;
3112
3113 for (i = 0; i < oprsz; i += 8) {
3114 tcg_gen_ld_i64(t0, cpu_env, aofs + i);
3115 tcg_gen_ld_i64(t1, cpu_env, bofs + i);
3116 tcg_gen_setcond_i64(cond, t0, t0, t1);
3117 tcg_gen_neg_i64(t0, t0);
3118 tcg_gen_st_i64(t0, cpu_env, dofs + i);
3119 }
3120 tcg_temp_free_i64(t1);
3121 tcg_temp_free_i64(t0);
3122}
3123
3124static void expand_cmp_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
3125 uint32_t bofs, uint32_t oprsz, uint32_t tysz,
3126 TCGType type, TCGCond cond)
3127{
3128 TCGv_vec t0 = tcg_temp_new_vec(type);
3129 TCGv_vec t1 = tcg_temp_new_vec(type);
3130 uint32_t i;
3131
3132 for (i = 0; i < oprsz; i += tysz) {
3133 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
3134 tcg_gen_ld_vec(t1, cpu_env, bofs + i);
3135 tcg_gen_cmp_vec(cond, vece, t0, t0, t1);
3136 tcg_gen_st_vec(t0, cpu_env, dofs + i);
3137 }
3138 tcg_temp_free_vec(t1);
3139 tcg_temp_free_vec(t0);
3140}
3141
3142void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
3143 uint32_t aofs, uint32_t bofs,
3144 uint32_t oprsz, uint32_t maxsz)
3145{
53229a77 3146 static const TCGOpcode cmp_list[] = { INDEX_op_cmp_vec, 0 };
212be173
RH		 3147 static gen_helper_gvec_3 * const eq_fn[4] = {
3148 gen_helper_gvec_eq8, gen_helper_gvec_eq16,
3149 gen_helper_gvec_eq32, gen_helper_gvec_eq64
3150 };
3151 static gen_helper_gvec_3 * const ne_fn[4] = {
3152 gen_helper_gvec_ne8, gen_helper_gvec_ne16,
3153 gen_helper_gvec_ne32, gen_helper_gvec_ne64
3154 };
3155 static gen_helper_gvec_3 * const lt_fn[4] = {
3156 gen_helper_gvec_lt8, gen_helper_gvec_lt16,
3157 gen_helper_gvec_lt32, gen_helper_gvec_lt64
3158 };
3159 static gen_helper_gvec_3 * const le_fn[4] = {
3160 gen_helper_gvec_le8, gen_helper_gvec_le16,
3161 gen_helper_gvec_le32, gen_helper_gvec_le64
3162 };
3163 static gen_helper_gvec_3 * const ltu_fn[4] = {
3164 gen_helper_gvec_ltu8, gen_helper_gvec_ltu16,
3165 gen_helper_gvec_ltu32, gen_helper_gvec_ltu64
3166 };
3167 static gen_helper_gvec_3 * const leu_fn[4] = {
3168 gen_helper_gvec_leu8, gen_helper_gvec_leu16,
3169 gen_helper_gvec_leu32, gen_helper_gvec_leu64
3170 };
3171 static gen_helper_gvec_3 * const * const fns[16] = {
3172 [TCG_COND_EQ] = eq_fn,
3173 [TCG_COND_NE] = ne_fn,
3174 [TCG_COND_LT] = lt_fn,
3175 [TCG_COND_LE] = le_fn,
3176 [TCG_COND_LTU] = ltu_fn,
3177 [TCG_COND_LEU] = leu_fn,
3178 };
53229a77
RH		 3179
3180 const TCGOpcode *hold_list;
adb196cb
RH		 3181 TCGType type;
3182 uint32_t some;
212be173
RH		 3183
3184 check_size_align(oprsz, maxsz, dofs | aofs | bofs);
3185 check_overlap_3(dofs, aofs, bofs, maxsz);
3186
3187 if (cond == TCG_COND_NEVER || cond == TCG_COND_ALWAYS) {
3188 do_dup(MO_8, dofs, oprsz, maxsz,
3189 NULL, NULL, -(cond == TCG_COND_ALWAYS));
3190 return;
3191 }
3192
53229a77
RH		 3193 /*
3194 * Implement inline with a vector type, if possible.
adb196cb
RH		 3195 * Prefer integer when 64-bit host and 64-bit comparison.
3196 */
53229a77
RH		 3197 hold_list = tcg_swap_vecop_list(cmp_list);
3198 type = choose_vector_type(cmp_list, vece, oprsz,
adb196cb
RH		 3199 TCG_TARGET_REG_BITS == 64 && vece == MO_64);
3200 switch (type) {
3201 case TCG_TYPE_V256:
3202 /* Recall that ARM SVE allows vector sizes that are not a
3203 * power of 2, but always a multiple of 16. The intent is
3204 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
3205 */
3206 some = QEMU_ALIGN_DOWN(oprsz, 32);
212be173
RH		 3207 expand_cmp_vec(vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, cond);
3208 if (some == oprsz) {
adb196cb 3209 break;
212be173
RH		 3210 }
3211 dofs += some;
3212 aofs += some;
3213 bofs += some;
3214 oprsz -= some;
3215 maxsz -= some;
adb196cb
RH		 3216 /* fallthru */
3217 case TCG_TYPE_V128:
212be173 3218 expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, cond);
adb196cb
RH		 3219 break;
3220 case TCG_TYPE_V64:
212be173 3221 expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, cond);
adb196cb
RH		 3222 break;
3223
3224 case 0:
3225 if (vece == MO_64 && check_size_impl(oprsz, 8)) {
3226 expand_cmp_i64(dofs, aofs, bofs, oprsz, cond);
3227 } else if (vece == MO_32 && check_size_impl(oprsz, 4)) {
3228 expand_cmp_i32(dofs, aofs, bofs, oprsz, cond);
3229 } else {
3230 gen_helper_gvec_3 * const *fn = fns[cond];
3231
3232 if (fn == NULL) {
3233 uint32_t tmp;
3234 tmp = aofs, aofs = bofs, bofs = tmp;
3235 cond = tcg_swap_cond(cond);
3236 fn = fns[cond];
3237 assert(fn != NULL);
3238 }
3239 tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, fn[vece]);
53229a77 3240 oprsz = maxsz;
212be173 3241 }
adb196cb
RH		 3242 break;
3243
3244 default:
3245 g_assert_not_reached();
212be173 3246 }
53229a77 3247 tcg_swap_vecop_list(hold_list);
212be173 3248
212be173
RH		 3249 if (oprsz < maxsz) {
3250 expand_clr(dofs + oprsz, maxsz - oprsz);
3251 }
3252}
38dc1294
RH		 3253
3254static void tcg_gen_bitsel_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c)
3255{
3256 TCGv_i64 t = tcg_temp_new_i64();
3257
3258 tcg_gen_and_i64(t, b, a);
3259 tcg_gen_andc_i64(d, c, a);
3260 tcg_gen_or_i64(d, d, t);
3261 tcg_temp_free_i64(t);
3262}
3263
3264void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs,
3265 uint32_t bofs, uint32_t cofs,
3266 uint32_t oprsz, uint32_t maxsz)
3267{
3268 static const GVecGen4 g = {
3269 .fni8 = tcg_gen_bitsel_i64,
3270 .fniv = tcg_gen_bitsel_vec,
3271 .fno = gen_helper_gvec_bitsel,
3272 };
3273
3274 tcg_gen_gvec_4(dofs, aofs, bofs, cofs, oprsz, maxsz, &g);
3275}
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