[qemu.git] / hw / arm / pxa2xx_gpio.c

/*
 * Intel XScale PXA255/270 GPIO controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <[email protected]>
 *
 * This code is licensed under the GPL.
 */

#include "hw/hw.h"
#include "hw/sysbus.h"
#include "hw/arm/pxa.h"

#define PXA2XX_GPIO_BANKS	4

#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
#define PXA2XX_GPIO(obj) \
    OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)

typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
struct PXA2xxGPIOInfo {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    MemoryRegion iomem;
    qemu_irq irq0, irq1, irqX;
    int lines;
    int ncpu;
    ARMCPU *cpu;

    /* XXX: GNU C vectors are more suitable */
    uint32_t ilevel[PXA2XX_GPIO_BANKS];
    uint32_t olevel[PXA2XX_GPIO_BANKS];
    uint32_t dir[PXA2XX_GPIO_BANKS];
    uint32_t rising[PXA2XX_GPIO_BANKS];
    uint32_t falling[PXA2XX_GPIO_BANKS];
    uint32_t status[PXA2XX_GPIO_BANKS];
    uint32_t gafr[PXA2XX_GPIO_BANKS * 2];

    uint32_t prev_level[PXA2XX_GPIO_BANKS];
    qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
    qemu_irq read_notify;
};

static struct {
    enum {
        GPIO_NONE,
        GPLR,
        GPSR,
        GPCR,
        GPDR,
        GRER,
        GFER,
        GEDR,
        GAFR_L,
        GAFR_U,
    } reg;
    int bank;
} pxa2xx_gpio_regs[0x200] = {
    [0 ... 0x1ff] = { GPIO_NONE, 0 },
#define PXA2XX_REG(reg, a0, a1, a2, a3)	\
    [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },

    PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
    PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
    PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
    PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
    PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
    PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
    PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
    PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
    PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
};

static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
{
    if (s->status[0] & (1 << 0))
        qemu_irq_raise(s->irq0);
    else
        qemu_irq_lower(s->irq0);

    if (s->status[0] & (1 << 1))
        qemu_irq_raise(s->irq1);
    else
        qemu_irq_lower(s->irq1);

    if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
        qemu_irq_raise(s->irqX);
    else
        qemu_irq_lower(s->irqX);
}

/* Bitmap of pins used as standby and sleep wake-up sources.  */
static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
    0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
};

static void pxa2xx_gpio_set(void *opaque, int line, int level)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    CPUState *cpu = CPU(s->cpu);
    int bank;
    uint32_t mask;

    if (line >= s->lines) {
        printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
        return;
    }

    bank = line >> 5;
    mask = 1U << (line & 31);

    if (level) {
        s->status[bank] |= s->rising[bank] & mask &
                ~s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] |= mask;
    } else {
        s->status[bank] |= s->falling[bank] & mask &
                s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] &= ~mask;
    }

    if (s->status[bank] & mask)
        pxa2xx_gpio_irq_update(s);

    /* Wake-up GPIOs */
    if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
        cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
    }
}

static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
    uint32_t level, diff;
    int i, bit, line;
    for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
        level = s->olevel[i] & s->dir[i];

        for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
            bit = ffs(diff) - 1;
            line = bit + 32 * i;
            qemu_set_irq(s->handler[line], (level >> bit) & 1);
        }

        s->prev_level[i] = level;
    }
}

static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
                                 unsigned size)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    uint32_t ret;
    int bank;
    if (offset >= 0x200)
        return 0;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        return s->dir[bank];

    case GPSR:		/* GPIO Pin-Output Set registers */
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pxa2xx GPIO: read from write only register GPSR\n");
        return 0;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pxa2xx GPIO: read from write only register GPCR\n");
        return 0;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        return s->rising[bank];

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        return s->falling[bank];

    case GAFR_L:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2];

    case GAFR_U:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2 + 1];

    case GPLR:		/* GPIO Pin-Level registers */
        ret = (s->olevel[bank] & s->dir[bank]) |
                (s->ilevel[bank] & ~s->dir[bank]);
        qemu_irq_raise(s->read_notify);
        return ret;

    case GEDR:		/* GPIO Edge Detect Status registers */
        return s->status[bank];

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }

    return 0;
}

static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
                              uint64_t value, unsigned size)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    int bank;
    if (offset >= 0x200)
        return;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        s->dir[bank] = value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPSR:		/* GPIO Pin-Output Set registers */
        s->olevel[bank] |= value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        s->olevel[bank] &= ~value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        s->rising[bank] = value;
        break;

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        s->falling[bank] = value;
        break;

    case GAFR_L:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2] = value;
        break;

    case GAFR_U:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2 + 1] = value;
        break;

    case GEDR:		/* GPIO Edge Detect Status registers */
        s->status[bank] &= ~value;
        pxa2xx_gpio_irq_update(s);
        break;

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }
}

static const MemoryRegionOps pxa_gpio_ops = {
    .read = pxa2xx_gpio_read,
    .write = pxa2xx_gpio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

DeviceState *pxa2xx_gpio_init(hwaddr base,
                              ARMCPU *cpu, DeviceState *pic, int lines)
{
    CPUState *cs = CPU(cpu);
    DeviceState *dev;

    dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
    qdev_prop_set_int32(dev, "lines", lines);
    qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));

    return dev;
}

static int pxa2xx_gpio_initfn(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));

    qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
    qdev_init_gpio_out(dev, s->handler, s->lines);

    memory_region_init_io(&s->iomem, OBJECT(s), &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq0);
    sysbus_init_irq(sbd, &s->irq1);
    sysbus_init_irq(sbd, &s->irqX);

    return 0;
}

/*
 * Registers a callback to notify on GPLR reads.  This normally
 * shouldn't be needed but it is used for the hack on Spitz machines.
 */
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
{
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    s->read_notify = handler;
}

static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
    .name = "pxa2xx-gpio",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
        VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_END_OF_LIST(),
    },
};

static Property pxa2xx_gpio_properties[] = {
    DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
    DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pxa2xx_gpio_initfn;
    dc->desc = "PXA2xx GPIO controller";
    dc->props = pxa2xx_gpio_properties;
    dc->vmsd = &vmstate_pxa2xx_gpio_regs;
}

static const TypeInfo pxa2xx_gpio_info = {
    .name          = TYPE_PXA2XX_GPIO,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxGPIOInfo),
    .class_init    = pxa2xx_gpio_class_init,
};

static void pxa2xx_gpio_register_types(void)
{
    type_register_static(&pxa2xx_gpio_info);
}

type_init(pxa2xx_gpio_register_types)
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 GPIO controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <[email protected]>
	6	*
	7	* This code is licensed under the GPL.
	8	*/
	9
83c9f4ca PB	10	#include "hw/hw.h"
83c9f4ca PB	11	#include "hw/sysbus.h"
0d09e41a	12	#include "hw/arm/pxa.h"
c1713132 AZ	13
	14	#define PXA2XX_GPIO_BANKS 4
	15
922bb317 AF	16	#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
	17	#define PXA2XX_GPIO(obj) \
	18	OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)
	19
0bb53337	20	typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
bc24a225	21	struct PXA2xxGPIOInfo {
922bb317 AF	22	/< private >/
	23	SysBusDevice parent_obj;
	24	/< public >/
	25
55a8b801	26	MemoryRegion iomem;
0bb53337	27	qemu_irq irq0, irq1, irqX;
c1713132	28	int lines;
0bb53337	29	int ncpu;
95d42bb5	30	ARMCPU *cpu;
c1713132 AZ	31
	32	/* XXX: GNU C vectors are more suitable */
	33	uint32_t ilevel[PXA2XX_GPIO_BANKS];
	34	uint32_t olevel[PXA2XX_GPIO_BANKS];
	35	uint32_t dir[PXA2XX_GPIO_BANKS];
	36	uint32_t rising[PXA2XX_GPIO_BANKS];
	37	uint32_t falling[PXA2XX_GPIO_BANKS];
	38	uint32_t status[PXA2XX_GPIO_BANKS];
	39	uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
	40
	41	uint32_t prev_level[PXA2XX_GPIO_BANKS];
38641a52 AZ	42	qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
38641a52 AZ	43	qemu_irq read_notify;
c1713132 AZ	44	};
	45
	46	static struct {
	47	enum {
	48	GPIO_NONE,
	49	GPLR,
	50	GPSR,
	51	GPCR,
	52	GPDR,
	53	GRER,
	54	GFER,
	55	GEDR,
	56	GAFR_L,
	57	GAFR_U,
	58	} reg;
	59	int bank;
	60	} pxa2xx_gpio_regs[0x200] = {
	61	[0 ... 0x1ff] = { GPIO_NONE, 0 },
	62	#define PXA2XX_REG(reg, a0, a1, a2, a3) \
5fafdf24	63	[a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
c1713132 AZ	64
	65	PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
	66	PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
	67	PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
	68	PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
	69	PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
	70	PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
	71	PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
	72	PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
	73	PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
	74	};
	75
bc24a225	76	static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
c1713132 AZ	77	{
c1713132 AZ	78	if (s->status[0] & (1 << 0))
0bb53337	79	qemu_irq_raise(s->irq0);
c1713132	80	else
0bb53337	81	qemu_irq_lower(s->irq0);
c1713132 AZ	82
c1713132 AZ	83	if (s->status[0] & (1 << 1))
0bb53337	84	qemu_irq_raise(s->irq1);
c1713132	85	else
0bb53337	86	qemu_irq_lower(s->irq1);
c1713132 AZ	87
c1713132 AZ	88	if ((s->status[0] & ~3) \| s->status[1] \| s->status[2] \| s->status[3])
0bb53337	89	qemu_irq_raise(s->irqX);
c1713132	90	else
0bb53337	91	qemu_irq_lower(s->irqX);
c1713132 AZ	92	}
	93
	94	/* Bitmap of pins used as standby and sleep wake-up sources. */
38641a52	95	static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
c1713132 AZ	96	0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
	97	};
	98
38641a52	99	static void pxa2xx_gpio_set(void *opaque, int line, int level)
c1713132	100	{
bc24a225	101	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
259186a7	102	CPUState *cpu = CPU(s->cpu);
c1713132 AZ	103	int bank;
	104	uint32_t mask;
	105
	106	if (line >= s->lines) {
	107	printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
	108	return;
	109	}
	110
	111	bank = line >> 5;
43a32ed6	112	mask = 1U << (line & 31);
c1713132 AZ	113
	114	if (level) {
	115	s->status[bank] \|= s->rising[bank] & mask &
	116	~s->ilevel[bank] & ~s->dir[bank];
	117	s->ilevel[bank] \|= mask;
	118	} else {
	119	s->status[bank] \|= s->falling[bank] & mask &
	120	s->ilevel[bank] & ~s->dir[bank];
	121	s->ilevel[bank] &= ~mask;
	122	}
	123
	124	if (s->status[bank] & mask)
	125	pxa2xx_gpio_irq_update(s);
	126
	127	/* Wake-up GPIOs */
259186a7	128	if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
c3affe56	129	cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
95d42bb5	130	}
c1713132 AZ	131	}
c1713132 AZ	132
bc24a225	133	static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
c1713132 AZ	134	uint32_t level, diff;
	135	int i, bit, line;
	136	for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
	137	level = s->olevel[i] & s->dir[i];
	138
	139	for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
	140	bit = ffs(diff) - 1;
	141	line = bit + 32 * i;
38641a52	142	qemu_set_irq(s->handler[line], (level >> bit) & 1);
c1713132 AZ	143	}
	144
	145	s->prev_level[i] = level;
	146	}
	147	}
	148
a8170e5e	149	static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
55a8b801	150	unsigned size)
c1713132	151	{
bc24a225	152	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132 AZ	153	uint32_t ret;
c1713132 AZ	154	int bank;
c1713132 AZ	155	if (offset >= 0x200)
	156	return 0;
	157
	158	bank = pxa2xx_gpio_regs[offset].bank;
	159	switch (pxa2xx_gpio_regs[offset].reg) {
	160	case GPDR: /* GPIO Pin-Direction registers */
	161	return s->dir[bank];
	162
2b76bdc9	163	case GPSR: /* GPIO Pin-Output Set registers */
ab7a0f0b PM	164	qemu_log_mask(LOG_GUEST_ERROR,
	165	"pxa2xx GPIO: read from write only register GPSR\n");
	166	return 0;
2b76bdc9	167
e1dad5a6	168	case GPCR: /* GPIO Pin-Output Clear registers */
ab7a0f0b PM	169	qemu_log_mask(LOG_GUEST_ERROR,
	170	"pxa2xx GPIO: read from write only register GPCR\n");
	171	return 0;
e1dad5a6	172
c1713132 AZ	173	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	174	return s->rising[bank];
	175
	176	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	177	return s->falling[bank];
	178
	179	case GAFR_L: /* GPIO Alternate Function registers */
	180	return s->gafr[bank * 2];
	181
	182	case GAFR_U: /* GPIO Alternate Function registers */
	183	return s->gafr[bank * 2 + 1];
	184
	185	case GPLR: /* GPIO Pin-Level registers */
	186	ret = (s->olevel[bank] & s->dir[bank]) \|
	187	(s->ilevel[bank] & ~s->dir[bank]);
38641a52	188	qemu_irq_raise(s->read_notify);
c1713132 AZ	189	return ret;
	190
	191	case GEDR: /* GPIO Edge Detect Status registers */
	192	return s->status[bank];
	193
	194	default:
2ac71179	195	hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
c1713132 AZ	196	}
	197
	198	return 0;
	199	}
	200
a8170e5e	201	static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
55a8b801	202	uint64_t value, unsigned size)
c1713132	203	{
bc24a225	204	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132	205	int bank;
c1713132 AZ	206	if (offset >= 0x200)
	207	return;
	208
	209	bank = pxa2xx_gpio_regs[offset].bank;
	210	switch (pxa2xx_gpio_regs[offset].reg) {
	211	case GPDR: /* GPIO Pin-Direction registers */
	212	s->dir[bank] = value;
	213	pxa2xx_gpio_handler_update(s);
	214	break;
	215
	216	case GPSR: /* GPIO Pin-Output Set registers */
	217	s->olevel[bank] \|= value;
	218	pxa2xx_gpio_handler_update(s);
	219	break;
	220
	221	case GPCR: /* GPIO Pin-Output Clear registers */
	222	s->olevel[bank] &= ~value;
	223	pxa2xx_gpio_handler_update(s);
	224	break;
	225
	226	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	227	s->rising[bank] = value;
	228	break;
	229
	230	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	231	s->falling[bank] = value;
	232	break;
	233
	234	case GAFR_L: /* GPIO Alternate Function registers */
	235	s->gafr[bank * 2] = value;
	236	break;
	237
	238	case GAFR_U: /* GPIO Alternate Function registers */
	239	s->gafr[bank * 2 + 1] = value;
	240	break;
	241
	242	case GEDR: /* GPIO Edge Detect Status registers */
	243	s->status[bank] &= ~value;
	244	pxa2xx_gpio_irq_update(s);
	245	break;
	246
	247	default:
2ac71179	248	hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
c1713132 AZ	249	}
	250	}
	251
55a8b801 BC	252	static const MemoryRegionOps pxa_gpio_ops = {
	253	.read = pxa2xx_gpio_read,
	254	.write = pxa2xx_gpio_write,
	255	.endianness = DEVICE_NATIVE_ENDIAN,
c1713132 AZ	256	};
c1713132 AZ	257
a8170e5e	258	DeviceState *pxa2xx_gpio_init(hwaddr base,
55e5c285	259	ARMCPU cpu, DeviceState pic, int lines)
aa941b94	260	{
55e5c285	261	CPUState *cs = CPU(cpu);
0bb53337	262	DeviceState *dev;
aa941b94	263
922bb317	264	dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
0bb53337	265	qdev_prop_set_int32(dev, "lines", lines);
55e5c285	266	qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
0bb53337	267	qdev_init_nofail(dev);
aa941b94	268
1356b98d AF	269	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1356b98d AF	270	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
e1f8c729	271	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
1356b98d	272	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
e1f8c729	273	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
1356b98d	274	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
e1f8c729	275	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
aa941b94	276
0bb53337	277	return dev;
aa941b94 AZ	278	}
aa941b94 AZ	279
922bb317	280	static int pxa2xx_gpio_initfn(SysBusDevice *sbd)
c1713132	281	{
922bb317 AF	282	DeviceState *dev = DEVICE(sbd);
922bb317 AF	283	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
c1713132	284
38d8f5c8	285	s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
c1713132	286
922bb317 AF	287	qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
922bb317 AF	288	qdev_init_gpio_out(dev, s->handler, s->lines);
c1713132	289
64bde0f3	290	memory_region_init_io(&s->iomem, OBJECT(s), &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
922bb317 AF	291	sysbus_init_mmio(sbd, &s->iomem);
	292	sysbus_init_irq(sbd, &s->irq0);
	293	sysbus_init_irq(sbd, &s->irq1);
	294	sysbus_init_irq(sbd, &s->irqX);
c1713132	295
0bb53337	296	return 0;
c1713132 AZ	297	}
	298
	299	/*
	300	* Registers a callback to notify on GPLR reads. This normally
	301	* shouldn't be needed but it is used for the hack on Spitz machines.
	302	*/
0bb53337	303	void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
38641a52	304	{
922bb317 AF	305	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
922bb317 AF	306
c1713132	307	s->read_notify = handler;
c1713132	308	}
0bb53337 DES	309
	310	static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
	311	.name = "pxa2xx-gpio",
	312	.version_id = 1,
	313	.minimum_version_id = 1,
8f1e884b	314	.fields = (VMStateField[]) {
0bb53337 DES	315	VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	316	VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	317	VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	318	VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	319	VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	320	VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	321	VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
166fa999	322	VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
0bb53337 DES	323	VMSTATE_END_OF_LIST(),
	324	},
	325	};
	326
999e12bb AL	327	static Property pxa2xx_gpio_properties[] = {
	328	DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
	329	DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
	330	DEFINE_PROP_END_OF_LIST(),
	331	};
	332
	333	static void pxa2xx_gpio_class_init(ObjectClass klass, void data)
	334	{
39bffca2	335	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	336	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	337
	338	k->init = pxa2xx_gpio_initfn;
39bffca2 AL	339	dc->desc = "PXA2xx GPIO controller";
39bffca2 AL	340	dc->props = pxa2xx_gpio_properties;
166fa999	341	dc->vmsd = &vmstate_pxa2xx_gpio_regs;
999e12bb AL	342	}
999e12bb AL	343
8c43a6f0	344	static const TypeInfo pxa2xx_gpio_info = {
922bb317	345	.name = TYPE_PXA2XX_GPIO,
39bffca2 AL	346	.parent = TYPE_SYS_BUS_DEVICE,
	347	.instance_size = sizeof(PXA2xxGPIOInfo),
	348	.class_init = pxa2xx_gpio_class_init,
0bb53337 DES	349	};
0bb53337 DES	350
83f7d43a	351	static void pxa2xx_gpio_register_types(void)
0bb53337	352	{
39bffca2	353	type_register_static(&pxa2xx_gpio_info);
0bb53337	354	}
83f7d43a AF	355
83f7d43a AF	356	type_init(pxa2xx_gpio_register_types)