[qemu.git] / hw / arm / exynos4210.c

/*
 *  Samsung exynos4210 SoC emulation
 *
 *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
 *    Maksim Kozlov <[email protected]>
 *    Evgeny Voevodin <[email protected]>
 *    Igor Mitsyanko  <[email protected]>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/log.h"
#include "cpu.h"
#include "hw/boards.h"
#include "sysemu/sysemu.h"
#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "hw/loader.h"
#include "hw/arm/exynos4210.h"
#include "hw/usb/hcd-ehci.h"

#define EXYNOS4210_CHIPID_ADDR         0x10000000

/* PWM */
#define EXYNOS4210_PWM_BASE_ADDR       0x139D0000

/* RTC */
#define EXYNOS4210_RTC_BASE_ADDR       0x10070000

/* MCT */
#define EXYNOS4210_MCT_BASE_ADDR       0x10050000

/* I2C */
#define EXYNOS4210_I2C_SHIFT           0x00010000
#define EXYNOS4210_I2C_BASE_ADDR       0x13860000
/* Interrupt Group of External Interrupt Combiner for I2C */
#define EXYNOS4210_I2C_INTG            27
#define EXYNOS4210_HDMI_INTG           16

/* UART's definitions */
#define EXYNOS4210_UART0_BASE_ADDR     0x13800000
#define EXYNOS4210_UART1_BASE_ADDR     0x13810000
#define EXYNOS4210_UART2_BASE_ADDR     0x13820000
#define EXYNOS4210_UART3_BASE_ADDR     0x13830000
#define EXYNOS4210_UART0_FIFO_SIZE     256
#define EXYNOS4210_UART1_FIFO_SIZE     64
#define EXYNOS4210_UART2_FIFO_SIZE     16
#define EXYNOS4210_UART3_FIFO_SIZE     16
/* Interrupt Group of External Interrupt Combiner for UART */
#define EXYNOS4210_UART_INT_GRP        26

/* External GIC */
#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR    0x10480000
#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR   0x10490000

/* Combiner */
#define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
#define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000

/* PMU SFR base address */
#define EXYNOS4210_PMU_BASE_ADDR            0x10020000

/* Clock controller SFR base address */
#define EXYNOS4210_CLK_BASE_ADDR            0x10030000

/* Display controllers (FIMD) */
#define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000

/* EHCI */
#define EXYNOS4210_EHCI_BASE_ADDR           0x12580000

static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                    0x09, 0x00, 0x00, 0x00 };

static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
                                               unsigned size)
{
    assert(offset < sizeof(chipid_and_omr));
    return chipid_and_omr[offset];
}

static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
                                            uint64_t value, unsigned size)
{
    return;
}

static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
    .read = exynos4210_chipid_and_omr_read,
    .write = exynos4210_chipid_and_omr_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .impl = {
        .max_access_size = 1,
    }
};

void exynos4210_write_secondary(ARMCPU *cpu,
        const struct arm_boot_info *info)
{
    int n;
    uint32_t smpboot[] = {
        0xe59f3034, /* ldr r3, External gic_cpu_if */
        0xe59f2034, /* ldr r2, Internal gic_cpu_if */
        0xe59f0034, /* ldr r0, startaddr */
        0xe3a01001, /* mov r1, #1 */
        0xe5821000, /* str r1, [r2] */
        0xe5831000, /* str r1, [r3] */
        0xe3a010ff, /* mov r1, #0xff */
        0xe5821004, /* str r1, [r2, #4] */
        0xe5831004, /* str r1, [r3, #4] */
        0xf57ff04f, /* dsb */
        0xe320f003, /* wfi */
        0xe5901000, /* ldr     r1, [r0] */
        0xe1110001, /* tst     r1, r1 */
        0x0afffffb, /* beq     <wfi> */
        0xe12fff11, /* bx      r1 */
        EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
        0,          /* gic_cpu_if: base address of Internal GIC CPU interface */
        0           /* bootreg: Boot register address is held here */
    };
    smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
    smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
        smpboot[n] = tswap32(smpboot[n]);
    }
    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
                       info->smp_loader_start);
}

static uint64_t exynos4210_calc_affinity(int cpu)
{
    uint64_t mp_affinity;

    /* Exynos4210 has 0x9 as cluster ID */
    mp_affinity = (0x9 << ARM_AFF1_SHIFT) | cpu;

    return mp_affinity;
}

Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
        unsigned long ram_size)
{
    int i, n;
    Exynos4210State *s = g_new(Exynos4210State, 1);
    qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
    unsigned long mem_size;
    DeviceState *dev;
    SysBusDevice *busdev;
    ObjectClass *cpu_oc;

    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
    assert(cpu_oc);

    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
        Object *cpuobj = object_new(object_class_get_name(cpu_oc));

        /* By default A9 CPUs have EL3 enabled.  This board does not currently
         * support EL3 so the CPU EL3 property is disabled before realization.
         */
        if (object_property_find(cpuobj, "has_el3", NULL)) {
            object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
        }

        s->cpu[n] = ARM_CPU(cpuobj);
        object_property_set_int(cpuobj, exynos4210_calc_affinity(n),
                                "mp-affinity", &error_abort);
        object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
                                "reset-cbar", &error_abort);
        object_property_set_bool(cpuobj, true, "realized", &error_fatal);
    }

    /*** IRQs ***/

    s->irq_table = exynos4210_init_irq(&s->irqs);

    /* IRQ Gate */
    for (i = 0; i < EXYNOS4210_NCPUS; i++) {
        dev = qdev_create(NULL, "exynos4210.irq_gate");
        qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
        qdev_init_nofail(dev);
        /* Get IRQ Gate input in gate_irq */
        for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
            gate_irq[i][n] = qdev_get_gpio_in(dev, n);
        }
        busdev = SYS_BUS_DEVICE(dev);

        /* Connect IRQ Gate output to CPU's IRQ line */
        sysbus_connect_irq(busdev, 0,
                           qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
    }

    /* Private memory region and Internal GIC */
    dev = qdev_create(NULL, "a9mpcore_priv");
    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
        sysbus_connect_irq(busdev, n, gate_irq[n][0]);
    }
    for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
    }

    /* Cache controller */
    sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);

    /* External GIC */
    dev = qdev_create(NULL, "exynos4210.gic");
    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    /* Map CPU interface */
    sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
    /* Map Distributer interface */
    sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
        sysbus_connect_irq(busdev, n, gate_irq[n][1]);
    }
    for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
    }

    /* Internal Interrupt Combiner */
    dev = qdev_create(NULL, "exynos4210.combiner");
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
        sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
    }
    exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
    sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);

    /* External Interrupt Combiner */
    dev = qdev_create(NULL, "exynos4210.combiner");
    qdev_prop_set_uint32(dev, "external", 1);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
        sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
    }
    exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
    sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);

    /* Initialize board IRQs. */
    exynos4210_init_board_irqs(&s->irqs);

    /*** Memory ***/

    /* Chip-ID and OMR */
    memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops,
        NULL, "exynos4210.chipid", sizeof(chipid_and_omr));
    memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
                                &s->chipid_mem);

    /* Internal ROM */
    memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom",
                           EXYNOS4210_IROM_SIZE, &error_fatal);
    vmstate_register_ram_global(&s->irom_mem);
    memory_region_set_readonly(&s->irom_mem, true);
    memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
                                &s->irom_mem);
    /* mirror of iROM */
    memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias",
                             &s->irom_mem,
                             0,
                             EXYNOS4210_IROM_SIZE);
    memory_region_set_readonly(&s->irom_alias_mem, true);
    memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
                                &s->irom_alias_mem);

    /* Internal RAM */
    memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
                           EXYNOS4210_IRAM_SIZE, &error_fatal);
    vmstate_register_ram_global(&s->iram_mem);
    memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
                                &s->iram_mem);

    /* DRAM */
    mem_size = ram_size;
    if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
        memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
                mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal);
        vmstate_register_ram_global(&s->dram1_mem);
        memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
                &s->dram1_mem);
        mem_size = EXYNOS4210_DRAM_MAX_SIZE;
    }
    memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
                           &error_fatal);
    vmstate_register_ram_global(&s->dram0_mem);
    memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
            &s->dram0_mem);

   /* PMU.
    * The only reason of existence at the moment is that secondary CPU boot
    * loader uses PMU INFORM5 register as a holding pen.
    */
    sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);

    sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);

    /* PWM */
    sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
                          s->irq_table[exynos4210_get_irq(22, 0)],
                          s->irq_table[exynos4210_get_irq(22, 1)],
                          s->irq_table[exynos4210_get_irq(22, 2)],
                          s->irq_table[exynos4210_get_irq(22, 3)],
                          s->irq_table[exynos4210_get_irq(22, 4)],
                          NULL);
    /* RTC */
    sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
                          s->irq_table[exynos4210_get_irq(23, 0)],
                          s->irq_table[exynos4210_get_irq(23, 1)],
                          NULL);

    /* Multi Core Timer */
    dev = qdev_create(NULL, "exynos4210.mct");
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    for (n = 0; n < 4; n++) {
        /* Connect global timer interrupts to Combiner gpio_in */
        sysbus_connect_irq(busdev, n,
                s->irq_table[exynos4210_get_irq(1, 4 + n)]);
    }
    /* Connect local timer interrupts to Combiner gpio_in */
    sysbus_connect_irq(busdev, 4,
            s->irq_table[exynos4210_get_irq(51, 0)]);
    sysbus_connect_irq(busdev, 5,
            s->irq_table[exynos4210_get_irq(35, 3)]);
    sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);

    /*** I2C ***/
    for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
        uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
        qemu_irq i2c_irq;

        if (n < 8) {
            i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
        } else {
            i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
        }

        dev = qdev_create(NULL, "exynos4210.i2c");
        qdev_init_nofail(dev);
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_connect_irq(busdev, 0, i2c_irq);
        sysbus_mmio_map(busdev, 0, addr);
        s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
    }


    /*** UARTs ***/
    exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
                           EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);

    exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
                           EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);

    exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
                           EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);

    exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
                           EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);

    /*** Display controller (FIMD) ***/
    sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
            s->irq_table[exynos4210_get_irq(11, 0)],
            s->irq_table[exynos4210_get_irq(11, 1)],
            s->irq_table[exynos4210_get_irq(11, 2)],
            NULL);

    sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
            s->irq_table[exynos4210_get_irq(28, 3)]);

    return s;
}
Commit	Line	Data
0caa7113 EV	1	/*
	2	* Samsung exynos4210 SoC emulation
	3	*
	4	* Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
	5	* Maksim Kozlov <[email protected]>
	6	* Evgeny Voevodin <[email protected]>
	7	* Igor Mitsyanko <[email protected]>
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	17	* for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along
	20	* with this program; if not, see <http://www.gnu.org/licenses/>.
	21	*
	22	*/
	23
12b16722	24	#include "qemu/osdep.h"
da34e65c	25	#include "qapi/error.h"
4771d756	26	#include "qemu-common.h"
1e0228fd	27	#include "qemu/log.h"
4771d756	28	#include "cpu.h"
83c9f4ca	29	#include "hw/boards.h"
9c17d615	30	#include "sysemu/sysemu.h"
83c9f4ca	31	#include "hw/sysbus.h"
bd2be150	32	#include "hw/arm/arm.h"
83c9f4ca	33	#include "hw/loader.h"
0d09e41a	34	#include "hw/arm/exynos4210.h"
83c9f4ca	35	#include "hw/usb/hcd-ehci.h"
0caa7113 EV	36
	37	#define EXYNOS4210_CHIPID_ADDR 0x10000000
	38
62db8bf3 EV	39	/* PWM */
	40	#define EXYNOS4210_PWM_BASE_ADDR 0x139D0000
	41
7bdf43a7 OO	42	/* RTC */
	43	#define EXYNOS4210_RTC_BASE_ADDR 0x10070000
	44
12c775db EV	45	/* MCT */
	46	#define EXYNOS4210_MCT_BASE_ADDR 0x10050000
	47
ffbbe7d0 MI	48	/* I2C */
	49	#define EXYNOS4210_I2C_SHIFT 0x00010000
	50	#define EXYNOS4210_I2C_BASE_ADDR 0x13860000
	51	/* Interrupt Group of External Interrupt Combiner for I2C */
	52	#define EXYNOS4210_I2C_INTG 27
	53	#define EXYNOS4210_HDMI_INTG 16
	54
e5a4914e MK	55	/* UART's definitions */
	56	#define EXYNOS4210_UART0_BASE_ADDR 0x13800000
	57	#define EXYNOS4210_UART1_BASE_ADDR 0x13810000
	58	#define EXYNOS4210_UART2_BASE_ADDR 0x13820000
	59	#define EXYNOS4210_UART3_BASE_ADDR 0x13830000
	60	#define EXYNOS4210_UART0_FIFO_SIZE 256
	61	#define EXYNOS4210_UART1_FIFO_SIZE 64
	62	#define EXYNOS4210_UART2_FIFO_SIZE 16
	63	#define EXYNOS4210_UART3_FIFO_SIZE 16
	64	/* Interrupt Group of External Interrupt Combiner for UART */
	65	#define EXYNOS4210_UART_INT_GRP 26
	66
0caa7113 EV	67	/* External GIC */
	68	#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000
	69	#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000
	70
	71	/* Combiner */
	72	#define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000
	73	#define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000
	74
df91b48f MK	75	/* PMU SFR base address */
	76	#define EXYNOS4210_PMU_BASE_ADDR 0x10020000
	77
1e0228fd KK	78	/* Clock controller SFR base address */
	79	#define EXYNOS4210_CLK_BASE_ADDR 0x10030000
	80
30628cb1 MI	81	/* Display controllers (FIMD) */
	82	#define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000
	83
358d615b LW	84	/* EHCI */
	85	#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
	86
0caa7113 EV	87	static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
	88	0x09, 0x00, 0x00, 0x00 };
	89
11a5e482 IM	90	static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
	91	unsigned size)
	92	{
	93	assert(offset < sizeof(chipid_and_omr));
	94	return chipid_and_omr[offset];
	95	}
	96
	97	static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
	98	uint64_t value, unsigned size)
	99	{
	100	return;
	101	}
	102
	103	static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
	104	.read = exynos4210_chipid_and_omr_read,
	105	.write = exynos4210_chipid_and_omr_write,
	106	.endianness = DEVICE_NATIVE_ENDIAN,
	107	.impl = {
	108	.max_access_size = 1,
	109	}
	110	};
	111
9543b0cd	112	void exynos4210_write_secondary(ARMCPU *cpu,
3f088e36 EV	113	const struct arm_boot_info *info)
	114	{
	115	int n;
	116	uint32_t smpboot[] = {
bf471f79 PM	117	0xe59f3034, /* ldr r3, External gic_cpu_if */
	118	0xe59f2034, /* ldr r2, Internal gic_cpu_if */
	119	0xe59f0034, /* ldr r0, startaddr */
3f088e36 EV	120	0xe3a01001, /* mov r1, #1 */
	121	0xe5821000, /* str r1, [r2] */
	122	0xe5831000, /* str r1, [r3] */
bf471f79 PM	123	0xe3a010ff, /* mov r1, #0xff */
	124	0xe5821004, /* str r1, [r2, #4] */
	125	0xe5831004, /* str r1, [r3, #4] */
	126	0xf57ff04f, /* dsb */
3f088e36 EV	127	0xe320f003, /* wfi */
	128	0xe5901000, /* ldr r1, [r0] */
	129	0xe1110001, /* tst r1, r1 */
	130	0x0afffffb, /* beq <wfi> */
	131	0xe12fff11, /* bx r1 */
	132	EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
	133	0, /* gic_cpu_if: base address of Internal GIC CPU interface */
	134	0 /* bootreg: Boot register address is held here */
	135	};
	136	smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
	137	smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
	138	for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
	139	smpboot[n] = tswap32(smpboot[n]);
	140	}
	141	rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
	142	info->smp_loader_start);
	143	}
	144
f3a6339a KK	145	static uint64_t exynos4210_calc_affinity(int cpu)
	146	{
	147	uint64_t mp_affinity;
	148
	149	/* Exynos4210 has 0x9 as cluster ID */
	150	mp_affinity = (0x9 << ARM_AFF1_SHIFT) \| cpu;
	151
	152	return mp_affinity;
	153	}
	154
0caa7113 EV	155	Exynos4210State exynos4210_init(MemoryRegion system_mem,
	156	unsigned long ram_size)
	157	{
61558e7a	158	int i, n;
0caa7113	159	Exynos4210State *s = g_new(Exynos4210State, 1);
61558e7a	160	qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
0caa7113 EV	161	unsigned long mem_size;
	162	DeviceState *dev;
	163	SysBusDevice *busdev;
4719ab91 PM	164	ObjectClass *cpu_oc;
	165
	166	cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
	167	assert(cpu_oc);
0caa7113 EV	168
0caa7113 EV	169	for (n = 0; n < EXYNOS4210_NCPUS; n++) {
4719ab91	170	Object *cpuobj = object_new(object_class_get_name(cpu_oc));
4719ab91	171
61e2f352 GB	172	/* By default A9 CPUs have EL3 enabled. This board does not currently
	173	* support EL3 so the CPU EL3 property is disabled before realization.
	174	*/
	175	if (object_property_find(cpuobj, "has_el3", NULL)) {
007b0657	176	object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
61e2f352 GB	177	}
61e2f352 GB	178
4719ab91	179	s->cpu[n] = ARM_CPU(cpuobj);
f3a6339a KK	180	object_property_set_int(cpuobj, exynos4210_calc_affinity(n),
f3a6339a KK	181	"mp-affinity", &error_abort);
4719ab91 PM	182	object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
4719ab91 PM	183	"reset-cbar", &error_abort);
007b0657	184	object_property_set_bool(cpuobj, true, "realized", &error_fatal);
0caa7113 EV	185	}
	186
	187	/* IRQs */
	188
	189	s->irq_table = exynos4210_init_irq(&s->irqs);
	190
	191	/* IRQ Gate */
61558e7a EV	192	for (i = 0; i < EXYNOS4210_NCPUS; i++) {
	193	dev = qdev_create(NULL, "exynos4210.irq_gate");
	194	qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
	195	qdev_init_nofail(dev);
	196	/* Get IRQ Gate input in gate_irq */
	197	for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
	198	gate_irq[i][n] = qdev_get_gpio_in(dev, n);
	199	}
1356b98d	200	busdev = SYS_BUS_DEVICE(dev);
61558e7a	201
ad666d91 PM	202	/* Connect IRQ Gate output to CPU's IRQ line */
	203	sysbus_connect_irq(busdev, 0,
	204	qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
0caa7113 EV	205	}
	206
	207	/* Private memory region and Internal GIC */
	208	dev = qdev_create(NULL, "a9mpcore_priv");
	209	qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
	210	qdev_init_nofail(dev);
1356b98d	211	busdev = SYS_BUS_DEVICE(dev);
0caa7113 EV	212	sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
0caa7113 EV	213	for (n = 0; n < EXYNOS4210_NCPUS; n++) {
61558e7a	214	sysbus_connect_irq(busdev, n, gate_irq[n][0]);
0caa7113 EV	215	}
	216	for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
	217	s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
	218	}
	219
	220	/* Cache controller */
	221	sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
	222
	223	/* External GIC */
	224	dev = qdev_create(NULL, "exynos4210.gic");
	225	qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
	226	qdev_init_nofail(dev);
1356b98d	227	busdev = SYS_BUS_DEVICE(dev);
0caa7113 EV	228	/* Map CPU interface */
	229	sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
	230	/* Map Distributer interface */
	231	sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
	232	for (n = 0; n < EXYNOS4210_NCPUS; n++) {
61558e7a	233	sysbus_connect_irq(busdev, n, gate_irq[n][1]);
0caa7113 EV	234	}
	235	for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
	236	s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
	237	}
	238
	239	/* Internal Interrupt Combiner */
	240	dev = qdev_create(NULL, "exynos4210.combiner");
	241	qdev_init_nofail(dev);
1356b98d	242	busdev = SYS_BUS_DEVICE(dev);
0caa7113 EV	243	for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
	244	sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
	245	}
	246	exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
	247	sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
	248
	249	/* External Interrupt Combiner */
	250	dev = qdev_create(NULL, "exynos4210.combiner");
	251	qdev_prop_set_uint32(dev, "external", 1);
	252	qdev_init_nofail(dev);
1356b98d	253	busdev = SYS_BUS_DEVICE(dev);
0caa7113 EV	254	for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
	255	sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
	256	}
	257	exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
	258	sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
	259
	260	/* Initialize board IRQs. */
	261	exynos4210_init_board_irqs(&s->irqs);
	262
	263	/* Memory */
	264
	265	/* Chip-ID and OMR */
2c9b15ca	266	memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops,
11a5e482	267	NULL, "exynos4210.chipid", sizeof(chipid_and_omr));
0caa7113 EV	268	memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
	269	&s->chipid_mem);
	270
	271	/* Internal ROM */
2c9b15ca	272	memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom",
f8ed85ac	273	EXYNOS4210_IROM_SIZE, &error_fatal);
6539ed21	274	vmstate_register_ram_global(&s->irom_mem);
0caa7113 EV	275	memory_region_set_readonly(&s->irom_mem, true);
	276	memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
	277	&s->irom_mem);
	278	/* mirror of iROM */
2c9b15ca	279	memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias",
0caa7113	280	&s->irom_mem,
7892df06	281	0,
0caa7113 EV	282	EXYNOS4210_IROM_SIZE);
	283	memory_region_set_readonly(&s->irom_alias_mem, true);
	284	memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
	285	&s->irom_alias_mem);
	286
	287	/* Internal RAM */
2c9b15ca	288	memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
f8ed85ac	289	EXYNOS4210_IRAM_SIZE, &error_fatal);
0caa7113 EV	290	vmstate_register_ram_global(&s->iram_mem);
	291	memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
	292	&s->iram_mem);
	293
	294	/* DRAM */
	295	mem_size = ram_size;
	296	if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
2c9b15ca	297	memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
f8ed85ac	298	mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal);
0caa7113 EV	299	vmstate_register_ram_global(&s->dram1_mem);
	300	memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
	301	&s->dram1_mem);
	302	mem_size = EXYNOS4210_DRAM_MAX_SIZE;
	303	}
49946538	304	memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
f8ed85ac	305	&error_fatal);
0caa7113 EV	306	vmstate_register_ram_global(&s->dram0_mem);
	307	memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
	308	&s->dram0_mem);
	309
df91b48f MK	310	/* PMU.
	311	* The only reason of existence at the moment is that secondary CPU boot
	312	* loader uses PMU INFORM5 register as a holding pen.
	313	*/
	314	sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
	315
1e0228fd KK	316	sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
1e0228fd KK	317
62db8bf3 EV	318	/* PWM */
	319	sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
	320	s->irq_table[exynos4210_get_irq(22, 0)],
	321	s->irq_table[exynos4210_get_irq(22, 1)],
	322	s->irq_table[exynos4210_get_irq(22, 2)],
	323	s->irq_table[exynos4210_get_irq(22, 3)],
	324	s->irq_table[exynos4210_get_irq(22, 4)],
	325	NULL);
7bdf43a7 OO	326	/* RTC */
	327	sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
	328	s->irq_table[exynos4210_get_irq(23, 0)],
	329	s->irq_table[exynos4210_get_irq(23, 1)],
	330	NULL);
62db8bf3	331
12c775db EV	332	/* Multi Core Timer */
	333	dev = qdev_create(NULL, "exynos4210.mct");
	334	qdev_init_nofail(dev);
1356b98d	335	busdev = SYS_BUS_DEVICE(dev);
12c775db EV	336	for (n = 0; n < 4; n++) {
	337	/* Connect global timer interrupts to Combiner gpio_in */
	338	sysbus_connect_irq(busdev, n,
	339	s->irq_table[exynos4210_get_irq(1, 4 + n)]);
	340	}
	341	/* Connect local timer interrupts to Combiner gpio_in */
	342	sysbus_connect_irq(busdev, 4,
	343	s->irq_table[exynos4210_get_irq(51, 0)]);
	344	sysbus_connect_irq(busdev, 5,
	345	s->irq_table[exynos4210_get_irq(35, 3)]);
	346	sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
	347
ffbbe7d0 MI	348	/* I2C */
	349	for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
	350	uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
	351	qemu_irq i2c_irq;
	352
	353	if (n < 8) {
	354	i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
	355	} else {
	356	i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
	357	}
	358
	359	dev = qdev_create(NULL, "exynos4210.i2c");
	360	qdev_init_nofail(dev);
1356b98d	361	busdev = SYS_BUS_DEVICE(dev);
ffbbe7d0 MI	362	sysbus_connect_irq(busdev, 0, i2c_irq);
ffbbe7d0 MI	363	sysbus_mmio_map(busdev, 0, addr);
a5c82852	364	s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
ffbbe7d0 MI	365	}
	366
	367
e5a4914e MK	368	/* UARTs */
	369	exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
	370	EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
	371	s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
	372
	373	exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
	374	EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
	375	s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
	376
	377	exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
	378	EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
	379	s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
	380
	381	exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
	382	EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
	383	s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
	384
30628cb1 MI	385	/* Display controller (FIMD) */
	386	sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
	387	s->irq_table[exynos4210_get_irq(11, 0)],
	388	s->irq_table[exynos4210_get_irq(11, 1)],
	389	s->irq_table[exynos4210_get_irq(11, 2)],
	390	NULL);
	391
358d615b LW	392	sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
	393	s->irq_table[exynos4210_get_irq(28, 3)]);
	394
0caa7113 EV	395	return s;
0caa7113 EV	396	}