[qemu.git] / hw / timer / exynos4210_rtc.c

/*
 * Samsung exynos4210 Real Time Clock
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *  Ogurtsov Oleg <[email protected]>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 */

/* Description:
 * Register RTCCON:
 *  CLKSEL Bit[1] not used
 *  CLKOUTEN Bit[9] not used
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "qemu-common.h"
#include "qemu/bcd.h"
#include "hw/ptimer.h"

#include "hw/hw.h"
#include "sysemu/sysemu.h"

#include "hw/arm/exynos4210.h"

#define DEBUG_RTC 0

#if DEBUG_RTC
#define DPRINTF(fmt, ...) \
        do { fprintf(stdout, "RTC: [%24s:%5d] " fmt, __func__, __LINE__, \
                ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) do {} while (0)
#endif

#define     EXYNOS4210_RTC_REG_MEM_SIZE     0x0100

#define     INTP            0x0030
#define     RTCCON          0x0040
#define     TICCNT          0x0044
#define     RTCALM          0x0050
#define     ALMSEC          0x0054
#define     ALMMIN          0x0058
#define     ALMHOUR         0x005C
#define     ALMDAY          0x0060
#define     ALMMON          0x0064
#define     ALMYEAR         0x0068
#define     BCDSEC          0x0070
#define     BCDMIN          0x0074
#define     BCDHOUR         0x0078
#define     BCDDAY          0x007C
#define     BCDDAYWEEK      0x0080
#define     BCDMON          0x0084
#define     BCDYEAR         0x0088
#define     CURTICNT        0x0090

#define     TICK_TIMER_ENABLE   0x0100
#define     TICNT_THRESHOLD     2


#define     RTC_ENABLE          0x0001

#define     INTP_TICK_ENABLE    0x0001
#define     INTP_ALM_ENABLE     0x0002

#define     ALARM_INT_ENABLE    0x0040

#define     RTC_BASE_FREQ       32768

#define TYPE_EXYNOS4210_RTC "exynos4210.rtc"
#define EXYNOS4210_RTC(obj) \
    OBJECT_CHECK(Exynos4210RTCState, (obj), TYPE_EXYNOS4210_RTC)

typedef struct Exynos4210RTCState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;

    /* registers */
    uint32_t    reg_intp;
    uint32_t    reg_rtccon;
    uint32_t    reg_ticcnt;
    uint32_t    reg_rtcalm;
    uint32_t    reg_almsec;
    uint32_t    reg_almmin;
    uint32_t    reg_almhour;
    uint32_t    reg_almday;
    uint32_t    reg_almmon;
    uint32_t    reg_almyear;
    uint32_t    reg_curticcnt;

    ptimer_state    *ptimer;        /* tick timer */
    ptimer_state    *ptimer_1Hz;    /* clock timer */
    uint32_t        freq;

    qemu_irq        tick_irq;   /* Time Tick Generator irq */
    qemu_irq        alm_irq;    /* alarm irq */

    struct tm   current_tm;     /* current time */
} Exynos4210RTCState;

#define TICCKSEL(value) ((value & (0x0F << 4)) >> 4)

/*** VMState ***/
static const VMStateDescription vmstate_exynos4210_rtc_state = {
    .name = "exynos4210.rtc",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(reg_intp, Exynos4210RTCState),
        VMSTATE_UINT32(reg_rtccon, Exynos4210RTCState),
        VMSTATE_UINT32(reg_ticcnt, Exynos4210RTCState),
        VMSTATE_UINT32(reg_rtcalm, Exynos4210RTCState),
        VMSTATE_UINT32(reg_almsec, Exynos4210RTCState),
        VMSTATE_UINT32(reg_almmin, Exynos4210RTCState),
        VMSTATE_UINT32(reg_almhour, Exynos4210RTCState),
        VMSTATE_UINT32(reg_almday, Exynos4210RTCState),
        VMSTATE_UINT32(reg_almmon, Exynos4210RTCState),
        VMSTATE_UINT32(reg_almyear, Exynos4210RTCState),
        VMSTATE_UINT32(reg_curticcnt, Exynos4210RTCState),
        VMSTATE_PTIMER(ptimer, Exynos4210RTCState),
        VMSTATE_PTIMER(ptimer_1Hz, Exynos4210RTCState),
        VMSTATE_UINT32(freq, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_sec, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_min, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_hour, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_wday, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_mday, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_mon, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_year, Exynos4210RTCState),
        VMSTATE_END_OF_LIST()
    }
};

#define BCD3DIGITS(x) \
    ((uint32_t)to_bcd((uint8_t)(x % 100)) + \
    ((uint32_t)to_bcd((uint8_t)((x % 1000) / 100)) << 8))

static void check_alarm_raise(Exynos4210RTCState *s)
{
    unsigned int alarm_raise = 0;
    struct tm stm = s->current_tm;

    if ((s->reg_rtcalm & 0x01) &&
        (to_bcd((uint8_t)stm.tm_sec) == (uint8_t)s->reg_almsec)) {
        alarm_raise = 1;
    }
    if ((s->reg_rtcalm & 0x02) &&
        (to_bcd((uint8_t)stm.tm_min) == (uint8_t)s->reg_almmin)) {
        alarm_raise = 1;
    }
    if ((s->reg_rtcalm & 0x04) &&
        (to_bcd((uint8_t)stm.tm_hour) == (uint8_t)s->reg_almhour)) {
        alarm_raise = 1;
    }
    if ((s->reg_rtcalm & 0x08) &&
        (to_bcd((uint8_t)stm.tm_mday) == (uint8_t)s->reg_almday)) {
        alarm_raise = 1;
    }
    if ((s->reg_rtcalm & 0x10) &&
         (to_bcd((uint8_t)stm.tm_mon) == (uint8_t)s->reg_almmon)) {
        alarm_raise = 1;
    }
    if ((s->reg_rtcalm & 0x20) &&
        (BCD3DIGITS(stm.tm_year) == s->reg_almyear)) {
        alarm_raise = 1;
    }

    if (alarm_raise) {
        DPRINTF("ALARM IRQ\n");
        /* set irq status */
        s->reg_intp |= INTP_ALM_ENABLE;
        qemu_irq_raise(s->alm_irq);
    }
}

/*
 * RTC update frequency
 * Parameters:
 *     reg_value - current RTCCON register or his new value
 */
static void exynos4210_rtc_update_freq(Exynos4210RTCState *s,
                                       uint32_t reg_value)
{
    uint32_t freq;

    freq = s->freq;
    /* set frequncy for time generator */
    s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value));

    if (freq != s->freq) {
        ptimer_set_freq(s->ptimer, s->freq);
        DPRINTF("freq=%dHz\n", s->freq);
    }
}

/* month is between 0 and 11. */
static int get_days_in_month(int month, int year)
{
    static const int days_tab[12] = {
        31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
    };
    int d;
    if ((unsigned)month >= 12) {
        return 31;
    }
    d = days_tab[month];
    if (month == 1) {
        if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) {
            d++;
        }
    }
    return d;
}

/* update 'tm' to the next second */
static void rtc_next_second(struct tm *tm)
{
    int days_in_month;

    tm->tm_sec++;
    if ((unsigned)tm->tm_sec >= 60) {
        tm->tm_sec = 0;
        tm->tm_min++;
        if ((unsigned)tm->tm_min >= 60) {
            tm->tm_min = 0;
            tm->tm_hour++;
            if ((unsigned)tm->tm_hour >= 24) {
                tm->tm_hour = 0;
                /* next day */
                tm->tm_wday++;
                if ((unsigned)tm->tm_wday >= 7) {
                    tm->tm_wday = 0;
                }
                days_in_month = get_days_in_month(tm->tm_mon,
                                                  tm->tm_year + 1900);
                tm->tm_mday++;
                if (tm->tm_mday < 1) {
                    tm->tm_mday = 1;
                } else if (tm->tm_mday > days_in_month) {
                    tm->tm_mday = 1;
                    tm->tm_mon++;
                    if (tm->tm_mon >= 12) {
                        tm->tm_mon = 0;
                        tm->tm_year++;
                    }
                }
            }
        }
    }
}

/*
 * tick handler
 */
static void exynos4210_rtc_tick(void *opaque)
{
    Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;

    DPRINTF("TICK IRQ\n");
    /* set irq status */
    s->reg_intp |= INTP_TICK_ENABLE;
    /* raise IRQ */
    qemu_irq_raise(s->tick_irq);

    /* restart timer */
    ptimer_set_count(s->ptimer, s->reg_ticcnt);
    ptimer_run(s->ptimer, 1);
}

/*
 * 1Hz clock handler
 */
static void exynos4210_rtc_1Hz_tick(void *opaque)
{
    Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;

    rtc_next_second(&s->current_tm);
    /* DPRINTF("1Hz tick\n"); */

    /* raise IRQ */
    if (s->reg_rtcalm & ALARM_INT_ENABLE) {
        check_alarm_raise(s);
    }

    ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
    ptimer_run(s->ptimer_1Hz, 1);
}

/*
 * RTC Read
 */
static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
        unsigned size)
{
    uint32_t value = 0;
    Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;

    switch (offset) {
    case INTP:
        value = s->reg_intp;
        break;
    case RTCCON:
        value = s->reg_rtccon;
        break;
    case TICCNT:
        value = s->reg_ticcnt;
        break;
    case RTCALM:
        value = s->reg_rtcalm;
        break;
    case ALMSEC:
        value = s->reg_almsec;
        break;
    case ALMMIN:
        value = s->reg_almmin;
        break;
    case ALMHOUR:
        value = s->reg_almhour;
        break;
    case ALMDAY:
        value = s->reg_almday;
        break;
    case ALMMON:
        value = s->reg_almmon;
        break;
    case ALMYEAR:
        value = s->reg_almyear;
        break;

    case BCDSEC:
        value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_sec);
        break;
    case BCDMIN:
        value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_min);
        break;
    case BCDHOUR:
        value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_hour);
        break;
    case BCDDAYWEEK:
        value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_wday);
        break;
    case BCDDAY:
        value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mday);
        break;
    case BCDMON:
        value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mon + 1);
        break;
    case BCDYEAR:
        value = BCD3DIGITS(s->current_tm.tm_year);
        break;

    case CURTICNT:
        s->reg_curticcnt = ptimer_get_count(s->ptimer);
        value = s->reg_curticcnt;
        break;

    default:
        fprintf(stderr,
                "[exynos4210.rtc: bad read offset " TARGET_FMT_plx "]\n",
                offset);
        break;
    }
    return value;
}

/*
 * RTC Write
 */
static void exynos4210_rtc_write(void *opaque, hwaddr offset,
        uint64_t value, unsigned size)
{
    Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;

    switch (offset) {
    case INTP:
        if (value & INTP_ALM_ENABLE) {
            qemu_irq_lower(s->alm_irq);
            s->reg_intp &= (~INTP_ALM_ENABLE);
        }
        if (value & INTP_TICK_ENABLE) {
            qemu_irq_lower(s->tick_irq);
            s->reg_intp &= (~INTP_TICK_ENABLE);
        }
        break;
    case RTCCON:
        if (value & RTC_ENABLE) {
            exynos4210_rtc_update_freq(s, value);
        }
        if ((value & RTC_ENABLE) > (s->reg_rtccon & RTC_ENABLE)) {
            /* clock timer */
            ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
            ptimer_run(s->ptimer_1Hz, 1);
            DPRINTF("run clock timer\n");
        }
        if ((value & RTC_ENABLE) < (s->reg_rtccon & RTC_ENABLE)) {
            /* tick timer */
            ptimer_stop(s->ptimer);
            /* clock timer */
            ptimer_stop(s->ptimer_1Hz);
            DPRINTF("stop all timers\n");
        }
        if (value & RTC_ENABLE) {
            if ((value & TICK_TIMER_ENABLE) >
                (s->reg_rtccon & TICK_TIMER_ENABLE) &&
                (s->reg_ticcnt)) {
                ptimer_set_count(s->ptimer, s->reg_ticcnt);
                ptimer_run(s->ptimer, 1);
                DPRINTF("run tick timer\n");
            }
            if ((value & TICK_TIMER_ENABLE) <
                (s->reg_rtccon & TICK_TIMER_ENABLE)) {
                ptimer_stop(s->ptimer);
            }
        }
        s->reg_rtccon = value;
        break;
    case TICCNT:
        if (value > TICNT_THRESHOLD) {
            s->reg_ticcnt = value;
        } else {
            fprintf(stderr,
                    "[exynos4210.rtc: bad TICNT value %u ]\n",
                    (uint32_t)value);
        }
        break;

    case RTCALM:
        s->reg_rtcalm = value;
        break;
    case ALMSEC:
        s->reg_almsec = (value & 0x7f);
        break;
    case ALMMIN:
        s->reg_almmin = (value & 0x7f);
        break;
    case ALMHOUR:
        s->reg_almhour = (value & 0x3f);
        break;
    case ALMDAY:
        s->reg_almday = (value & 0x3f);
        break;
    case ALMMON:
        s->reg_almmon = (value & 0x1f);
        break;
    case ALMYEAR:
        s->reg_almyear = (value & 0x0fff);
        break;

    case BCDSEC:
        if (s->reg_rtccon & RTC_ENABLE) {
            s->current_tm.tm_sec = (int)from_bcd((uint8_t)value);
        }
        break;
    case BCDMIN:
        if (s->reg_rtccon & RTC_ENABLE) {
            s->current_tm.tm_min = (int)from_bcd((uint8_t)value);
        }
        break;
    case BCDHOUR:
        if (s->reg_rtccon & RTC_ENABLE) {
            s->current_tm.tm_hour = (int)from_bcd((uint8_t)value);
        }
        break;
    case BCDDAYWEEK:
        if (s->reg_rtccon & RTC_ENABLE) {
            s->current_tm.tm_wday = (int)from_bcd((uint8_t)value);
        }
        break;
    case BCDDAY:
        if (s->reg_rtccon & RTC_ENABLE) {
            s->current_tm.tm_mday = (int)from_bcd((uint8_t)value);
        }
        break;
    case BCDMON:
        if (s->reg_rtccon & RTC_ENABLE) {
            s->current_tm.tm_mon = (int)from_bcd((uint8_t)value) - 1;
        }
        break;
    case BCDYEAR:
        if (s->reg_rtccon & RTC_ENABLE) {
            /* 3 digits */
            s->current_tm.tm_year = (int)from_bcd((uint8_t)value) +
                    (int)from_bcd((uint8_t)((value >> 8) & 0x0f)) * 100;
        }
        break;

    default:
        fprintf(stderr,
                "[exynos4210.rtc: bad write offset " TARGET_FMT_plx "]\n",
                offset);
        break;

    }
}

/*
 * Set default values to timer fields and registers
 */
static void exynos4210_rtc_reset(DeviceState *d)
{
    Exynos4210RTCState *s = EXYNOS4210_RTC(d);

    qemu_get_timedate(&s->current_tm, 0);

    DPRINTF("Get time from host: %d-%d-%d %2d:%02d:%02d\n",
            s->current_tm.tm_year, s->current_tm.tm_mon, s->current_tm.tm_mday,
            s->current_tm.tm_hour, s->current_tm.tm_min, s->current_tm.tm_sec);

    s->reg_intp = 0;
    s->reg_rtccon = 0;
    s->reg_ticcnt = 0;
    s->reg_rtcalm = 0;
    s->reg_almsec = 0;
    s->reg_almmin = 0;
    s->reg_almhour = 0;
    s->reg_almday = 0;
    s->reg_almmon = 0;
    s->reg_almyear = 0;

    s->reg_curticcnt = 0;

    exynos4210_rtc_update_freq(s, s->reg_rtccon);
    ptimer_stop(s->ptimer);
    ptimer_stop(s->ptimer_1Hz);
}

static const MemoryRegionOps exynos4210_rtc_ops = {
    .read = exynos4210_rtc_read,
    .write = exynos4210_rtc_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

/*
 * RTC timer initialization
 */
static void exynos4210_rtc_init(Object *obj)
{
    Exynos4210RTCState *s = EXYNOS4210_RTC(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
    QEMUBH *bh;

    bh = qemu_bh_new(exynos4210_rtc_tick, s);
    s->ptimer = ptimer_init(bh);
    ptimer_set_freq(s->ptimer, RTC_BASE_FREQ);
    exynos4210_rtc_update_freq(s, 0);

    bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s);
    s->ptimer_1Hz = ptimer_init(bh);
    ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ);

    sysbus_init_irq(dev, &s->alm_irq);
    sysbus_init_irq(dev, &s->tick_irq);

    memory_region_init_io(&s->iomem, obj, &exynos4210_rtc_ops, s,
                          "exynos4210-rtc", EXYNOS4210_RTC_REG_MEM_SIZE);
    sysbus_init_mmio(dev, &s->iomem);
}

static void exynos4210_rtc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = exynos4210_rtc_reset;
    dc->vmsd = &vmstate_exynos4210_rtc_state;
}

static const TypeInfo exynos4210_rtc_info = {
    .name          = TYPE_EXYNOS4210_RTC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(Exynos4210RTCState),
    .instance_init = exynos4210_rtc_init,
    .class_init    = exynos4210_rtc_class_init,
};

static void exynos4210_rtc_register_types(void)
{
    type_register_static(&exynos4210_rtc_info);
}

type_init(exynos4210_rtc_register_types)
Commit	Line	Data
7bdf43a7 OO	1	/*
	2	* Samsung exynos4210 Real Time Clock
	3	*
	4	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	5	* Ogurtsov Oleg <[email protected]>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along
	18	* with this program; if not, see <http://www.gnu.org/licenses/>.
	19	*
	20	*/
	21
	22	/* Description:
	23	* Register RTCCON:
	24	* CLKSEL Bit[1] not used
	25	* CLKOUTEN Bit[9] not used
	26	*/
	27
8ef94f0b	28	#include "qemu/osdep.h"
83c9f4ca	29	#include "hw/sysbus.h"
1de7afc9	30	#include "qemu/timer.h"
7bdf43a7	31	#include "qemu-common.h"
f348b6d1	32	#include "qemu/bcd.h"
83c9f4ca	33	#include "hw/ptimer.h"
7bdf43a7	34
83c9f4ca	35	#include "hw/hw.h"
9c17d615	36	#include "sysemu/sysemu.h"
7bdf43a7	37
0d09e41a	38	#include "hw/arm/exynos4210.h"
7bdf43a7 OO	39
	40	#define DEBUG_RTC 0
	41
	42	#if DEBUG_RTC
	43	#define DPRINTF(fmt, ...) \
	44	do { fprintf(stdout, "RTC: [%24s:%5d] " fmt, __func__, __LINE__, \
	45	## __VA_ARGS__); } while (0)
	46	#else
	47	#define DPRINTF(fmt, ...) do {} while (0)
	48	#endif
	49
	50	#define EXYNOS4210_RTC_REG_MEM_SIZE 0x0100
	51
	52	#define INTP 0x0030
	53	#define RTCCON 0x0040
	54	#define TICCNT 0x0044
	55	#define RTCALM 0x0050
	56	#define ALMSEC 0x0054
	57	#define ALMMIN 0x0058
	58	#define ALMHOUR 0x005C
	59	#define ALMDAY 0x0060
	60	#define ALMMON 0x0064
	61	#define ALMYEAR 0x0068
	62	#define BCDSEC 0x0070
	63	#define BCDMIN 0x0074
	64	#define BCDHOUR 0x0078
	65	#define BCDDAY 0x007C
	66	#define BCDDAYWEEK 0x0080
	67	#define BCDMON 0x0084
	68	#define BCDYEAR 0x0088
	69	#define CURTICNT 0x0090
	70
	71	#define TICK_TIMER_ENABLE 0x0100
4c293dc6	72	#define TICNT_THRESHOLD 2
7bdf43a7 OO	73
	74
	75	#define RTC_ENABLE 0x0001
	76
	77	#define INTP_TICK_ENABLE 0x0001
	78	#define INTP_ALM_ENABLE 0x0002
	79
	80	#define ALARM_INT_ENABLE 0x0040
	81
	82	#define RTC_BASE_FREQ 32768
	83
3ddacf27 AF	84	#define TYPE_EXYNOS4210_RTC "exynos4210.rtc"
	85	#define EXYNOS4210_RTC(obj) \
	86	OBJECT_CHECK(Exynos4210RTCState, (obj), TYPE_EXYNOS4210_RTC)
	87
7bdf43a7	88	typedef struct Exynos4210RTCState {
3ddacf27 AF	89	SysBusDevice parent_obj;
3ddacf27 AF	90
7bdf43a7 OO	91	MemoryRegion iomem;
	92
	93	/* registers */
	94	uint32_t reg_intp;
	95	uint32_t reg_rtccon;
	96	uint32_t reg_ticcnt;
	97	uint32_t reg_rtcalm;
	98	uint32_t reg_almsec;
	99	uint32_t reg_almmin;
	100	uint32_t reg_almhour;
	101	uint32_t reg_almday;
	102	uint32_t reg_almmon;
	103	uint32_t reg_almyear;
	104	uint32_t reg_curticcnt;
	105
	106	ptimer_state ptimer; / tick timer */
	107	ptimer_state ptimer_1Hz; / clock timer */
	108	uint32_t freq;
	109
	110	qemu_irq tick_irq; /* Time Tick Generator irq */
	111	qemu_irq alm_irq; /* alarm irq */
	112
	113	struct tm current_tm; /* current time */
	114	} Exynos4210RTCState;
	115
	116	#define TICCKSEL(value) ((value & (0x0F << 4)) >> 4)
	117
	118	/* VMState */
	119	static const VMStateDescription vmstate_exynos4210_rtc_state = {
	120	.name = "exynos4210.rtc",
	121	.version_id = 1,
	122	.minimum_version_id = 1,
7bdf43a7 OO	123	.fields = (VMStateField[]) {
	124	VMSTATE_UINT32(reg_intp, Exynos4210RTCState),
	125	VMSTATE_UINT32(reg_rtccon, Exynos4210RTCState),
	126	VMSTATE_UINT32(reg_ticcnt, Exynos4210RTCState),
	127	VMSTATE_UINT32(reg_rtcalm, Exynos4210RTCState),
	128	VMSTATE_UINT32(reg_almsec, Exynos4210RTCState),
	129	VMSTATE_UINT32(reg_almmin, Exynos4210RTCState),
	130	VMSTATE_UINT32(reg_almhour, Exynos4210RTCState),
	131	VMSTATE_UINT32(reg_almday, Exynos4210RTCState),
	132	VMSTATE_UINT32(reg_almmon, Exynos4210RTCState),
	133	VMSTATE_UINT32(reg_almyear, Exynos4210RTCState),
	134	VMSTATE_UINT32(reg_curticcnt, Exynos4210RTCState),
	135	VMSTATE_PTIMER(ptimer, Exynos4210RTCState),
	136	VMSTATE_PTIMER(ptimer_1Hz, Exynos4210RTCState),
	137	VMSTATE_UINT32(freq, Exynos4210RTCState),
	138	VMSTATE_INT32(current_tm.tm_sec, Exynos4210RTCState),
	139	VMSTATE_INT32(current_tm.tm_min, Exynos4210RTCState),
	140	VMSTATE_INT32(current_tm.tm_hour, Exynos4210RTCState),
	141	VMSTATE_INT32(current_tm.tm_wday, Exynos4210RTCState),
	142	VMSTATE_INT32(current_tm.tm_mday, Exynos4210RTCState),
	143	VMSTATE_INT32(current_tm.tm_mon, Exynos4210RTCState),
	144	VMSTATE_INT32(current_tm.tm_year, Exynos4210RTCState),
	145	VMSTATE_END_OF_LIST()
	146	}
	147	};
	148
	149	#define BCD3DIGITS(x) \
64de1ecf	150	((uint32_t)to_bcd((uint8_t)(x % 100)) + \
7bdf43a7 OO	151	((uint32_t)to_bcd((uint8_t)((x % 1000) / 100)) << 8))
	152
	153	static void check_alarm_raise(Exynos4210RTCState *s)
	154	{
	155	unsigned int alarm_raise = 0;
	156	struct tm stm = s->current_tm;
	157
	158	if ((s->reg_rtcalm & 0x01) &&
	159	(to_bcd((uint8_t)stm.tm_sec) == (uint8_t)s->reg_almsec)) {
	160	alarm_raise = 1;
	161	}
	162	if ((s->reg_rtcalm & 0x02) &&
	163	(to_bcd((uint8_t)stm.tm_min) == (uint8_t)s->reg_almmin)) {
	164	alarm_raise = 1;
	165	}
	166	if ((s->reg_rtcalm & 0x04) &&
	167	(to_bcd((uint8_t)stm.tm_hour) == (uint8_t)s->reg_almhour)) {
	168	alarm_raise = 1;
	169	}
	170	if ((s->reg_rtcalm & 0x08) &&
	171	(to_bcd((uint8_t)stm.tm_mday) == (uint8_t)s->reg_almday)) {
	172	alarm_raise = 1;
	173	}
	174	if ((s->reg_rtcalm & 0x10) &&
	175	(to_bcd((uint8_t)stm.tm_mon) == (uint8_t)s->reg_almmon)) {
	176	alarm_raise = 1;
	177	}
	178	if ((s->reg_rtcalm & 0x20) &&
	179	(BCD3DIGITS(stm.tm_year) == s->reg_almyear)) {
	180	alarm_raise = 1;
	181	}
	182
	183	if (alarm_raise) {
	184	DPRINTF("ALARM IRQ\n");
	185	/* set irq status */
	186	s->reg_intp \|= INTP_ALM_ENABLE;
	187	qemu_irq_raise(s->alm_irq);
	188	}
	189	}
	190
	191	/*
	192	* RTC update frequency
	193	* Parameters:
	194	* reg_value - current RTCCON register or his new value
	195	*/
	196	static void exynos4210_rtc_update_freq(Exynos4210RTCState *s,
	197	uint32_t reg_value)
	198	{
	199	uint32_t freq;
	200
	201	freq = s->freq;
	202	/* set frequncy for time generator */
	203	s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value));
	204
	205	if (freq != s->freq) {
	206	ptimer_set_freq(s->ptimer, s->freq);
	207	DPRINTF("freq=%dHz\n", s->freq);
	208	}
	209	}
	210
	211	/* month is between 0 and 11. */
	212	static int get_days_in_month(int month, int year)
	213	{
	214	static const int days_tab[12] = {
215	31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
216	};
217	int d;
218	if ((unsigned)month >= 12) {
219	return 31;
220	}
221	d = days_tab[month];
222	if (month == 1) {
223	if ((year % 4) == 0 && ((year % 100) != 0 \|\| (year % 400) == 0)) {
224	d++;
225	}
226	}
227	return d;
228	}
229
230	/* update 'tm' to the next second */
231	static void rtc_next_second(struct tm *tm)
232	{
233	int days_in_month;
234
235	tm->tm_sec++;
236	if ((unsigned)tm->tm_sec >= 60) {
237	tm->tm_sec = 0;
238	tm->tm_min++;
239	if ((unsigned)tm->tm_min >= 60) {
240	tm->tm_min = 0;
241	tm->tm_hour++;
242	if ((unsigned)tm->tm_hour >= 24) {
243	tm->tm_hour = 0;
244	/* next day */
245	tm->tm_wday++;
246	if ((unsigned)tm->tm_wday >= 7) {
247	tm->tm_wday = 0;
248	}
249	days_in_month = get_days_in_month(tm->tm_mon,
250	tm->tm_year + 1900);
251	tm->tm_mday++;
252	if (tm->tm_mday < 1) {
253	tm->tm_mday = 1;
254	} else if (tm->tm_mday > days_in_month) {
255	tm->tm_mday = 1;
256	tm->tm_mon++;
257	if (tm->tm_mon >= 12) {
258	tm->tm_mon = 0;
259	tm->tm_year++;
260	}
261	}
262	}
263	}
264	}
265	}
266
267	/*
268	* tick handler
269	*/
270	static void exynos4210_rtc_tick(void *opaque)
271	{
272	Exynos4210RTCState s = (Exynos4210RTCState )opaque;
273
274	DPRINTF("TICK IRQ\n");
275	/* set irq status */
276	s->reg_intp \|= INTP_TICK_ENABLE;
277	/* raise IRQ */
278	qemu_irq_raise(s->tick_irq);
279
280	/* restart timer */
281	ptimer_set_count(s->ptimer, s->reg_ticcnt);
282	ptimer_run(s->ptimer, 1);
283	}
284
285	/*
286	* 1Hz clock handler
287	*/
288	static void exynos4210_rtc_1Hz_tick(void *opaque)
289	{
290	Exynos4210RTCState s = (Exynos4210RTCState )opaque;
291
292	rtc_next_second(&s->current_tm);
293	/* DPRINTF("1Hz tick\n"); */
294
295	/* raise IRQ */
296	if (s->reg_rtcalm & ALARM_INT_ENABLE) {
297	check_alarm_raise(s);
298	}
299
300	ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
301	ptimer_run(s->ptimer_1Hz, 1);
302	}
303
304	/*
305	* RTC Read
306	*/
a8170e5e	307	static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
7bdf43a7 OO	308	unsigned size)
	309	{
	310	uint32_t value = 0;
	311	Exynos4210RTCState s = (Exynos4210RTCState )opaque;
	312
	313	switch (offset) {
	314	case INTP:
	315	value = s->reg_intp;
	316	break;
	317	case RTCCON:
	318	value = s->reg_rtccon;
	319	break;
	320	case TICCNT:
	321	value = s->reg_ticcnt;
	322	break;
	323	case RTCALM:
	324	value = s->reg_rtcalm;
	325	break;
	326	case ALMSEC:
	327	value = s->reg_almsec;
	328	break;
	329	case ALMMIN:
	330	value = s->reg_almmin;
	331	break;
	332	case ALMHOUR:
	333	value = s->reg_almhour;
	334	break;
	335	case ALMDAY:
	336	value = s->reg_almday;
	337	break;
	338	case ALMMON:
	339	value = s->reg_almmon;
	340	break;
	341	case ALMYEAR:
	342	value = s->reg_almyear;
	343	break;
	344
	345	case BCDSEC:
	346	value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_sec);
	347	break;
	348	case BCDMIN:
	349	value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_min);
	350	break;
	351	case BCDHOUR:
	352	value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_hour);
	353	break;
	354	case BCDDAYWEEK:
	355	value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_wday);
	356	break;
	357	case BCDDAY:
	358	value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mday);
	359	break;
	360	case BCDMON:
	361	value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mon + 1);
	362	break;
	363	case BCDYEAR:
	364	value = BCD3DIGITS(s->current_tm.tm_year);
	365	break;
	366
	367	case CURTICNT:
	368	s->reg_curticcnt = ptimer_get_count(s->ptimer);
	369	value = s->reg_curticcnt;
	370	break;
	371
372	default:
373	fprintf(stderr,
374	"[exynos4210.rtc: bad read offset " TARGET_FMT_plx "]\n",
375	offset);
376	break;
377	}
378	return value;
379	}
380
381	/*
382	* RTC Write
383	*/
a8170e5e	384	static void exynos4210_rtc_write(void *opaque, hwaddr offset,
7bdf43a7 OO	385	uint64_t value, unsigned size)
	386	{
	387	Exynos4210RTCState s = (Exynos4210RTCState )opaque;
	388
	389	switch (offset) {
	390	case INTP:
	391	if (value & INTP_ALM_ENABLE) {
	392	qemu_irq_lower(s->alm_irq);
	393	s->reg_intp &= (~INTP_ALM_ENABLE);
	394	}
	395	if (value & INTP_TICK_ENABLE) {
	396	qemu_irq_lower(s->tick_irq);
	397	s->reg_intp &= (~INTP_TICK_ENABLE);
	398	}
	399	break;
	400	case RTCCON:
	401	if (value & RTC_ENABLE) {
	402	exynos4210_rtc_update_freq(s, value);
	403	}
	404	if ((value & RTC_ENABLE) > (s->reg_rtccon & RTC_ENABLE)) {
	405	/* clock timer */
	406	ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
	407	ptimer_run(s->ptimer_1Hz, 1);
	408	DPRINTF("run clock timer\n");
	409	}
	410	if ((value & RTC_ENABLE) < (s->reg_rtccon & RTC_ENABLE)) {
	411	/* tick timer */
	412	ptimer_stop(s->ptimer);
	413	/* clock timer */
	414	ptimer_stop(s->ptimer_1Hz);
	415	DPRINTF("stop all timers\n");
	416	}
	417	if (value & RTC_ENABLE) {
	418	if ((value & TICK_TIMER_ENABLE) >
	419	(s->reg_rtccon & TICK_TIMER_ENABLE) &&
	420	(s->reg_ticcnt)) {
	421	ptimer_set_count(s->ptimer, s->reg_ticcnt);
	422	ptimer_run(s->ptimer, 1);
	423	DPRINTF("run tick timer\n");
	424	}
	425	if ((value & TICK_TIMER_ENABLE) <
	426	(s->reg_rtccon & TICK_TIMER_ENABLE)) {
	427	ptimer_stop(s->ptimer);
	428	}
	429	}
	430	s->reg_rtccon = value;
	431	break;
	432	case TICCNT:
4c293dc6	433	if (value > TICNT_THRESHOLD) {
7bdf43a7 OO	434	s->reg_ticcnt = value;
	435	} else {
	436	fprintf(stderr,
	437	"[exynos4210.rtc: bad TICNT value %u ]\n",
	438	(uint32_t)value);
	439	}
	440	break;
	441
	442	case RTCALM:
	443	s->reg_rtcalm = value;
	444	break;
	445	case ALMSEC:
	446	s->reg_almsec = (value & 0x7f);
	447	break;
	448	case ALMMIN:
	449	s->reg_almmin = (value & 0x7f);
	450	break;
	451	case ALMHOUR:
	452	s->reg_almhour = (value & 0x3f);
	453	break;
	454	case ALMDAY:
	455	s->reg_almday = (value & 0x3f);
	456	break;
	457	case ALMMON:
	458	s->reg_almmon = (value & 0x1f);
	459	break;
	460	case ALMYEAR:
	461	s->reg_almyear = (value & 0x0fff);
	462	break;
	463
	464	case BCDSEC:
	465	if (s->reg_rtccon & RTC_ENABLE) {
	466	s->current_tm.tm_sec = (int)from_bcd((uint8_t)value);
	467	}
	468	break;
	469	case BCDMIN:
	470	if (s->reg_rtccon & RTC_ENABLE) {
	471	s->current_tm.tm_min = (int)from_bcd((uint8_t)value);
	472	}
	473	break;
	474	case BCDHOUR:
	475	if (s->reg_rtccon & RTC_ENABLE) {
	476	s->current_tm.tm_hour = (int)from_bcd((uint8_t)value);
	477	}
	478	break;
	479	case BCDDAYWEEK:
	480	if (s->reg_rtccon & RTC_ENABLE) {
	481	s->current_tm.tm_wday = (int)from_bcd((uint8_t)value);
	482	}
	483	break;
	484	case BCDDAY:
	485	if (s->reg_rtccon & RTC_ENABLE) {
	486	s->current_tm.tm_mday = (int)from_bcd((uint8_t)value);
	487	}
	488	break;
	489	case BCDMON:
	490	if (s->reg_rtccon & RTC_ENABLE) {
	491	s->current_tm.tm_mon = (int)from_bcd((uint8_t)value) - 1;
	492	}
	493	break;
	494	case BCDYEAR:
	495	if (s->reg_rtccon & RTC_ENABLE) {
	496	/* 3 digits */
	497	s->current_tm.tm_year = (int)from_bcd((uint8_t)value) +
498	(int)from_bcd((uint8_t)((value >> 8) & 0x0f)) * 100;
499	}
500	break;
501
502	default:
503	fprintf(stderr,
504	"[exynos4210.rtc: bad write offset " TARGET_FMT_plx "]\n",
505	offset);
506	break;
507
508	}
509	}
510
511	/*
512	* Set default values to timer fields and registers
513	*/
514	static void exynos4210_rtc_reset(DeviceState *d)
515	{
3ddacf27	516	Exynos4210RTCState *s = EXYNOS4210_RTC(d);
7bdf43a7	517
4688870d	518	qemu_get_timedate(&s->current_tm, 0);
7bdf43a7 OO	519
	520	DPRINTF("Get time from host: %d-%d-%d %2d:%02d:%02d\n",
	521	s->current_tm.tm_year, s->current_tm.tm_mon, s->current_tm.tm_mday,
	522	s->current_tm.tm_hour, s->current_tm.tm_min, s->current_tm.tm_sec);
	523
	524	s->reg_intp = 0;
	525	s->reg_rtccon = 0;
	526	s->reg_ticcnt = 0;
	527	s->reg_rtcalm = 0;
	528	s->reg_almsec = 0;
	529	s->reg_almmin = 0;
	530	s->reg_almhour = 0;
	531	s->reg_almday = 0;
	532	s->reg_almmon = 0;
	533	s->reg_almyear = 0;
	534
	535	s->reg_curticcnt = 0;
	536
	537	exynos4210_rtc_update_freq(s, s->reg_rtccon);
	538	ptimer_stop(s->ptimer);
	539	ptimer_stop(s->ptimer_1Hz);
	540	}
	541
	542	static const MemoryRegionOps exynos4210_rtc_ops = {
	543	.read = exynos4210_rtc_read,
	544	.write = exynos4210_rtc_write,
	545	.endianness = DEVICE_NATIVE_ENDIAN,
	546	};
	547
	548	/*
	549	* RTC timer initialization
	550	*/
c9d64639	551	static void exynos4210_rtc_init(Object *obj)
7bdf43a7	552	{
c9d64639 XZ	553	Exynos4210RTCState *s = EXYNOS4210_RTC(obj);
c9d64639 XZ	554	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
7bdf43a7 OO	555	QEMUBH *bh;
	556
	557	bh = qemu_bh_new(exynos4210_rtc_tick, s);
	558	s->ptimer = ptimer_init(bh);
	559	ptimer_set_freq(s->ptimer, RTC_BASE_FREQ);
	560	exynos4210_rtc_update_freq(s, 0);
	561
	562	bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s);
	563	s->ptimer_1Hz = ptimer_init(bh);
	564	ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ);
	565
	566	sysbus_init_irq(dev, &s->alm_irq);
	567	sysbus_init_irq(dev, &s->tick_irq);
	568
c9d64639	569	memory_region_init_io(&s->iomem, obj, &exynos4210_rtc_ops, s,
853dca12	570	"exynos4210-rtc", EXYNOS4210_RTC_REG_MEM_SIZE);
7bdf43a7	571	sysbus_init_mmio(dev, &s->iomem);
7bdf43a7 OO	572	}
	573
	574	static void exynos4210_rtc_class_init(ObjectClass klass, void data)
	575	{
	576	DeviceClass *dc = DEVICE_CLASS(klass);
7bdf43a7	577
7bdf43a7 OO	578	dc->reset = exynos4210_rtc_reset;
	579	dc->vmsd = &vmstate_exynos4210_rtc_state;
	580	}
	581
	582	static const TypeInfo exynos4210_rtc_info = {
3ddacf27	583	.name = TYPE_EXYNOS4210_RTC,
7bdf43a7 OO	584	.parent = TYPE_SYS_BUS_DEVICE,
7bdf43a7 OO	585	.instance_size = sizeof(Exynos4210RTCState),
c9d64639	586	.instance_init = exynos4210_rtc_init,
7bdf43a7 OO	587	.class_init = exynos4210_rtc_class_init,
	588	};
	589
	590	static void exynos4210_rtc_register_types(void)
	591	{
	592	type_register_static(&exynos4210_rtc_info);
	593	}
	594
	595	type_init(exynos4210_rtc_register_types)