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Commit | Line | Data |
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87ecb68b PB |
1 | #include "hw.h" |
2 | #include "mips.h" | |
4de9b249 TS |
3 | #include "cpu.h" |
4 | ||
5 | /* Raise IRQ to CPU if necessary. It must be called every time the active | |
6 | IRQ may change */ | |
7 | void cpu_mips_update_irq(CPUState *env) | |
8 | { | |
24c7b0e3 TS |
9 | if ((env->CP0_Status & (1 << CP0St_IE)) && |
10 | !(env->CP0_Status & (1 << CP0St_EXL)) && | |
11 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
12 | !(env->hflags & MIPS_HFLAG_DM)) { | |
13 | if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && | |
14 | !(env->interrupt_request & CPU_INTERRUPT_HARD)) { | |
4de9b249 TS |
15 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
16 | } | |
24c7b0e3 | 17 | } else |
4de9b249 | 18 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
4de9b249 TS |
19 | } |
20 | ||
d537cf6c | 21 | static void cpu_mips_irq_request(void *opaque, int irq, int level) |
4de9b249 | 22 | { |
39d51eb8 | 23 | CPUState *env = (CPUState *)opaque; |
4de9b249 | 24 | |
39d51eb8 | 25 | if (irq < 0 || irq > 7) |
4de9b249 TS |
26 | return; |
27 | ||
4de9b249 | 28 | if (level) { |
39d51eb8 | 29 | env->CP0_Cause |= 1 << (irq + CP0Ca_IP); |
4de9b249 | 30 | } else { |
a4bc3afc | 31 | env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); |
4de9b249 TS |
32 | } |
33 | cpu_mips_update_irq(env); | |
34 | } | |
d537cf6c PB |
35 | |
36 | void cpu_mips_irq_init_cpu(CPUState *env) | |
37 | { | |
38 | qemu_irq *qi; | |
39 | int i; | |
40 | ||
41 | qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8); | |
42 | for (i = 0; i < 8; i++) { | |
43 | env->irq[i] = qi[i]; | |
44 | } | |
45 | } |