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[qemu.git] / hw / pxa2xx_lcd.c
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a171fe39
AZ		 1/*
2 * Intel XScale PXA255/270 LCDC emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <[email protected]>
6 *
7 * This code is licensed under the GPLv2.
8 */
9
10#include "vl.h"
e27f01ef 11#include "pixel_ops.h"
a171fe39
AZ		 12
13typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int, int);
14
15struct pxa2xx_lcdc_s {
16 target_phys_addr_t base;
17 qemu_irq irq;
18 int irqlevel;
19
20 int invalidated;
21 DisplayState *ds;
22 drawfn *line_fn[2];
23 int dest_width;
24 int xres, yres;
25 int pal_for;
26 int transp;
27 enum {
28 pxa_lcdc_2bpp = 1,
29 pxa_lcdc_4bpp = 2,
30 pxa_lcdc_8bpp = 3,
31 pxa_lcdc_16bpp = 4,
32 pxa_lcdc_18bpp = 5,
33 pxa_lcdc_18pbpp = 6,
34 pxa_lcdc_19bpp = 7,
35 pxa_lcdc_19pbpp = 8,
36 pxa_lcdc_24bpp = 9,
37 pxa_lcdc_25bpp = 10,
38 } bpp;
39
40 uint32_t control[6];
41 uint32_t status[2];
42 uint32_t ovl1c[2];
43 uint32_t ovl2c[2];
44 uint32_t ccr;
45 uint32_t cmdcr;
46 uint32_t trgbr;
47 uint32_t tcr;
48 uint32_t liidr;
49 uint8_t bscntr;
50
51 struct {
52 target_phys_addr_t branch;
53 int up;
54 uint8_t palette[1024];
55 uint8_t pbuffer[1024];
56 void (*redraw)(struct pxa2xx_lcdc_s *s, uint8_t *fb,
57 int *miny, int *maxy);
58
59 target_phys_addr_t descriptor;
60 target_phys_addr_t source;
61 uint32_t id;
62 uint32_t command;
63 } dma_ch[7];
64
65 void (*vsync_cb)(void *opaque);
66 void *opaque;
67 int orientation;
68};
69
70struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
71 uint32_t fdaddr;
72 uint32_t fsaddr;
73 uint32_t fidr;
74 uint32_t ldcmd;
75};
76
77#define LCCR0 0x000 /* LCD Controller Control register 0 */
78#define LCCR1 0x004 /* LCD Controller Control register 1 */
79#define LCCR2 0x008 /* LCD Controller Control register 2 */
80#define LCCR3 0x00c /* LCD Controller Control register 3 */
81#define LCCR4 0x010 /* LCD Controller Control register 4 */
82#define LCCR5 0x014 /* LCD Controller Control register 5 */
83
84#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
85#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
86#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
87#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
88#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
89#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
90#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
91
92#define LCSR1 0x034 /* LCD Controller Status register 1 */
93#define LCSR0 0x038 /* LCD Controller Status register 0 */
94#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
95
96#define TRGBR 0x040 /* TMED RGB Seed register */
97#define TCR 0x044 /* TMED Control register */
98
99#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
100#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
101#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
102#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
103#define CCR 0x090 /* Cursor Control register */
104
105#define CMDCR 0x100 /* Command Control register */
106#define PRSR 0x104 /* Panel Read Status register */
107
108#define PXA_LCDDMA_CHANS 7
109#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
110#define DMA_FSADR 0x04 /* Frame Source Address register */
111#define DMA_FIDR 0x08 /* Frame ID register */
112#define DMA_LDCMD 0x0c /* Command register */
113
114/* LCD Buffer Strength Control register */
115#define BSCNTR 0x04000054
116
117/* Bitfield masks */
118#define LCCR0_ENB (1 << 0)
119#define LCCR0_CMS (1 << 1)
120#define LCCR0_SDS (1 << 2)
121#define LCCR0_LDM (1 << 3)
122#define LCCR0_SOFM0 (1 << 4)
123#define LCCR0_IUM (1 << 5)
124#define LCCR0_EOFM0 (1 << 6)
125#define LCCR0_PAS (1 << 7)
126#define LCCR0_DPD (1 << 9)
127#define LCCR0_DIS (1 << 10)
128#define LCCR0_QDM (1 << 11)
129#define LCCR0_PDD (0xff << 12)
130#define LCCR0_BSM0 (1 << 20)
131#define LCCR0_OUM (1 << 21)
132#define LCCR0_LCDT (1 << 22)
133#define LCCR0_RDSTM (1 << 23)
134#define LCCR0_CMDIM (1 << 24)
135#define LCCR0_OUC (1 << 25)
136#define LCCR0_LDDALT (1 << 26)
137#define LCCR1_PPL(x) ((x) & 0x3ff)
138#define LCCR2_LPP(x) ((x) & 0x3ff)
139#define LCCR3_API (15 << 16)
140#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
141#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
142#define LCCR4_K1(x) (((x) >> 0) & 7)
143#define LCCR4_K2(x) (((x) >> 3) & 7)
144#define LCCR4_K3(x) (((x) >> 6) & 7)
145#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
146#define LCCR5_SOFM(ch) (1 << (ch - 1))
147#define LCCR5_EOFM(ch) (1 << (ch + 7))
148#define LCCR5_BSM(ch) (1 << (ch + 15))
149#define LCCR5_IUM(ch) (1 << (ch + 23))
150#define OVLC1_EN (1 << 31)
151#define CCR_CEN (1 << 31)
152#define FBR_BRA (1 << 0)
153#define FBR_BINT (1 << 1)
154#define FBR_SRCADDR (0xfffffff << 4)
155#define LCSR0_LDD (1 << 0)
156#define LCSR0_SOF0 (1 << 1)
157#define LCSR0_BER (1 << 2)
158#define LCSR0_ABC (1 << 3)
159#define LCSR0_IU0 (1 << 4)
160#define LCSR0_IU1 (1 << 5)
161#define LCSR0_OU (1 << 6)
162#define LCSR0_QD (1 << 7)
163#define LCSR0_EOF0 (1 << 8)
164#define LCSR0_BS0 (1 << 9)
165#define LCSR0_SINT (1 << 10)
166#define LCSR0_RDST (1 << 11)
167#define LCSR0_CMDINT (1 << 12)
168#define LCSR0_BERCH(x) (((x) & 7) << 28)
169#define LCSR1_SOF(ch) (1 << (ch - 1))
170#define LCSR1_EOF(ch) (1 << (ch + 7))
171#define LCSR1_BS(ch) (1 << (ch + 15))
172#define LCSR1_IU(ch) (1 << (ch + 23))
173#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
174#define LDCMD_EOFINT (1 << 21)
175#define LDCMD_SOFINT (1 << 22)
176#define LDCMD_PAL (1 << 26)
177
178/* Route internal interrupt lines to the global IC */
179static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s)
180{
181 int level = 0;
182 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
183 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
184 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
185 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
186 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
187 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
188 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
189 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
190 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
191 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
192 level |= (s->status[1] & ~s->control[5]);
193
194 qemu_set_irq(s->irq, !!level);
195 s->irqlevel = level;
196}
197
198/* Set Branch Status interrupt high and poke associated registers */
199static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch)
200{
201 int unmasked;
202 if (ch == 0) {
203 s->status[0] |= LCSR0_BS0;
204 unmasked = !(s->control[0] & LCCR0_BSM0);
205 } else {
206 s->status[1] |= LCSR1_BS(ch);
207 unmasked = !(s->control[5] & LCCR5_BSM(ch));
208 }
209
210 if (unmasked) {
211 if (s->irqlevel)
212 s->status[0] |= LCSR0_SINT;
213 else
214 s->liidr = s->dma_ch[ch].id;
215 }
216}
217
218/* Set Start Of Frame Status interrupt high and poke associated registers */
219static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch)
220{
221 int unmasked;
222 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
223 return;
224
225 if (ch == 0) {
226 s->status[0] |= LCSR0_SOF0;
227 unmasked = !(s->control[0] & LCCR0_SOFM0);
228 } else {
229 s->status[1] |= LCSR1_SOF(ch);
230 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
231 }
232
233 if (unmasked) {
234 if (s->irqlevel)
235 s->status[0] |= LCSR0_SINT;
236 else
237 s->liidr = s->dma_ch[ch].id;
238 }
239}
240
241/* Set End Of Frame Status interrupt high and poke associated registers */
242static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch)
243{
244 int unmasked;
245 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
246 return;
247
248 if (ch == 0) {
249 s->status[0] |= LCSR0_EOF0;
250 unmasked = !(s->control[0] & LCCR0_EOFM0);
251 } else {
252 s->status[1] |= LCSR1_EOF(ch);
253 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
254 }
255
256 if (unmasked) {
257 if (s->irqlevel)
258 s->status[0] |= LCSR0_SINT;
259 else
260 s->liidr = s->dma_ch[ch].id;
261 }
262}
263
264/* Set Bus Error Status interrupt high and poke associated registers */
265static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch)
266{
267 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
268 if (s->irqlevel)
269 s->status[0] |= LCSR0_SINT;
270 else
271 s->liidr = s->dma_ch[ch].id;
272}
273
274/* Set Read Status interrupt high and poke associated registers */
275static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s)
276{
277 s->status[0] |= LCSR0_RDST;
278 if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
279 s->status[0] |= LCSR0_SINT;
280}
281
282/* Load new Frame Descriptors from DMA */
283static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
284{
285 struct pxa_frame_descriptor_s *desc[PXA_LCDDMA_CHANS];
286 target_phys_addr_t descptr;
287 int i;
288
289 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
290 desc[i] = 0;
291 s->dma_ch[i].source = 0;
292
293 if (!s->dma_ch[i].up)
294 continue;
295
296 if (s->dma_ch[i].branch & FBR_BRA) {
297 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
298 if (s->dma_ch[i].branch & FBR_BINT)
299 pxa2xx_dma_bs_set(s, i);
300 s->dma_ch[i].branch &= ~FBR_BRA;
301 } else
302 descptr = s->dma_ch[i].descriptor;
303
d95b2f8d
AZ		 304 if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
305 sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size))
a171fe39
AZ		 306 continue;
307
d95b2f8d 308 descptr -= PXA2XX_SDRAM_BASE;
a171fe39
AZ		 309 desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr);
310 s->dma_ch[i].descriptor = desc[i]->fdaddr;
311 s->dma_ch[i].source = desc[i]->fsaddr;
312 s->dma_ch[i].id = desc[i]->fidr;
313 s->dma_ch[i].command = desc[i]->ldcmd;
314 }
315}
316
317static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
318{
319 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
320 int ch;
321 offset -= s->base;
322
323 switch (offset) {
324 case LCCR0:
325 return s->control[0];
326 case LCCR1:
327 return s->control[1];
328 case LCCR2:
329 return s->control[2];
330 case LCCR3:
331 return s->control[3];
332 case LCCR4:
333 return s->control[4];
334 case LCCR5:
335 return s->control[5];
336
337 case OVL1C1:
338 return s->ovl1c[0];
339 case OVL1C2:
340 return s->ovl1c[1];
341 case OVL2C1:
342 return s->ovl2c[0];
343 case OVL2C2:
344 return s->ovl2c[1];
345
346 case CCR:
347 return s->ccr;
348
349 case CMDCR:
350 return s->cmdcr;
351
352 case TRGBR:
353 return s->trgbr;
354 case TCR:
355 return s->tcr;
356
357 case 0x200 ... 0x1000: /* DMA per-channel registers */
358 ch = (offset - 0x200) >> 4;
359 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
360 goto fail;
361
362 switch (offset & 0xf) {
363 case DMA_FDADR:
364 return s->dma_ch[ch].descriptor;
365 case DMA_FSADR:
366 return s->dma_ch[ch].source;
367 case DMA_FIDR:
368 return s->dma_ch[ch].id;
369 case DMA_LDCMD:
370 return s->dma_ch[ch].command;
371 default:
372 goto fail;
373 }
374
375 case FBR0:
376 return s->dma_ch[0].branch;
377 case FBR1:
378 return s->dma_ch[1].branch;
379 case FBR2:
380 return s->dma_ch[2].branch;
381 case FBR3:
382 return s->dma_ch[3].branch;
383 case FBR4:
384 return s->dma_ch[4].branch;
385 case FBR5:
386 return s->dma_ch[5].branch;
387 case FBR6:
388 return s->dma_ch[6].branch;
389
390 case BSCNTR:
391 return s->bscntr;
392
393 case PRSR:
394 return 0;
395
396 case LCSR0:
397 return s->status[0];
398 case LCSR1:
399 return s->status[1];
400 case LIIDR:
401 return s->liidr;
402
403 default:
404 fail:
405 cpu_abort(cpu_single_env,
406 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
407 }
408
409 return 0;
410}
411
412static void pxa2xx_lcdc_write(void *opaque,
413 target_phys_addr_t offset, uint32_t value)
414{
415 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
416 int ch;
417 offset -= s->base;
418
419 switch (offset) {
420 case LCCR0:
421 /* ACK Quick Disable done */
422 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
423 s->status[0] |= LCSR0_QD;
424
425 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
426 printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
427
428 if ((s->control[3] & LCCR3_API) &&
429 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
430 s->status[0] |= LCSR0_ABC;
431
432 s->control[0] = value & 0x07ffffff;
433 pxa2xx_lcdc_int_update(s);
434
435 s->dma_ch[0].up = !!(value & LCCR0_ENB);
436 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
437 break;
438
439 case LCCR1:
440 s->control[1] = value;
441 break;
442
443 case LCCR2:
444 s->control[2] = value;
445 break;
446
447 case LCCR3:
448 s->control[3] = value & 0xefffffff;
449 s->bpp = LCCR3_BPP(value);
450 break;
451
452 case LCCR4:
453 s->control[4] = value & 0x83ff81ff;
454 break;
455
456 case LCCR5:
457 s->control[5] = value & 0x3f3f3f3f;
458 break;
459
460 case OVL1C1:
461 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
462 printf("%s: Overlay 1 not supported\n", __FUNCTION__);
463
464 s->ovl1c[0] = value & 0x80ffffff;
465 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
466 break;
467
468 case OVL1C2:
469 s->ovl1c[1] = value & 0x000fffff;
470 break;
471
472 case OVL2C1:
473 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
474 printf("%s: Overlay 2 not supported\n", __FUNCTION__);
475
476 s->ovl2c[0] = value & 0x80ffffff;
477 s->dma_ch[2].up = !!(value & OVLC1_EN);
478 s->dma_ch[3].up = !!(value & OVLC1_EN);
479 s->dma_ch[4].up = !!(value & OVLC1_EN);
480 break;
481
482 case OVL2C2:
483 s->ovl2c[1] = value & 0x007fffff;
484 break;
485
486 case CCR:
487 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
488 printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
489
490 s->ccr = value & 0x81ffffe7;
491 s->dma_ch[5].up = !!(value & CCR_CEN);
492 break;
493
494 case CMDCR:
495 s->cmdcr = value & 0xff;
496 break;
497
498 case TRGBR:
499 s->trgbr = value & 0x00ffffff;
500 break;
501
502 case TCR:
503 s->tcr = value & 0x7fff;
504 break;
505
506 case 0x200 ... 0x1000: /* DMA per-channel registers */
507 ch = (offset - 0x200) >> 4;
508 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
509 goto fail;
510
511 switch (offset & 0xf) {
512 case DMA_FDADR:
513 s->dma_ch[ch].descriptor = value & 0xfffffff0;
514 break;
515
516 default:
517 goto fail;
518 }
519 break;
520
521 case FBR0:
522 s->dma_ch[0].branch = value & 0xfffffff3;
523 break;
524 case FBR1:
525 s->dma_ch[1].branch = value & 0xfffffff3;
526 break;
527 case FBR2:
528 s->dma_ch[2].branch = value & 0xfffffff3;
529 break;
530 case FBR3:
531 s->dma_ch[3].branch = value & 0xfffffff3;
532 break;
533 case FBR4:
534 s->dma_ch[4].branch = value & 0xfffffff3;
535 break;
536 case FBR5:
537 s->dma_ch[5].branch = value & 0xfffffff3;
538 break;
539 case FBR6:
540 s->dma_ch[6].branch = value & 0xfffffff3;
541 break;
542
543 case BSCNTR:
544 s->bscntr = value & 0xf;
545 break;
546
547 case PRSR:
548 break;
549
550 case LCSR0:
551 s->status[0] &= ~(value & 0xfff);
552 if (value & LCSR0_BER)
553 s->status[0] &= ~LCSR0_BERCH(7);
554 break;
555
556 case LCSR1:
557 s->status[1] &= ~(value & 0x3e3f3f);
558 break;
559
560 default:
561 fail:
562 cpu_abort(cpu_single_env,
563 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
564 }
565}
566
567static CPUReadMemoryFunc *pxa2xx_lcdc_readfn[] = {
568 pxa2xx_lcdc_read,
569 pxa2xx_lcdc_read,
570 pxa2xx_lcdc_read
571};
572
573static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
574 pxa2xx_lcdc_write,
575 pxa2xx_lcdc_write,
576 pxa2xx_lcdc_write
577};
578
a171fe39
AZ		 579/* Load new palette for a given DMA channel, convert to internal format */
580static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp)
581{
582 int i, n, format, r, g, b, alpha;
583 uint32_t *dest, *src;
584 s->pal_for = LCCR4_PALFOR(s->control[4]);
585 format = s->pal_for;
586
587 switch (bpp) {
588 case pxa_lcdc_2bpp:
589 n = 4;
590 break;
591 case pxa_lcdc_4bpp:
592 n = 16;
593 break;
594 case pxa_lcdc_8bpp:
595 n = 256;
596 break;
597 default:
598 format = 0;
599 return;
600 }
601
602 src = (uint32_t *) s->dma_ch[ch].pbuffer;
603 dest = (uint32_t *) s->dma_ch[ch].palette;
604 alpha = r = g = b = 0;
605
606 for (i = 0; i < n; i ++) {
607 switch (format) {
608 case 0: /* 16 bpp, no transparency */
609 alpha = 0;
610 if (s->control[0] & LCCR0_CMS)
611 r = g = b = *src & 0xff;
612 else {
613 r = (*src & 0xf800) >> 8;
614 g = (*src & 0x07e0) >> 3;
615 b = (*src & 0x001f) << 3;
616 }
617 break;
618 case 1: /* 16 bpp plus transparency */
619 alpha = *src & (1 << 24);
620 if (s->control[0] & LCCR0_CMS)
621 r = g = b = *src & 0xff;
622 else {
623 r = (*src & 0xf800) >> 8;
624 g = (*src & 0x07e0) >> 3;
625 b = (*src & 0x001f) << 3;
626 }
627 break;
628 case 2: /* 18 bpp plus transparency */
629 alpha = *src & (1 << 24);
630 if (s->control[0] & LCCR0_CMS)
631 r = g = b = *src & 0xff;
632 else {
633 r = (*src & 0xf80000) >> 16;
634 g = (*src & 0x00fc00) >> 8;
635 b = (*src & 0x0000f8);
636 }
637 break;
638 case 3: /* 24 bpp plus transparency */
639 alpha = *src & (1 << 24);
640 if (s->control[0] & LCCR0_CMS)
641 r = g = b = *src & 0xff;
642 else {
643 r = (*src & 0xff0000) >> 16;
644 g = (*src & 0x00ff00) >> 8;
645 b = (*src & 0x0000ff);
646 }
647 break;
648 }
649 switch (s->ds->depth) {
650 case 8:
651 *dest = rgb_to_pixel8(r, g, b) | alpha;
652 break;
653 case 15:
654 *dest = rgb_to_pixel15(r, g, b) | alpha;
655 break;
656 case 16:
657 *dest = rgb_to_pixel16(r, g, b) | alpha;
658 break;
659 case 24:
660 *dest = rgb_to_pixel24(r, g, b) | alpha;
661 break;
662 case 32:
663 *dest = rgb_to_pixel32(r, g, b) | alpha;
664 break;
665 }
666 src ++;
667 dest ++;
668 }
669}
670
671static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s,
672 uint8_t *fb, int *miny, int *maxy)
673{
674 int y, src_width, dest_width, dirty[2];
675 uint8_t *src, *dest;
676 ram_addr_t x, addr, new_addr, start, end;
677 drawfn fn = 0;
678 if (s->dest_width)
679 fn = s->line_fn[s->transp][s->bpp];
680 if (!fn)
681 return;
682
683 src = fb;
684 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
685 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
686 src_width *= 3;
687 else if (s->bpp > pxa_lcdc_16bpp)
688 src_width *= 4;
689 else if (s->bpp > pxa_lcdc_8bpp)
690 src_width *= 2;
691
692 dest = s->ds->data;
693 dest_width = s->xres * s->dest_width;
694
695 addr = (ram_addr_t) (fb - phys_ram_base);
696 start = addr + s->yres * src_width;
697 end = addr;
698 dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
699 for (y = 0; y < s->yres; y ++) {
700 new_addr = addr + src_width;
701 for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
702 x += TARGET_PAGE_SIZE) {
703 dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
704 dirty[0] |= dirty[1];
705 }
706 if (dirty[0] || s->invalidated) {
707 fn((uint32_t *) s->dma_ch[0].palette,
708 dest, src, s->xres, s->dest_width);
709 if (addr < start)
710 start = addr;
a07dec22 711 end = new_addr;
a171fe39
AZ		 712 if (y < *miny)
713 *miny = y;
714 if (y >= *maxy)
715 *maxy = y + 1;
716 }
717 addr = new_addr;
718 dirty[0] = dirty[1];
719 src += src_width;
720 dest += dest_width;
721 }
722
723 if (end > start)
724 cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
725}
726
727static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s,
728 uint8_t *fb, int *miny, int *maxy)
729{
730 int y, src_width, dest_width, dirty[2];
731 uint8_t *src, *dest;
732 ram_addr_t x, addr, new_addr, start, end;
733 drawfn fn = 0;
734 if (s->dest_width)
735 fn = s->line_fn[s->transp][s->bpp];
736 if (!fn)
737 return;
738
739 src = fb;
740 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
741 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
742 src_width *= 3;
743 else if (s->bpp > pxa_lcdc_16bpp)
744 src_width *= 4;
745 else if (s->bpp > pxa_lcdc_8bpp)
746 src_width *= 2;
747
748 dest_width = s->yres * s->dest_width;
749 dest = s->ds->data + dest_width * (s->xres - 1);
750
751 addr = (ram_addr_t) (fb - phys_ram_base);
752 start = addr + s->yres * src_width;
753 end = addr;
754 dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
755 for (y = 0; y < s->yres; y ++) {
756 new_addr = addr + src_width;
757 for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
758 x += TARGET_PAGE_SIZE) {
759 dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
760 dirty[0] |= dirty[1];
761 }
762 if (dirty[0] || s->invalidated) {
763 fn((uint32_t *) s->dma_ch[0].palette,
764 dest, src, s->xres, -dest_width);
765 if (addr < start)
766 start = addr;
3f582262 767 end = new_addr;
a171fe39
AZ		 768 if (y < *miny)
769 *miny = y;
770 if (y >= *maxy)
771 *maxy = y + 1;
772 }
773 addr = new_addr;
774 dirty[0] = dirty[1];
775 src += src_width;
776 dest += s->dest_width;
777 }
778
779 if (end > start)
780 cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
781}
782
783static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s)
784{
785 int width, height;
786 if (!(s->control[0] & LCCR0_ENB))
787 return;
788
789 width = LCCR1_PPL(s->control[1]) + 1;
790 height = LCCR2_LPP(s->control[2]) + 1;
791
792 if (width != s->xres || height != s->yres) {
793 if (s->orientation)
794 dpy_resize(s->ds, height, width);
795 else
796 dpy_resize(s->ds, width, height);
797 s->invalidated = 1;
798 s->xres = width;
799 s->yres = height;
800 }
801}
802
803static void pxa2xx_update_display(void *opaque)
804{
805 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
806 uint8_t *fb;
807 target_phys_addr_t fbptr;
808 int miny, maxy;
809 int ch;
810 if (!(s->control[0] & LCCR0_ENB))
811 return;
812
813 pxa2xx_descriptor_load(s);
814
815 pxa2xx_lcdc_resize(s);
816 miny = s->yres;
817 maxy = 0;
818 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
819 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
820 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
821 if (s->dma_ch[ch].up) {
822 if (!s->dma_ch[ch].source) {
823 pxa2xx_dma_ber_set(s, ch);
824 continue;
825 }
826 fbptr = s->dma_ch[ch].source;
d95b2f8d
AZ		 827 if (!(fbptr >= PXA2XX_SDRAM_BASE &&
828 fbptr <= PXA2XX_SDRAM_BASE + phys_ram_size)) {
a171fe39
AZ		 829 pxa2xx_dma_ber_set(s, ch);
830 continue;
831 }
d95b2f8d 832 fbptr -= PXA2XX_SDRAM_BASE;
a171fe39
AZ		 833 fb = phys_ram_base + fbptr;
834
835 if (s->dma_ch[ch].command & LDCMD_PAL) {
836 memcpy(s->dma_ch[ch].pbuffer, fb,
837 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
838 sizeof(s->dma_ch[ch].pbuffer)));
839 pxa2xx_palette_parse(s, ch, s->bpp);
840 } else {
841 /* Do we need to reparse palette */
842 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
843 pxa2xx_palette_parse(s, ch, s->bpp);
844
845 /* ACK frame start */
846 pxa2xx_dma_sof_set(s, ch);
847
848 s->dma_ch[ch].redraw(s, fb, &miny, &maxy);
849 s->invalidated = 0;
850
851 /* ACK frame completed */
852 pxa2xx_dma_eof_set(s, ch);
853 }
854 }
855
856 if (s->control[0] & LCCR0_DIS) {
857 /* ACK last frame completed */
858 s->control[0] &= ~LCCR0_ENB;
859 s->status[0] |= LCSR0_LDD;
860 }
861
862 if (s->orientation)
863 dpy_update(s->ds, miny, 0, maxy, s->xres);
864 else
865 dpy_update(s->ds, 0, miny, s->xres, maxy);
866 pxa2xx_lcdc_int_update(s);
867
868 if (s->vsync_cb)
869 s->vsync_cb(s->opaque);
870}
871
872static void pxa2xx_invalidate_display(void *opaque)
873{
874 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
875 s->invalidated = 1;
876}
877
878static void pxa2xx_screen_dump(void *opaque, const char *filename)
879{
880 /* TODO */
881}
882
883void pxa2xx_lcdc_orientation(void *opaque, int angle)
884{
885 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
886
887 if (angle) {
888 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
889 } else {
890 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
891 }
892
893 s->orientation = angle;
894 s->xres = s->yres = -1;
895 pxa2xx_lcdc_resize(s);
896}
897
aa941b94
AZ		 898static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)
899{
900 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
901 int i;
902
903 qemu_put_be32(f, s->irqlevel);
904 qemu_put_be32(f, s->transp);
905
906 for (i = 0; i < 6; i ++)
907 qemu_put_be32s(f, &s->control[i]);
908 for (i = 0; i < 2; i ++)
909 qemu_put_be32s(f, &s->status[i]);
910 for (i = 0; i < 2; i ++)
911 qemu_put_be32s(f, &s->ovl1c[i]);
912 for (i = 0; i < 2; i ++)
913 qemu_put_be32s(f, &s->ovl2c[i]);
914 qemu_put_be32s(f, &s->ccr);
915 qemu_put_be32s(f, &s->cmdcr);
916 qemu_put_be32s(f, &s->trgbr);
917 qemu_put_be32s(f, &s->tcr);
918 qemu_put_be32s(f, &s->liidr);
919 qemu_put_8s(f, &s->bscntr);
920
921 for (i = 0; i < 7; i ++) {
922 qemu_put_betl(f, s->dma_ch[i].branch);
923 qemu_put_byte(f, s->dma_ch[i].up);
924 qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
925
926 qemu_put_betl(f, s->dma_ch[i].descriptor);
927 qemu_put_betl(f, s->dma_ch[i].source);
928 qemu_put_be32s(f, &s->dma_ch[i].id);
929 qemu_put_be32s(f, &s->dma_ch[i].command);
930 }
931}
932
933static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
934{
935 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
936 int i;
937
938 s->irqlevel = qemu_get_be32(f);
939 s->transp = qemu_get_be32(f);
940
941 for (i = 0; i < 6; i ++)
942 qemu_get_be32s(f, &s->control[i]);
943 for (i = 0; i < 2; i ++)
944 qemu_get_be32s(f, &s->status[i]);
945 for (i = 0; i < 2; i ++)
946 qemu_get_be32s(f, &s->ovl1c[i]);
947 for (i = 0; i < 2; i ++)
948 qemu_get_be32s(f, &s->ovl2c[i]);
949 qemu_get_be32s(f, &s->ccr);
950 qemu_get_be32s(f, &s->cmdcr);
951 qemu_get_be32s(f, &s->trgbr);
952 qemu_get_be32s(f, &s->tcr);
953 qemu_get_be32s(f, &s->liidr);
954 qemu_get_8s(f, &s->bscntr);
955
956 for (i = 0; i < 7; i ++) {
957 s->dma_ch[i].branch = qemu_get_betl(f);
958 s->dma_ch[i].up = qemu_get_byte(f);
959 qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
960
961 s->dma_ch[i].descriptor = qemu_get_betl(f);
962 s->dma_ch[i].source = qemu_get_betl(f);
963 qemu_get_be32s(f, &s->dma_ch[i].id);
964 qemu_get_be32s(f, &s->dma_ch[i].command);
965 }
966
967 s->bpp = LCCR3_BPP(s->control[3]);
968 s->xres = s->yres = s->pal_for = -1;
969
970 return 0;
971}
972
a171fe39
AZ		 973#define BITS 8
974#include "pxa2xx_template.h"
975#define BITS 15
976#include "pxa2xx_template.h"
977#define BITS 16
978#include "pxa2xx_template.h"
979#define BITS 24
980#include "pxa2xx_template.h"
981#define BITS 32
982#include "pxa2xx_template.h"
983
984struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
985 DisplayState *ds)
986{
987 int iomemtype;
988 struct pxa2xx_lcdc_s *s;
989
990 s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s));
991 s->base = base;
992 s->invalidated = 1;
993 s->irq = irq;
994 s->ds = ds;
995
996 pxa2xx_lcdc_orientation(s, graphic_rotate);
997
998 iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
999 pxa2xx_lcdc_writefn, s);
187337f8 1000 cpu_register_physical_memory(base, 0x00100000, iomemtype);
a171fe39
AZ		 1001
1002 graphic_console_init(ds, pxa2xx_update_display,
1003 pxa2xx_invalidate_display, pxa2xx_screen_dump, s);
1004
1005 switch (s->ds->depth) {
1006 case 0:
1007 s->dest_width = 0;
1008 break;
1009 case 8:
1010 s->line_fn[0] = pxa2xx_draw_fn_8;
1011 s->line_fn[1] = pxa2xx_draw_fn_8t;
1012 s->dest_width = 1;
1013 break;
1014 case 15:
1015 s->line_fn[0] = pxa2xx_draw_fn_15;
1016 s->line_fn[1] = pxa2xx_draw_fn_15t;
1017 s->dest_width = 2;
1018 break;
1019 case 16:
1020 s->line_fn[0] = pxa2xx_draw_fn_16;
1021 s->line_fn[1] = pxa2xx_draw_fn_16t;
1022 s->dest_width = 2;
1023 break;
1024 case 24:
1025 s->line_fn[0] = pxa2xx_draw_fn_24;
1026 s->line_fn[1] = pxa2xx_draw_fn_24t;
1027 s->dest_width = 3;
1028 break;
1029 case 32:
1030 s->line_fn[0] = pxa2xx_draw_fn_32;
1031 s->line_fn[1] = pxa2xx_draw_fn_32t;
1032 s->dest_width = 4;
1033 break;
1034 default:
1035 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
1036 exit(1);
1037 }
aa941b94
AZ		 1038
1039 register_savevm("pxa2xx_lcdc", 0, 0,
1040 pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);
1041
a171fe39
AZ		 1042 return s;
1043}
1044
1045void pxa2xx_lcd_vsync_cb(struct pxa2xx_lcdc_s *s,
1046 void (*cb)(void *opaque), void *opaque) {
1047 s->vsync_cb = cb;
1048 s->opaque = opaque;
1049}
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