[qemu.git] / target-m68k / cpu.h

/*
 * m68k virtual CPU header
 *
 *  Copyright (c) 2005-2007 CodeSourcery
 *  Written by Paul Brook
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef M68K_CPU_H
#define M68K_CPU_H

#define TARGET_LONG_BITS 32

#define CPUArchState struct CPUM68KState

#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
#include "fpu/softfloat.h"

#define MAX_QREGS 32

#define EXCP_ACCESS         2   /* Access (MMU) error.  */
#define EXCP_ADDRESS        3   /* Address error.  */
#define EXCP_ILLEGAL        4   /* Illegal instruction.  */
#define EXCP_DIV0           5   /* Divide by zero */
#define EXCP_PRIVILEGE      8   /* Privilege violation.  */
#define EXCP_TRACE          9
#define EXCP_LINEA          10  /* Unimplemented line-A (MAC) opcode.  */
#define EXCP_LINEF          11  /* Unimplemented line-F (FPU) opcode.  */
#define EXCP_DEBUGNBP       12  /* Non-breakpoint debug interrupt.  */
#define EXCP_DEBEGBP        13  /* Breakpoint debug interrupt.  */
#define EXCP_FORMAT         14  /* RTE format error.  */
#define EXCP_UNINITIALIZED  15
#define EXCP_TRAP0          32   /* User trap #0.  */
#define EXCP_TRAP15         47   /* User trap #15.  */
#define EXCP_UNSUPPORTED    61
#define EXCP_ICE            13

#define EXCP_RTE            0x100
#define EXCP_HALT_INSN      0x101

#define NB_MMU_MODES 2

typedef struct CPUM68KState {
    uint32_t dregs[8];
    uint32_t aregs[8];
    uint32_t pc;
    uint32_t sr;

    /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
    int current_sp;
    uint32_t sp[2];

    /* Condition flags.  */
    uint32_t cc_op;
    uint32_t cc_dest;
    uint32_t cc_src;
    uint32_t cc_x;

    float64 fregs[8];
    float64 fp_result;
    uint32_t fpcr;
    uint32_t fpsr;
    float_status fp_status;

    uint64_t mactmp;
    /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
       two 8-bit parts.  We store a single 64-bit value and
       rearrange/extend this when changing modes.  */
    uint64_t macc[4];
    uint32_t macsr;
    uint32_t mac_mask;

    /* Temporary storage for DIV helpers.  */
    uint32_t div1;
    uint32_t div2;

    /* MMU status.  */
    struct {
        uint32_t ar;
    } mmu;

    /* Control registers.  */
    uint32_t vbr;
    uint32_t mbar;
    uint32_t rambar0;
    uint32_t cacr;

    int pending_vector;
    int pending_level;

    uint32_t qregs[MAX_QREGS];

    CPU_COMMON

    /* Fields from here on are preserved across CPU reset. */
    uint32_t features;
} CPUM68KState;

/**
 * M68kCPU:
 * @env: #CPUM68KState
 *
 * A Motorola 68k CPU.
 */
struct M68kCPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/

    CPUM68KState env;
};

static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
{
    return container_of(env, M68kCPU, env);
}

#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))

#define ENV_OFFSET offsetof(M68kCPU, env)

void m68k_cpu_do_interrupt(CPUState *cpu);
bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
                         int flags);
hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

void m68k_cpu_exec_enter(CPUState *cs);
void m68k_cpu_exec_exit(CPUState *cs);

void m68k_tcg_init(void);
void m68k_cpu_init_gdb(M68kCPU *cpu);
M68kCPU *cpu_m68k_init(const char *cpu_model);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_m68k_signal_handler(int host_signum, void *pinfo,
                           void *puc);
void cpu_m68k_flush_flags(CPUM68KState *, int);


/* Instead of computing the condition codes after each m68k instruction,
 * QEMU just stores one operand (called CC_SRC), the result
 * (called CC_DEST) and the type of operation (called CC_OP). When the
 * condition codes are needed, the condition codes can be calculated
 * using this information. Condition codes are not generated if they
 * are only needed for conditional branches.
 */
enum {
    CC_OP_DYNAMIC, /* Use env->cc_op  */
    CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
    CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
    CC_OP_ADD,   /* CC_DEST = result, CC_SRC = source */
    CC_OP_SUB,   /* CC_DEST = result, CC_SRC = source */
    CC_OP_CMPB,  /* CC_DEST = result, CC_SRC = source */
    CC_OP_CMPW,  /* CC_DEST = result, CC_SRC = source */
    CC_OP_ADDX,  /* CC_DEST = result, CC_SRC = source */
    CC_OP_SUBX,  /* CC_DEST = result, CC_SRC = source */
    CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
};

#define CCF_C 0x01
#define CCF_V 0x02
#define CCF_Z 0x04
#define CCF_N 0x08
#define CCF_X 0x10

#define SR_I_SHIFT 8
#define SR_I  0x0700
#define SR_M  0x1000
#define SR_S  0x2000
#define SR_T  0x8000

#define M68K_SSP    0
#define M68K_USP    1

/* CACR fields are implementation defined, but some bits are common.  */
#define M68K_CACR_EUSP  0x10

#define MACSR_PAV0  0x100
#define MACSR_OMC   0x080
#define MACSR_SU    0x040
#define MACSR_FI    0x020
#define MACSR_RT    0x010
#define MACSR_N     0x008
#define MACSR_Z     0x004
#define MACSR_V     0x002
#define MACSR_EV    0x001

void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
void m68k_switch_sp(CPUM68KState *env);

#define M68K_FPCR_PREC (1 << 6)

void do_m68k_semihosting(CPUM68KState *env, int nr);

/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
   Each feature covers the subset of instructions common to the
   ISA revisions mentioned.  */

enum m68k_features {
    M68K_FEATURE_M68000,
    M68K_FEATURE_CF_ISA_A,
    M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
    M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
    M68K_FEATURE_BRAL, /* Long unconditional branch.  (ISA A+ or B).  */
    M68K_FEATURE_CF_FPU,
    M68K_FEATURE_CF_MAC,
    M68K_FEATURE_CF_EMAC,
    M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
    M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
    M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
    M68K_FEATURE_WORD_INDEX, /* word sized address index registers.  */
    M68K_FEATURE_SCALED_INDEX, /* scaled address index registers.  */
    M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
    M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
    M68K_FEATURE_BCCL, /* Long conditional branches.  */
    M68K_FEATURE_BITFIELD, /* Bit field insns.  */
    M68K_FEATURE_FPU,
    M68K_FEATURE_CAS,
    M68K_FEATURE_BKPT,
};

static inline int m68k_feature(CPUM68KState *env, int feature)
{
    return (env->features & (1u << feature)) != 0;
}

void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);

void register_m68k_insns (CPUM68KState *env);

#ifdef CONFIG_USER_ONLY
/* Linux uses 8k pages.  */
#define TARGET_PAGE_BITS 13
#else
/* Smallest TLB entry size is 1k.  */
#define TARGET_PAGE_BITS 10
#endif

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))

#define cpu_signal_handler cpu_m68k_signal_handler
#define cpu_list m68k_cpu_list

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
{
    return (env->sr & SR_S) == 0 ? 1 : 0;
}

int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
                              int mmu_idx);

#include "exec/cpu-all.h"

static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
                                        target_ulong *cs_base, uint32_t *flags)
{
    *pc = env->pc;
    *cs_base = 0;
    *flags = (env->fpcr & M68K_FPCR_PREC)       /* Bit  6 */
            | (env->sr & SR_S)                  /* Bit  13 */
            | ((env->macsr >> 4) & 0xf);        /* Bits 0-3 */
}

#endif
Commit	Line	Data
e6e5906b PB	1	/*
e6e5906b PB	2	* m68k virtual CPU header
5fafdf24	3	*
0633879f	4	* Copyright (c) 2005-2007 CodeSourcery
e6e5906b PB	5	* Written by Paul Brook
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
e6e5906b	19	*/
07f5a258 MA	20
	21	#ifndef M68K_CPU_H
	22	#define M68K_CPU_H
e6e5906b PB	23
	24	#define TARGET_LONG_BITS 32
	25
9349b4f9	26	#define CPUArchState struct CPUM68KState
c2764719	27
9a78eead	28	#include "qemu-common.h"
022c62cb	29	#include "exec/cpu-defs.h"
a836b8fa	30	#include "cpu-qom.h"
6b4c305c	31	#include "fpu/softfloat.h"
e6e5906b PB	32
	33	#define MAX_QREGS 32
	34
e6e5906b PB	35	#define EXCP_ACCESS 2 /* Access (MMU) error. */
	36	#define EXCP_ADDRESS 3 /* Address error. */
	37	#define EXCP_ILLEGAL 4 /* Illegal instruction. */
	38	#define EXCP_DIV0 5 /* Divide by zero */
	39	#define EXCP_PRIVILEGE 8 /* Privilege violation. */
	40	#define EXCP_TRACE 9
	41	#define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */
	42	#define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */
	43	#define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */
	44	#define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */
	45	#define EXCP_FORMAT 14 /* RTE format error. */
	46	#define EXCP_UNINITIALIZED 15
	47	#define EXCP_TRAP0 32 /* User trap #0. */
	48	#define EXCP_TRAP15 47 /* User trap #15. */
	49	#define EXCP_UNSUPPORTED 61
	50	#define EXCP_ICE 13
	51
0633879f	52	#define EXCP_RTE 0x100
a87295e8	53	#define EXCP_HALT_INSN 0x101
0633879f	54
6ebbf390 JM	55	#define NB_MMU_MODES 2
6ebbf390 JM	56
e6e5906b PB	57	typedef struct CPUM68KState {
	58	uint32_t dregs[8];
	59	uint32_t aregs[8];
	60	uint32_t pc;
	61	uint32_t sr;
	62
20dcee94 PB	63	/* SSP and USP. The current_sp is stored in aregs[7], the other here. */
	64	int current_sp;
	65	uint32_t sp[2];
	66
e6e5906b PB	67	/* Condition flags. */
	68	uint32_t cc_op;
	69	uint32_t cc_dest;
	70	uint32_t cc_src;
	71	uint32_t cc_x;
	72
	73	float64 fregs[8];
	74	float64 fp_result;
	75	uint32_t fpcr;
	76	uint32_t fpsr;
	77	float_status fp_status;
	78
acf930aa PB	79	uint64_t mactmp;
	80	/* EMAC Hardware deals with 48-bit values composed of one 32-bit and
	81	two 8-bit parts. We store a single 64-bit value and
	82	rearrange/extend this when changing modes. */
	83	uint64_t macc[4];
	84	uint32_t macsr;
	85	uint32_t mac_mask;
	86
e6e5906b PB	87	/* Temporary storage for DIV helpers. */
	88	uint32_t div1;
	89	uint32_t div2;
3b46e624	90
e6e5906b PB	91	/* MMU status. */
	92	struct {
	93	uint32_t ar;
	94	} mmu;
0633879f PB	95
	96	/* Control registers. */
	97	uint32_t vbr;
	98	uint32_t mbar;
	99	uint32_t rambar0;
20dcee94	100	uint32_t cacr;
0633879f	101
0633879f PB	102	int pending_vector;
0633879f PB	103	int pending_level;
e6e5906b PB	104
	105	uint32_t qregs[MAX_QREGS];
	106
	107	CPU_COMMON
aaed909a	108
f0c3c505	109	/* Fields from here on are preserved across CPU reset. */
aaed909a	110	uint32_t features;
e6e5906b PB	111	} CPUM68KState;
e6e5906b PB	112
a836b8fa PB	113	/**
	114	* M68kCPU:
	115	* @env: #CPUM68KState
	116	*
	117	* A Motorola 68k CPU.
	118	*/
	119	struct M68kCPU {
	120	/< private >/
	121	CPUState parent_obj;
	122	/< public >/
	123
	124	CPUM68KState env;
	125	};
	126
	127	static inline M68kCPU m68k_env_get_cpu(CPUM68KState env)
	128	{
	129	return container_of(env, M68kCPU, env);
	130	}
	131
	132	#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
	133
	134	#define ENV_OFFSET offsetof(M68kCPU, env)
	135
	136	void m68k_cpu_do_interrupt(CPUState *cpu);
	137	bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
	138	void m68k_cpu_dump_state(CPUState cpu, FILE f, fprintf_function cpu_fprintf,
	139	int flags);
	140	hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
	141	int m68k_cpu_gdb_read_register(CPUState cpu, uint8_t buf, int reg);
	142	int m68k_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
	143
	144	void m68k_cpu_exec_enter(CPUState *cs);
	145	void m68k_cpu_exec_exit(CPUState *cs);
b9e7a234	146
e1f3808e	147	void m68k_tcg_init(void);
6d1bbc62	148	void m68k_cpu_init_gdb(M68kCPU *cpu);
c7937d9f	149	M68kCPU cpu_m68k_init(const char cpu_model);
e6e5906b PB	150	/* you can call this signal handler from your SIGBUS and SIGSEGV
	151	signal handlers to inform the virtual CPU of exceptions. non zero
	152	is returned if the signal was handled by the virtual CPU. */
5fafdf24	153	int cpu_m68k_signal_handler(int host_signum, void *pinfo,
e6e5906b PB	154	void *puc);
	155	void cpu_m68k_flush_flags(CPUM68KState *, int);
	156
c3ce5a23 PB	157
	158	/* Instead of computing the condition codes after each m68k instruction,
	159	* QEMU just stores one operand (called CC_SRC), the result
	160	* (called CC_DEST) and the type of operation (called CC_OP). When the
	161	* condition codes are needed, the condition codes can be calculated
	162	* using this information. Condition codes are not generated if they
	163	* are only needed for conditional branches.
	164	*/
e6e5906b PB	165	enum {
	166	CC_OP_DYNAMIC, /* Use env->cc_op */
	167	CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
	168	CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
	169	CC_OP_ADD, /* CC_DEST = result, CC_SRC = source */
	170	CC_OP_SUB, /* CC_DEST = result, CC_SRC = source */
	171	CC_OP_CMPB, /* CC_DEST = result, CC_SRC = source */
	172	CC_OP_CMPW, /* CC_DEST = result, CC_SRC = source */
	173	CC_OP_ADDX, /* CC_DEST = result, CC_SRC = source */
	174	CC_OP_SUBX, /* CC_DEST = result, CC_SRC = source */
e1f3808e	175	CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
e6e5906b PB	176	};
	177
	178	#define CCF_C 0x01
	179	#define CCF_V 0x02
	180	#define CCF_Z 0x04
	181	#define CCF_N 0x08
0633879f PB	182	#define CCF_X 0x10
	183
	184	#define SR_I_SHIFT 8
	185	#define SR_I 0x0700
	186	#define SR_M 0x1000
	187	#define SR_S 0x2000
	188	#define SR_T 0x8000
e6e5906b	189
20dcee94 PB	190	#define M68K_SSP 0
	191	#define M68K_USP 1
	192
	193	/* CACR fields are implementation defined, but some bits are common. */
	194	#define M68K_CACR_EUSP 0x10
	195
acf930aa PB	196	#define MACSR_PAV0 0x100
	197	#define MACSR_OMC 0x080
	198	#define MACSR_SU 0x040
	199	#define MACSR_FI 0x020
	200	#define MACSR_RT 0x010
	201	#define MACSR_N 0x008
	202	#define MACSR_Z 0x004
	203	#define MACSR_V 0x002
	204	#define MACSR_EV 0x001
	205
cb3fb38e	206	void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
20dcee94	207	void m68k_switch_sp(CPUM68KState *env);
e6e5906b PB	208
	209	#define M68K_FPCR_PREC (1 << 6)
	210
a87295e8 PB	211	void do_m68k_semihosting(CPUM68KState *env, int nr);
a87295e8 PB	212
d315c888 PB	213	/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
	214	Each feature covers the subset of instructions common to the
	215	ISA revisions mentioned. */
	216
0402f767	217	enum m68k_features {
f076803b	218	M68K_FEATURE_M68000,
0402f767	219	M68K_FEATURE_CF_ISA_A,
d315c888 PB	220	M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
	221	M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
	222	M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
0402f767 PB	223	M68K_FEATURE_CF_FPU,
	224	M68K_FEATURE_CF_MAC,
	225	M68K_FEATURE_CF_EMAC,
d315c888 PB	226	M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
d315c888 PB	227	M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
e6dbd3b3	228	M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
f076803b LV	229	M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */
	230	M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */
	231	M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
	232	M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
	233	M68K_FEATURE_BCCL, /* Long conditional branches. */
	234	M68K_FEATURE_BITFIELD, /* Bit field insns. */
	235	M68K_FEATURE_FPU,
	236	M68K_FEATURE_CAS,
	237	M68K_FEATURE_BKPT,
0402f767 PB	238	};
	239
	240	static inline int m68k_feature(CPUM68KState *env, int feature)
	241	{
	242	return (env->features & (1u << feature)) != 0;
	243	}
	244
9a78eead	245	void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
009a4356	246
0402f767 PB	247	void register_m68k_insns (CPUM68KState *env);
0402f767 PB	248
e6e5906b PB	249	#ifdef CONFIG_USER_ONLY
	250	/* Linux uses 8k pages. */
	251	#define TARGET_PAGE_BITS 13
	252	#else
5fafdf24	253	/* Smallest TLB entry size is 1k. */
e6e5906b PB	254	#define TARGET_PAGE_BITS 10
e6e5906b PB	255	#endif
9467d44c	256
52705890 RH	257	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	258	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	259
2994fd96	260	#define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))
c7937d9f	261
9467d44c	262	#define cpu_signal_handler cpu_m68k_signal_handler
009a4356	263	#define cpu_list m68k_cpu_list
9467d44c	264
6ebbf390 JM	265	/* MMU modes definitions */
	266	#define MMU_MODE0_SUFFIX _kernel
	267	#define MMU_MODE1_SUFFIX _user
	268	#define MMU_USER_IDX 1
97ed5ccd	269	static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
6ebbf390 JM	270	{
	271	return (env->sr & SR_S) == 0 ? 1 : 0;
	272	}
	273
7510454e	274	int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
97b348e7	275	int mmu_idx);
aaedd1f9	276
022c62cb	277	#include "exec/cpu-all.h"
622ed360	278
2b3e3cfe	279	static inline void cpu_get_tb_cpu_state(CPUM68KState env, target_ulong pc,
89fee74a	280	target_ulong cs_base, uint32_t flags)
6b917547 AL	281	{
	282	*pc = env->pc;
	283	*cs_base = 0;
	284	flags = (env->fpcr & M68K_FPCR_PREC) / Bit 6 */
	285	\| (env->sr & SR_S) /* Bit 13 */
	286	\| ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
	287	}
	288
e6e5906b	289	#endif