[qemu.git] / hw / misc / mst_fpga.c

/*
 * PXA270-based Intel Mainstone platforms.
 * FPGA driver
 *
 * Copyright (c) 2007 by Armin Kuster <[email protected]> or
 *                                    <[email protected]>
 *
 * This code is licensed under the GNU GPL v2.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */
#include "hw/hw.h"
#include "hw/sysbus.h"

/* Mainstone FPGA for extern irqs */
#define FPGA_GPIO_PIN	0
#define MST_NUM_IRQS	16
#define MST_LEDDAT1		0x10
#define MST_LEDDAT2		0x14
#define MST_LEDCTRL		0x40
#define MST_GPSWR		0x60
#define MST_MSCWR1		0x80
#define MST_MSCWR2		0x84
#define MST_MSCWR3		0x88
#define MST_MSCRD		0x90
#define MST_INTMSKENA	0xc0
#define MST_INTSETCLR	0xd0
#define MST_PCMCIA0		0xe0
#define MST_PCMCIA1		0xe4

#define MST_PCMCIAx_READY	(1 << 10)
#define MST_PCMCIAx_nCD		(1 << 5)

#define MST_PCMCIA_CD0_IRQ	9
#define MST_PCMCIA_CD1_IRQ	13

#define TYPE_MAINSTONE_FPGA "mainstone-fpga"
#define MAINSTONE_FPGA(obj) \
    OBJECT_CHECK(mst_irq_state, (obj), TYPE_MAINSTONE_FPGA)

typedef struct mst_irq_state{
    SysBusDevice parent_obj;

    MemoryRegion iomem;

    qemu_irq parent;

    uint32_t prev_level;
    uint32_t leddat1;
    uint32_t leddat2;
    uint32_t ledctrl;
    uint32_t gpswr;
    uint32_t mscwr1;
    uint32_t mscwr2;
    uint32_t mscwr3;
    uint32_t mscrd;
    uint32_t intmskena;
    uint32_t intsetclr;
    uint32_t pcmcia0;
    uint32_t pcmcia1;
}mst_irq_state;

static void
mst_fpga_set_irq(void *opaque, int irq, int level)
{
	mst_irq_state *s = (mst_irq_state *)opaque;
	uint32_t oldint = s->intsetclr & s->intmskena;

	if (level)
		s->prev_level |= 1u << irq;
	else
		s->prev_level &= ~(1u << irq);

	switch(irq) {
	case MST_PCMCIA_CD0_IRQ:
		if (level)
			s->pcmcia0 &= ~MST_PCMCIAx_nCD;
		else
			s->pcmcia0 |=  MST_PCMCIAx_nCD;
		break;
	case MST_PCMCIA_CD1_IRQ:
		if (level)
			s->pcmcia1 &= ~MST_PCMCIAx_nCD;
		else
			s->pcmcia1 |=  MST_PCMCIAx_nCD;
		break;
	}

	if ((s->intmskena & (1u << irq)) && level)
		s->intsetclr |= 1u << irq;

	if (oldint != (s->intsetclr & s->intmskena))
		qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
}


static uint64_t
mst_fpga_readb(void *opaque, hwaddr addr, unsigned size)
{
	mst_irq_state *s = (mst_irq_state *) opaque;

	switch (addr) {
	case MST_LEDDAT1:
		return s->leddat1;
	case MST_LEDDAT2:
		return s->leddat2;
	case MST_LEDCTRL:
		return s->ledctrl;
	case MST_GPSWR:
		return s->gpswr;
	case MST_MSCWR1:
		return s->mscwr1;
	case MST_MSCWR2:
		return s->mscwr2;
	case MST_MSCWR3:
		return s->mscwr3;
	case MST_MSCRD:
		return s->mscrd;
	case MST_INTMSKENA:
		return s->intmskena;
	case MST_INTSETCLR:
		return s->intsetclr;
	case MST_PCMCIA0:
		return s->pcmcia0;
	case MST_PCMCIA1:
		return s->pcmcia1;
	default:
		printf("Mainstone - mst_fpga_readb: Bad register offset "
			"0x" TARGET_FMT_plx "\n", addr);
	}
	return 0;
}

static void
mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
		unsigned size)
{
	mst_irq_state *s = (mst_irq_state *) opaque;
	value &= 0xffffffff;

	switch (addr) {
	case MST_LEDDAT1:
		s->leddat1 = value;
		break;
	case MST_LEDDAT2:
		s->leddat2 = value;
		break;
	case MST_LEDCTRL:
		s->ledctrl = value;
		break;
	case MST_GPSWR:
		s->gpswr = value;
		break;
	case MST_MSCWR1:
		s->mscwr1 = value;
		break;
	case MST_MSCWR2:
		s->mscwr2 = value;
		break;
	case MST_MSCWR3:
		s->mscwr3 = value;
		break;
	case MST_MSCRD:
		s->mscrd =  value;
		break;
	case MST_INTMSKENA:	/* Mask interrupt */
		s->intmskena = (value & 0xFEEFF);
		qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
		break;
	case MST_INTSETCLR:	/* clear or set interrupt */
		s->intsetclr = (value & 0xFEEFF);
		qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
		break;
		/* For PCMCIAx allow the to change only power and reset */
	case MST_PCMCIA0:
		s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f);
		break;
	case MST_PCMCIA1:
		s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f);
		break;
	default:
		printf("Mainstone - mst_fpga_writeb: Bad register offset "
			"0x" TARGET_FMT_plx "\n", addr);
	}
}

static const MemoryRegionOps mst_fpga_ops = {
	.read = mst_fpga_readb,
	.write = mst_fpga_writeb,
	.endianness = DEVICE_NATIVE_ENDIAN,
};

static int mst_fpga_post_load(void *opaque, int version_id)
{
	mst_irq_state *s = (mst_irq_state *) opaque;

	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
	return 0;
}

static int mst_fpga_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    mst_irq_state *s = MAINSTONE_FPGA(dev);

    s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
    s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;

    sysbus_init_irq(sbd, &s->parent);

    /* alloc the external 16 irqs */
    qdev_init_gpio_in(dev, mst_fpga_set_irq, MST_NUM_IRQS);

    memory_region_init_io(&s->iomem, OBJECT(s), &mst_fpga_ops, s,
                          "fpga", 0x00100000);
    sysbus_init_mmio(sbd, &s->iomem);
    return 0;
}

static VMStateDescription vmstate_mst_fpga_regs = {
	.name = "mainstone_fpga",
	.version_id = 0,
	.minimum_version_id = 0,
	.minimum_version_id_old = 0,
	.post_load = mst_fpga_post_load,
	.fields = (VMStateField []) {
		VMSTATE_UINT32(prev_level, mst_irq_state),
		VMSTATE_UINT32(leddat1, mst_irq_state),
		VMSTATE_UINT32(leddat2, mst_irq_state),
		VMSTATE_UINT32(ledctrl, mst_irq_state),
		VMSTATE_UINT32(gpswr, mst_irq_state),
		VMSTATE_UINT32(mscwr1, mst_irq_state),
		VMSTATE_UINT32(mscwr2, mst_irq_state),
		VMSTATE_UINT32(mscwr3, mst_irq_state),
		VMSTATE_UINT32(mscrd, mst_irq_state),
		VMSTATE_UINT32(intmskena, mst_irq_state),
		VMSTATE_UINT32(intsetclr, mst_irq_state),
		VMSTATE_UINT32(pcmcia0, mst_irq_state),
		VMSTATE_UINT32(pcmcia1, mst_irq_state),
		VMSTATE_END_OF_LIST(),
	},
};

static void mst_fpga_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = mst_fpga_init;
    dc->desc = "Mainstone II FPGA";
    dc->vmsd = &vmstate_mst_fpga_regs;
}

static const TypeInfo mst_fpga_info = {
    .name          = TYPE_MAINSTONE_FPGA,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(mst_irq_state),
    .class_init    = mst_fpga_class_init,
};

static void mst_fpga_register_types(void)
{
    type_register_static(&mst_fpga_info);
}

type_init(mst_fpga_register_types)
Commit	Line	Data
7233b355 TS	1	/*
	2	* PXA270-based Intel Mainstone platforms.
	3	* FPGA driver
	4	*
	5	* Copyright (c) 2007 by Armin Kuster <[email protected]> or
	6	* <[email protected]>
	7	*
	8	* This code is licensed under the GNU GPL v2.
6b620ca3 PB	9	*
	10	* Contributions after 2012-01-13 are licensed under the terms of the
	11	* GNU GPL, version 2 or (at your option) any later version.
7233b355	12	*/
83c9f4ca PB	13	#include "hw/hw.h"
83c9f4ca PB	14	#include "hw/sysbus.h"
7233b355 TS	15
	16	/* Mainstone FPGA for extern irqs */
	17	#define FPGA_GPIO_PIN 0
	18	#define MST_NUM_IRQS 16
7233b355 TS	19	#define MST_LEDDAT1 0x10
	20	#define MST_LEDDAT2 0x14
	21	#define MST_LEDCTRL 0x40
	22	#define MST_GPSWR 0x60
	23	#define MST_MSCWR1 0x80
	24	#define MST_MSCWR2 0x84
	25	#define MST_MSCWR3 0x88
	26	#define MST_MSCRD 0x90
	27	#define MST_INTMSKENA 0xc0
	28	#define MST_INTSETCLR 0xd0
	29	#define MST_PCMCIA0 0xe0
	30	#define MST_PCMCIA1 0xe4
	31
b651fc6f DES	32	#define MST_PCMCIAx_READY (1 << 10)
	33	#define MST_PCMCIAx_nCD (1 << 5)
	34
	35	#define MST_PCMCIA_CD0_IRQ 9
	36	#define MST_PCMCIA_CD1_IRQ 13
	37
5c0e12f5 AF	38	#define TYPE_MAINSTONE_FPGA "mainstone-fpga"
	39	#define MAINSTONE_FPGA(obj) \
	40	OBJECT_CHECK(mst_irq_state, (obj), TYPE_MAINSTONE_FPGA)
	41
7233b355	42	typedef struct mst_irq_state{
5c0e12f5 AF	43	SysBusDevice parent_obj;
	44
	45	MemoryRegion iomem;
	46
	47	qemu_irq parent;
	48
	49	uint32_t prev_level;
	50	uint32_t leddat1;
	51	uint32_t leddat2;
	52	uint32_t ledctrl;
	53	uint32_t gpswr;
	54	uint32_t mscwr1;
	55	uint32_t mscwr2;
	56	uint32_t mscwr3;
	57	uint32_t mscrd;
	58	uint32_t intmskena;
	59	uint32_t intsetclr;
	60	uint32_t pcmcia0;
	61	uint32_t pcmcia1;
7233b355 TS	62	}mst_irq_state;
7233b355 TS	63
7233b355 TS	64	static void
	65	mst_fpga_set_irq(void *opaque, int irq, int level)
	66	{
	67	mst_irq_state s = (mst_irq_state )opaque;
3e1dbc3b	68	uint32_t oldint = s->intsetclr & s->intmskena;
7233b355 TS	69
	70	if (level)
	71	s->prev_level \|= 1u << irq;
	72	else
	73	s->prev_level &= ~(1u << irq);
	74
b651fc6f DES	75	switch(irq) {
	76	case MST_PCMCIA_CD0_IRQ:
	77	if (level)
	78	s->pcmcia0 &= ~MST_PCMCIAx_nCD;
	79	else
	80	s->pcmcia0 \|= MST_PCMCIAx_nCD;
	81	break;
	82	case MST_PCMCIA_CD1_IRQ:
	83	if (level)
	84	s->pcmcia1 &= ~MST_PCMCIAx_nCD;
	85	else
	86	s->pcmcia1 \|= MST_PCMCIAx_nCD;
	87	break;
	88	}
	89
43d91709 DES	90	if ((s->intmskena & (1u << irq)) && level)
	91	s->intsetclr \|= 1u << irq;
	92
	93	if (oldint != (s->intsetclr & s->intmskena))
	94	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
7233b355 TS	95	}
	96
	97
b9441ebb	98	static uint64_t
a8170e5e	99	mst_fpga_readb(void *opaque, hwaddr addr, unsigned size)
7233b355 TS	100	{
7233b355 TS	101	mst_irq_state s = (mst_irq_state ) opaque;
7233b355 TS	102
	103	switch (addr) {
	104	case MST_LEDDAT1:
	105	return s->leddat1;
	106	case MST_LEDDAT2:
	107	return s->leddat2;
	108	case MST_LEDCTRL:
	109	return s->ledctrl;
	110	case MST_GPSWR:
	111	return s->gpswr;
	112	case MST_MSCWR1:
	113	return s->mscwr1;
	114	case MST_MSCWR2:
	115	return s->mscwr2;
	116	case MST_MSCWR3:
	117	return s->mscwr3;
	118	case MST_MSCRD:
	119	return s->mscrd;
	120	case MST_INTMSKENA:
	121	return s->intmskena;
	122	case MST_INTSETCLR:
	123	return s->intsetclr;
	124	case MST_PCMCIA0:
	125	return s->pcmcia0;
	126	case MST_PCMCIA1:
	127	return s->pcmcia1;
	128	default:
	129	printf("Mainstone - mst_fpga_readb: Bad register offset "
b2bedb21	130	"0x" TARGET_FMT_plx "\n", addr);
7233b355 TS	131	}
	132	return 0;
	133	}
	134
	135	static void
a8170e5e	136	mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
b9441ebb	137	unsigned size)
7233b355 TS	138	{
7233b355 TS	139	mst_irq_state s = (mst_irq_state ) opaque;
7233b355 TS	140	value &= 0xffffffff;
	141
	142	switch (addr) {
	143	case MST_LEDDAT1:
	144	s->leddat1 = value;
	145	break;
	146	case MST_LEDDAT2:
	147	s->leddat2 = value;
	148	break;
	149	case MST_LEDCTRL:
	150	s->ledctrl = value;
	151	break;
	152	case MST_GPSWR:
	153	s->gpswr = value;
	154	break;
	155	case MST_MSCWR1:
	156	s->mscwr1 = value;
	157	break;
	158	case MST_MSCWR2:
	159	s->mscwr2 = value;
	160	break;
	161	case MST_MSCWR3:
	162	s->mscwr3 = value;
	163	break;
	164	case MST_MSCRD:
	165	s->mscrd = value;
	166	break;
ff2712ba	167	case MST_INTMSKENA: /* Mask interrupt */
7233b355	168	s->intmskena = (value & 0xFEEFF);
43d91709	169	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
7233b355 TS	170	break;
	171	case MST_INTSETCLR: /* clear or set interrupt */
	172	s->intsetclr = (value & 0xFEEFF);
3e1dbc3b	173	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
7233b355	174	break;
b651fc6f	175	/* For PCMCIAx allow the to change only power and reset */
7233b355	176	case MST_PCMCIA0:
b651fc6f	177	s->pcmcia0 = (value & 0x1f) \| (s->pcmcia0 & ~0x1f);
7233b355 TS	178	break;
7233b355 TS	179	case MST_PCMCIA1:
b651fc6f	180	s->pcmcia1 = (value & 0x1f) \| (s->pcmcia1 & ~0x1f);
7233b355 TS	181	break;
	182	default:
	183	printf("Mainstone - mst_fpga_writeb: Bad register offset "
b2bedb21	184	"0x" TARGET_FMT_plx "\n", addr);
7233b355 TS	185	}
	186	}
	187
b9441ebb BC	188	static const MemoryRegionOps mst_fpga_ops = {
	189	.read = mst_fpga_readb,
	190	.write = mst_fpga_writeb,
	191	.endianness = DEVICE_NATIVE_ENDIAN,
7233b355	192	};
7233b355	193
cb380f61	194	static int mst_fpga_post_load(void *opaque, int version_id)
7233b355 TS	195	{
	196	mst_irq_state s = (mst_irq_state ) opaque;
	197
43d91709	198	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
7233b355 TS	199	return 0;
	200	}
	201
5c0e12f5	202	static int mst_fpga_init(SysBusDevice *sbd)
7233b355	203	{
5c0e12f5 AF	204	DeviceState *dev = DEVICE(sbd);
5c0e12f5 AF	205	mst_irq_state *s = MAINSTONE_FPGA(dev);
7233b355	206
5c0e12f5 AF	207	s->pcmcia0 = MST_PCMCIAx_READY \| MST_PCMCIAx_nCD;
5c0e12f5 AF	208	s->pcmcia1 = MST_PCMCIAx_READY \| MST_PCMCIAx_nCD;
b651fc6f	209
5c0e12f5	210	sysbus_init_irq(sbd, &s->parent);
7233b355	211
5c0e12f5 AF	212	/* alloc the external 16 irqs */
5c0e12f5 AF	213	qdev_init_gpio_in(dev, mst_fpga_set_irq, MST_NUM_IRQS);
7233b355	214
5c0e12f5 AF	215	memory_region_init_io(&s->iomem, OBJECT(s), &mst_fpga_ops, s,
	216	"fpga", 0x00100000);
	217	sysbus_init_mmio(sbd, &s->iomem);
	218	return 0;
cb380f61 DES	219	}
	220
	221	static VMStateDescription vmstate_mst_fpga_regs = {
	222	.name = "mainstone_fpga",
	223	.version_id = 0,
	224	.minimum_version_id = 0,
	225	.minimum_version_id_old = 0,
	226	.post_load = mst_fpga_post_load,
	227	.fields = (VMStateField []) {
	228	VMSTATE_UINT32(prev_level, mst_irq_state),
	229	VMSTATE_UINT32(leddat1, mst_irq_state),
	230	VMSTATE_UINT32(leddat2, mst_irq_state),
	231	VMSTATE_UINT32(ledctrl, mst_irq_state),
	232	VMSTATE_UINT32(gpswr, mst_irq_state),
	233	VMSTATE_UINT32(mscwr1, mst_irq_state),
	234	VMSTATE_UINT32(mscwr2, mst_irq_state),
	235	VMSTATE_UINT32(mscwr3, mst_irq_state),
	236	VMSTATE_UINT32(mscrd, mst_irq_state),
	237	VMSTATE_UINT32(intmskena, mst_irq_state),
	238	VMSTATE_UINT32(intsetclr, mst_irq_state),
	239	VMSTATE_UINT32(pcmcia0, mst_irq_state),
	240	VMSTATE_UINT32(pcmcia1, mst_irq_state),
	241	VMSTATE_END_OF_LIST(),
	242	},
	243	};
	244
999e12bb AL	245	static void mst_fpga_class_init(ObjectClass klass, void data)
999e12bb AL	246	{
39bffca2	247	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	248	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	249
	250	k->init = mst_fpga_init;
39bffca2 AL	251	dc->desc = "Mainstone II FPGA";
39bffca2 AL	252	dc->vmsd = &vmstate_mst_fpga_regs;
999e12bb AL	253	}
999e12bb AL	254
8c43a6f0	255	static const TypeInfo mst_fpga_info = {
5c0e12f5	256	.name = TYPE_MAINSTONE_FPGA,
39bffca2 AL	257	.parent = TYPE_SYS_BUS_DEVICE,
	258	.instance_size = sizeof(mst_irq_state),
	259	.class_init = mst_fpga_class_init,
cb380f61 DES	260	};
cb380f61 DES	261
83f7d43a	262	static void mst_fpga_register_types(void)
cb380f61	263	{
39bffca2	264	type_register_static(&mst_fpga_info);
7233b355	265	}
83f7d43a AF	266
83f7d43a AF	267	type_init(mst_fpga_register_types)