projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 7c23b892 AZ |
1 | /******************************************************************************* |
| 2 | ||
| 3 | Intel PRO/1000 Linux driver | |
| 4 | Copyright(c) 1999 - 2006 Intel Corporation. | |
| 5 | ||
| 6 | This program is free software; you can redistribute it and/or modify it | |
| 7 | under the terms and conditions of the GNU General Public License, | |
| 8 | version 2, as published by the Free Software Foundation. | |
| 9 | ||
| 10 | This program is distributed in the hope it will be useful, but WITHOUT | |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 13 | more details. | |
| 14 | ||
| 15 | You should have received a copy of the GNU General Public License along with | |
| 8167ee88 | 16 | this program; if not, see <http://www.gnu.org/licenses/>. |
| 7c23b892 AZ |
17 | |
| 18 | The full GNU General Public License is included in this distribution in | |
| 19 | the file called "COPYING". | |
| 20 | ||
| 21 | Contact Information: | |
| 22 | Linux NICS <[email protected]> | |
| 23 | e1000-devel Mailing List <[email protected]> | |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
| 25 | ||
| 26 | *******************************************************************************/ | |
| 27 | ||
| 28 | /* e1000_hw.h | |
| 29 | * Structures, enums, and macros for the MAC | |
| 30 | */ | |
| 31 | ||
| 121d0712 MA |
32 | #ifndef HW_E1000_REGS_H |
| 33 | #define HW_E1000_REGS_H | |
| 7c23b892 AZ |
34 | |
| 35 | /* PCI Device IDs */ | |
| 36 | #define E1000_DEV_ID_82542 0x1000 | |
| 37 | #define E1000_DEV_ID_82543GC_FIBER 0x1001 | |
| 38 | #define E1000_DEV_ID_82543GC_COPPER 0x1004 | |
| 39 | #define E1000_DEV_ID_82544EI_COPPER 0x1008 | |
| 40 | #define E1000_DEV_ID_82544EI_FIBER 0x1009 | |
| 41 | #define E1000_DEV_ID_82544GC_COPPER 0x100C | |
| 42 | #define E1000_DEV_ID_82544GC_LOM 0x100D | |
| 43 | #define E1000_DEV_ID_82540EM 0x100E | |
| 44 | #define E1000_DEV_ID_82540EM_LOM 0x1015 | |
| 45 | #define E1000_DEV_ID_82540EP_LOM 0x1016 | |
| 46 | #define E1000_DEV_ID_82540EP 0x1017 | |
| 47 | #define E1000_DEV_ID_82540EP_LP 0x101E | |
| 48 | #define E1000_DEV_ID_82545EM_COPPER 0x100F | |
| 49 | #define E1000_DEV_ID_82545EM_FIBER 0x1011 | |
| 50 | #define E1000_DEV_ID_82545GM_COPPER 0x1026 | |
| 51 | #define E1000_DEV_ID_82545GM_FIBER 0x1027 | |
| 52 | #define E1000_DEV_ID_82545GM_SERDES 0x1028 | |
| 53 | #define E1000_DEV_ID_82546EB_COPPER 0x1010 | |
| 54 | #define E1000_DEV_ID_82546EB_FIBER 0x1012 | |
| 55 | #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D | |
| 56 | #define E1000_DEV_ID_82541EI 0x1013 | |
| 57 | #define E1000_DEV_ID_82541EI_MOBILE 0x1018 | |
| 58 | #define E1000_DEV_ID_82541ER_LOM 0x1014 | |
| 59 | #define E1000_DEV_ID_82541ER 0x1078 | |
| 60 | #define E1000_DEV_ID_82547GI 0x1075 | |
| 61 | #define E1000_DEV_ID_82541GI 0x1076 | |
| 62 | #define E1000_DEV_ID_82541GI_MOBILE 0x1077 | |
| 63 | #define E1000_DEV_ID_82541GI_LF 0x107C | |
| 64 | #define E1000_DEV_ID_82546GB_COPPER 0x1079 | |
| 65 | #define E1000_DEV_ID_82546GB_FIBER 0x107A | |
| 66 | #define E1000_DEV_ID_82546GB_SERDES 0x107B | |
| 67 | #define E1000_DEV_ID_82546GB_PCIE 0x108A | |
| 68 | #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 | |
| 69 | #define E1000_DEV_ID_82547EI 0x1019 | |
| 70 | #define E1000_DEV_ID_82547EI_MOBILE 0x101A | |
| 71 | #define E1000_DEV_ID_82571EB_COPPER 0x105E | |
| 72 | #define E1000_DEV_ID_82571EB_FIBER 0x105F | |
| 73 | #define E1000_DEV_ID_82571EB_SERDES 0x1060 | |
| 74 | #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 | |
| 75 | #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 | |
| 76 | #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 | |
| 77 | #define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC | |
| 78 | #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 | |
| 79 | #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA | |
| 80 | #define E1000_DEV_ID_82572EI_COPPER 0x107D | |
| 81 | #define E1000_DEV_ID_82572EI_FIBER 0x107E | |
| 82 | #define E1000_DEV_ID_82572EI_SERDES 0x107F | |
| 83 | #define E1000_DEV_ID_82572EI 0x10B9 | |
| 84 | #define E1000_DEV_ID_82573E 0x108B | |
| 85 | #define E1000_DEV_ID_82573E_IAMT 0x108C | |
| 86 | #define E1000_DEV_ID_82573L 0x109A | |
| 06e7fa0a | 87 | #define E1000_DEV_ID_82574L 0x10D3 |
| 7c23b892 AZ |
88 | #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 |
| 89 | #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 | |
| 90 | #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 | |
| 91 | #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA | |
| 92 | #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB | |
| 93 | ||
| 94 | #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 | |
| 95 | #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A | |
| 96 | #define E1000_DEV_ID_ICH8_IGP_C 0x104B | |
| 97 | #define E1000_DEV_ID_ICH8_IFE 0x104C | |
| 98 | #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 | |
| 99 | #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 | |
| 100 | #define E1000_DEV_ID_ICH8_IGP_M 0x104D | |
| 101 | ||
| 8597f2e1 GS |
102 | /* Device Specific Register Defaults */ |
| 103 | #define E1000_PHY_ID2_82541x 0x380 | |
| 104 | #define E1000_PHY_ID2_82544x 0xC30 | |
| 105 | #define E1000_PHY_ID2_8254xx_DEFAULT 0xC20 /* 82540x, 82545x, and 82546x */ | |
| 106 | #define E1000_PHY_ID2_82573x 0xCC0 | |
| 06e7fa0a | 107 | #define E1000_PHY_ID2_82574x 0xCB1 |
| 8597f2e1 | 108 | |
| 7c23b892 AZ |
109 | /* Register Set. (82543, 82544) |
| 110 | * | |
| 111 | * Registers are defined to be 32 bits and should be accessed as 32 bit values. | |
| 112 | * These registers are physically located on the NIC, but are mapped into the | |
| 113 | * host memory address space. | |
| 114 | * | |
| 115 | * RW - register is both readable and writable | |
| 116 | * RO - register is read only | |
| 117 | * WO - register is write only | |
| 118 | * R/clr - register is read only and is cleared when read | |
| 119 | * A - register array | |
| 120 | */ | |
| 121 | #define E1000_CTRL 0x00000 /* Device Control - RW */ | |
| 122 | #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ | |
| 123 | #define E1000_STATUS 0x00008 /* Device Status - RO */ | |
| 124 | #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ | |
| 125 | #define E1000_EERD 0x00014 /* EEPROM Read - RW */ | |
| 126 | #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ | |
| 127 | #define E1000_FLA 0x0001C /* Flash Access - RW */ | |
| 128 | #define E1000_MDIC 0x00020 /* MDI Control - RW */ | |
| 129 | #define E1000_SCTL 0x00024 /* SerDes Control - RW */ | |
| 130 | #define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ | |
| 131 | #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ | |
| 132 | #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ | |
| 133 | #define E1000_FCT 0x00030 /* Flow Control Type - RW */ | |
| 134 | #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ | |
| 135 | #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ | |
| 136 | #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ | |
| 137 | #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ | |
| 138 | #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ | |
| 06e7fa0a | 139 | #define E1000_EIAC 0x000DC /* Ext. Interrupt Auto Clear - RW */ |
| 7c23b892 AZ |
140 | #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ |
| 141 | #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ | |
| 06e7fa0a DF |
142 | #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ |
| 143 | #define E1000_EITR 0x000E8 /* Extended Interrupt Throttling Rate - RW */ | |
| 7c23b892 AZ |
144 | #define E1000_RCTL 0x00100 /* RX Control - RW */ |
| 145 | #define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ | |
| 146 | #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ | |
| 147 | #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ | |
| 148 | #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ | |
| 149 | #define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ | |
| 150 | #define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ | |
| 151 | #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ | |
| 06e7fa0a | 152 | #define E1000_FCRTV 0x05F40 /* Flow Control Refresh Timer Value - RW */ |
| 7c23b892 AZ |
153 | #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ |
| 154 | #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ | |
| 155 | #define E1000_TCTL 0x00400 /* TX Control - RW */ | |
| 156 | #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ | |
| 157 | #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ | |
| 158 | #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ | |
| 159 | #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ | |
| 160 | #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ | |
| 161 | #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ | |
| 162 | #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ | |
| 163 | #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ | |
| 164 | #define FEXTNVM_SW_CONFIG 0x0001 | |
| 165 | #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ | |
| 72ea771c | 166 | #define E1000_PBM 0x10000 /* Packet Buffer Memory - RW */ |
| 20f3e863 | 167 | #define E1000_PBS 0x01008 /* Packet Buffer Size - RW */ |
| 7c23b892 | 168 | #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ |
| 06e7fa0a DF |
169 | #define E1000_EEMNGDATA 0x01014 /* MNG EEPROM Read/Write data */ |
| 170 | #define E1000_FLMNGCTL 0x01018 /* MNG Flash Control */ | |
| 171 | #define E1000_FLMNGDATA 0x0101C /* MNG FLASH Read data */ | |
| 172 | #define E1000_FLMNGCNT 0x01020 /* MNG FLASH Read Counter */ | |
| 7c23b892 AZ |
173 | #define E1000_FLASH_UPDATES 1000 |
| 174 | #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ | |
| 175 | #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ | |
| 176 | #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ | |
| 177 | #define E1000_FLSWCTL 0x01030 /* FLASH control register */ | |
| 178 | #define E1000_FLSWDATA 0x01034 /* FLASH data register */ | |
| 179 | #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ | |
| 180 | #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ | |
| 06e7fa0a | 181 | #define E1000_FLOL 0x01050 /* FEEP Auto Load */ |
| 7c23b892 AZ |
182 | #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ |
| 183 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ | |
| 06e7fa0a | 184 | #define E1000_FCRTL_A 0x00168 /* Alias to FCRTL */ |
| 7c23b892 | 185 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ |
| 06e7fa0a | 186 | #define E1000_FCRTH_A 0x00160 /* Alias to FCRTH */ |
| 7c23b892 AZ |
187 | #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ |
| 188 | #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ | |
| 189 | #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ | |
| 190 | #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ | |
| 191 | #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ | |
| 192 | #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ | |
| 193 | #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ | |
| 06e7fa0a | 194 | #define E1000_RDTR_A 0x00108 /* Alias to RDTR */ |
| 7c23b892 | 195 | #define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ |
| 06e7fa0a | 196 | #define E1000_RDBAL0_A 0x00110 /* Alias to RDBAL0 */ |
| 7c23b892 | 197 | #define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ |
| 06e7fa0a | 198 | #define E1000_RDBAH0_A 0x00114 /* Alias to RDBAH0 */ |
| 7c23b892 | 199 | #define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ |
| 06e7fa0a | 200 | #define E1000_RDLEN0_A 0x00118 /* Alias to RDLEN0 */ |
| 7c23b892 | 201 | #define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ |
| 06e7fa0a | 202 | #define E1000_RDH0_A 0x00120 /* Alias to RDH0 */ |
| 7c23b892 | 203 | #define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ |
| 06e7fa0a | 204 | #define E1000_RDT0_A 0x00128 /* Alias to RDT0 */ |
| 7c23b892 AZ |
205 | #define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ |
| 206 | #define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ | |
| 207 | #define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ | |
| 208 | #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ | |
| 209 | #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ | |
| 210 | #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ | |
| 211 | #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ | |
| 212 | #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ | |
| 06e7fa0a | 213 | #define E1000_POEMB 0x00F10 /* PHY OEM Bits Register - RW */ |
| 72ea771c | 214 | #define E1000_RDFH 0x02410 /* Receive Data FIFO Head Register - RW */ |
| 06e7fa0a | 215 | #define E1000_RDFH_A 0x08000 /* Alias to RDFH */ |
| 72ea771c | 216 | #define E1000_RDFT 0x02418 /* Receive Data FIFO Tail Register - RW */ |
| 06e7fa0a | 217 | #define E1000_RDFT_A 0x08008 /* Alias to RDFT */ |
| 72ea771c LB |
218 | #define E1000_RDFHS 0x02420 /* Receive Data FIFO Head Saved Register - RW */ |
| 219 | #define E1000_RDFTS 0x02428 /* Receive Data FIFO Tail Saved Register - RW */ | |
| 220 | #define E1000_RDFPC 0x02430 /* Receive Data FIFO Packet Count - RW */ | |
| 7c23b892 | 221 | #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ |
| 06e7fa0a | 222 | #define E1000_TDFH_A 0x08010 /* Alias to TDFH */ |
| 7c23b892 | 223 | #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ |
| 06e7fa0a | 224 | #define E1000_TDFT_A 0x08018 /* Alias to TDFT */ |
| 7c23b892 AZ |
225 | #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ |
| 226 | #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ | |
| 227 | #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ | |
| 228 | #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ | |
| 06e7fa0a | 229 | #define E1000_TDBAL_A 0x00420 /* Alias to TDBAL */ |
| 7c23b892 | 230 | #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ |
| 06e7fa0a | 231 | #define E1000_TDBAH_A 0x00424 /* Alias to TDBAH */ |
| 7c23b892 | 232 | #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ |
| 06e7fa0a | 233 | #define E1000_TDLEN_A 0x00428 /* Alias to TDLEN */ |
| 7c23b892 | 234 | #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ |
| 06e7fa0a | 235 | #define E1000_TDH_A 0x00430 /* Alias to TDH */ |
| 7c23b892 | 236 | #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ |
| 06e7fa0a | 237 | #define E1000_TDT_A 0x00438 /* Alias to TDT */ |
| 7c23b892 | 238 | #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ |
| 06e7fa0a | 239 | #define E1000_TIDV_A 0x00440 /* Alias to TIDV */ |
| 7c23b892 AZ |
240 | #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ |
| 241 | #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ | |
| 242 | #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ | |
| 243 | #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ | |
| 244 | #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ | |
| 245 | #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ | |
| 246 | #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ | |
| 247 | #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ | |
| 248 | #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ | |
| 249 | #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ | |
| 250 | #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ | |
| 251 | #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ | |
| 252 | #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ | |
| 253 | #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ | |
| 254 | #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ | |
| 255 | #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ | |
| 256 | #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ | |
| 257 | #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ | |
| 258 | #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ | |
| 259 | #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ | |
| 260 | #define E1000_COLC 0x04028 /* Collision Count - R/clr */ | |
| 261 | #define E1000_DC 0x04030 /* Defer Count - R/clr */ | |
| 262 | #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ | |
| 757704f1 | 263 | #define E1000_SEQEC 0x04038 /* Sequence Error Count - R/clr */ |
| 7c23b892 AZ |
264 | #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ |
| 265 | #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ | |
| 266 | #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ | |
| 267 | #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ | |
| 268 | #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ | |
| 269 | #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ | |
| 270 | #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ | |
| 271 | #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ | |
| 272 | #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ | |
| 273 | #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ | |
| 274 | #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ | |
| 275 | #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ | |
| 276 | #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ | |
| 277 | #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ | |
| 278 | #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ | |
| 279 | #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ | |
| 280 | #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ | |
| 281 | #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ | |
| 282 | #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ | |
| 283 | #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ | |
| 284 | #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ | |
| 285 | #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ | |
| 286 | #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ | |
| 287 | #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ | |
| 288 | #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ | |
| 289 | #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ | |
| 290 | #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ | |
| 291 | #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ | |
| 292 | #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ | |
| 293 | #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ | |
| 294 | #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ | |
| 295 | #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ | |
| 296 | #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ | |
| 297 | #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ | |
| 298 | #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ | |
| 299 | #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ | |
| 300 | #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ | |
| 301 | #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ | |
| 302 | #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ | |
| 303 | #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ | |
| 304 | #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ | |
| 305 | #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ | |
| 306 | #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ | |
| 307 | #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ | |
| 308 | #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ | |
| 309 | #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ | |
| 310 | #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ | |
| 311 | #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ | |
| 312 | #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ | |
| 313 | #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ | |
| 314 | #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ | |
| 315 | #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ | |
| 316 | #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ | |
| 317 | #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ | |
| 318 | #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ | |
| 319 | #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ | |
| 06e7fa0a DF |
320 | #define E1000_MAVTV0 0x05010 /* Management VLAN TAG Value 0 */ |
| 321 | #define E1000_MAVTV1 0x05014 /* Management VLAN TAG Value 1 */ | |
| 322 | #define E1000_MAVTV2 0x05018 /* Management VLAN TAG Value 2 */ | |
| 323 | #define E1000_MAVTV3 0x0501c /* Management VLAN TAG Value 3 */ | |
| 7c23b892 AZ |
324 | #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ |
| 325 | #define E1000_RA 0x05400 /* Receive Address - RW Array */ | |
| 06e7fa0a | 326 | #define E1000_RA_A 0x00040 /* Alias to RA */ |
| 7c23b892 | 327 | #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ |
| 06e7fa0a | 328 | #define E1000_VFTA_A 0x00600 /* Alias to VFTA */ |
| 7c23b892 AZ |
329 | #define E1000_WUC 0x05800 /* Wakeup Control - RW */ |
| 330 | #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ | |
| 331 | #define E1000_WUS 0x05810 /* Wakeup Status - RO */ | |
| 332 | #define E1000_MANC 0x05820 /* Management Control - RW */ | |
| 333 | #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ | |
| 334 | #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ | |
| 335 | #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ | |
| 336 | #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ | |
| 337 | #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ | |
| 06e7fa0a DF |
338 | #define E1000_MFUTP01 0x05828 /* Management Flex UDP/TCP Ports 0/1 - RW */ |
| 339 | #define E1000_MFUTP23 0x05830 /* Management Flex UDP/TCP Ports 2/3 - RW */ | |
| 340 | #define E1000_MFVAL 0x05824 /* Manageability Filters Valid - RW */ | |
| 341 | #define E1000_MDEF 0x05890 /* Manageability Decision Filters - RW Array */ | |
| 7c23b892 AZ |
342 | #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ |
| 343 | #define E1000_HOST_IF 0x08800 /* Host Interface */ | |
| 344 | #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ | |
| 06e7fa0a | 345 | #define E1000_FTFT 0x09400 /* Flexible TCO Filter Table - RW Array */ |
| 7c23b892 AZ |
346 | #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ |
| 347 | ||
| 348 | #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ | |
| 06e7fa0a DF |
349 | #define E1000_MDPHYA 0x0003C /* PHY address - RW */ |
| 350 | #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ | |
| 7c23b892 AZ |
351 | #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ |
| 352 | ||
| 353 | #define E1000_GCR 0x05B00 /* PCI-Ex Control */ | |
| 06e7fa0a | 354 | #define E1000_FUNCTAG 0x05B08 /* Function-Tag Register */ |
| 7c23b892 AZ |
355 | #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ |
| 356 | #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ | |
| 357 | #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ | |
| 358 | #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ | |
| 06e7fa0a DF |
359 | #define E1000_GSCN_0 0x05B20 /* 3GIO Statistic Counter Register #0 */ |
| 360 | #define E1000_GSCN_1 0x05B24 /* 3GIO Statistic Counter Register #1 */ | |
| 361 | #define E1000_GSCN_2 0x05B28 /* 3GIO Statistic Counter Register #2 */ | |
| 362 | #define E1000_GSCN_3 0x05B2C /* 3GIO Statistic Counter Register #3 */ | |
| 7c23b892 AZ |
363 | #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ |
| 364 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ | |
| 06e7fa0a | 365 | #define E1000_GCR2 0x05B64 /* 3GIO Control Register 2 */ |
| 7c23b892 | 366 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ |
| 06e7fa0a | 367 | #define E1000_PBACLR 0x05B68 /* MSI-X PBA Clear */ |
| 7c23b892 AZ |
368 | #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ |
| 369 | #define E1000_HICR 0x08F00 /* Host Inteface Control */ | |
| 370 | ||
| 06e7fa0a DF |
371 | #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ |
| 372 | #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ | |
| 373 | #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ | |
| 374 | #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ | |
| 375 | #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ | |
| 376 | #define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ | |
| 377 | #define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ | |
| 378 | #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ | |
| 379 | #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ | |
| 380 | #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ | |
| 381 | #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ | |
| 382 | #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ | |
| 383 | #define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */ | |
| 384 | #define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */ | |
| 385 | #define E1000_TIMADJL 0x0B60C /* Time Adjustment Offset register Low - RW */ | |
| 386 | #define E1000_TIMADJH 0x0B610 /* Time Adjustment Offset register High - RW */ | |
| 387 | #define E1000_RXCFGL 0x0B634 /* RX Ethertype and Message Type - RW*/ | |
| 388 | ||
| 7c23b892 AZ |
389 | /* RSS registers */ |
| 390 | #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ | |
| 391 | #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ | |
| 392 | #define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ | |
| 393 | #define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ | |
| 394 | #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ | |
| 395 | #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ | |
| 396 | ||
| 06e7fa0a DF |
397 | #define E1000_MRQC_ENABLED(mrqc) (((mrqc) & (BIT(0) | BIT(1))) == BIT(0)) |
| 398 | ||
| 399 | #define E1000_RETA_IDX(hash) ((hash) & (BIT(7) - 1)) | |
| 400 | #define E1000_RETA_VAL(reta, hash) (((uint8_t *)(reta))[E1000_RETA_IDX(hash)]) | |
| 401 | #define E1000_RSS_QUEUE(reta, hash) ((E1000_RETA_VAL(reta, hash) & BIT(7)) >> 7) | |
| 402 | ||
| 403 | #define E1000_MRQC_EN_TCPIPV4(mrqc) ((mrqc) & BIT(16)) | |
| 404 | #define E1000_MRQC_EN_IPV4(mrqc) ((mrqc) & BIT(17)) | |
| 405 | #define E1000_MRQC_EN_TCPIPV6(mrqc) ((mrqc) & BIT(18)) | |
| 406 | #define E1000_MRQC_EN_IPV6EX(mrqc) ((mrqc) & BIT(19)) | |
| 407 | #define E1000_MRQC_EN_IPV6(mrqc) ((mrqc) & BIT(20)) | |
| 408 | ||
| 409 | #define E1000_MRQ_RSS_TYPE_NONE (0) | |
| 410 | #define E1000_MRQ_RSS_TYPE_IPV4TCP (1) | |
| 411 | #define E1000_MRQ_RSS_TYPE_IPV4 (2) | |
| 412 | #define E1000_MRQ_RSS_TYPE_IPV6TCP (3) | |
| 413 | #define E1000_MRQ_RSS_TYPE_IPV6EX (4) | |
| 414 | #define E1000_MRQ_RSS_TYPE_IPV6 (5) | |
| 415 | ||
| 416 | #define E1000_ICR_ASSERTED BIT(31) | |
| 417 | #define E1000_EIAC_MASK 0x01F00000 | |
| 418 | ||
| 6f3fbe4e DF |
419 | /* [TR]DBAL and [TR]DLEN masks */ |
| 420 | #define E1000_XDBAL_MASK (~(BIT(4) - 1)) | |
| 421 | #define E1000_XDLEN_MASK ((BIT(20) - 1) & (~(BIT(7) - 1))) | |
| 422 | ||
| 06e7fa0a DF |
423 | /* IVAR register parsing helpers */ |
| 424 | #define E1000_IVAR_INT_ALLOC_VALID (0x8) | |
| 425 | ||
| 426 | #define E1000_IVAR_RXQ0_SHIFT (0) | |
| 427 | #define E1000_IVAR_RXQ1_SHIFT (4) | |
| 428 | #define E1000_IVAR_TXQ0_SHIFT (8) | |
| 429 | #define E1000_IVAR_TXQ1_SHIFT (12) | |
| 430 | #define E1000_IVAR_OTHER_SHIFT (16) | |
| 431 | ||
| 432 | #define E1000_IVAR_ENTRY_MASK (0xF) | |
| 433 | #define E1000_IVAR_ENTRY_VALID_MASK E1000_IVAR_INT_ALLOC_VALID | |
| 434 | #define E1000_IVAR_ENTRY_VEC_MASK (0x7) | |
| 435 | ||
| 436 | #define E1000_IVAR_RXQ0(x) ((x) >> E1000_IVAR_RXQ0_SHIFT) | |
| 437 | #define E1000_IVAR_RXQ1(x) ((x) >> E1000_IVAR_RXQ1_SHIFT) | |
| 438 | #define E1000_IVAR_TXQ0(x) ((x) >> E1000_IVAR_TXQ0_SHIFT) | |
| 439 | #define E1000_IVAR_TXQ1(x) ((x) >> E1000_IVAR_TXQ1_SHIFT) | |
| 440 | #define E1000_IVAR_OTHER(x) ((x) >> E1000_IVAR_OTHER_SHIFT) | |
| 441 | ||
| 442 | #define E1000_IVAR_ENTRY_VALID(x) ((x) & E1000_IVAR_ENTRY_VALID_MASK) | |
| 443 | #define E1000_IVAR_ENTRY_VEC(x) ((x) & E1000_IVAR_ENTRY_VEC_MASK) | |
| 444 | ||
| 445 | #define E1000_IVAR_TX_INT_EVERY_WB BIT(31) | |
| 446 | ||
| 447 | /* RFCTL register bits */ | |
| 448 | #define E1000_RFCTL_ISCSI_DIS 0x00000001 | |
| 449 | #define E1000_RFCTL_NFSW_DIS 0x00000040 | |
| 450 | #define E1000_RFCTL_NFSR_DIS 0x00000080 | |
| 451 | #define E1000_RFCTL_IPV6_DIS 0x00000400 | |
| 452 | #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 | |
| 453 | #define E1000_RFCTL_ACK_DIS 0x00001000 | |
| 454 | #define E1000_RFCTL_ACK_DATA_DIS 0x00002000 | |
| 455 | #define E1000_RFCTL_IPFRSP_DIS 0x00004000 | |
| 456 | #define E1000_RFCTL_EXTEN 0x00008000 | |
| 457 | #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 | |
| 458 | #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 | |
| 459 | ||
| 460 | /* PSRCTL parsing */ | |
| 461 | #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F | |
| 462 | #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 | |
| 463 | #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 | |
| 464 | #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 | |
| 465 | ||
| 466 | #define E1000_PSRCTL_BSIZE0_SHIFT 0 | |
| 467 | #define E1000_PSRCTL_BSIZE1_SHIFT 8 | |
| 468 | #define E1000_PSRCTL_BSIZE2_SHIFT 16 | |
| 469 | #define E1000_PSRCTL_BSIZE3_SHIFT 24 | |
| 470 | ||
| 471 | #define E1000_PSRCTL_BUFFS_PER_DESC 4 | |
| 472 | ||
| 473 | /* TARC* parsing */ | |
| 474 | #define E1000_TARC_ENABLE BIT(10) | |
| 475 | ||
| 7c23b892 AZ |
476 | /* PHY 1000 MII Register/Bit Definitions */ |
| 477 | /* PHY Registers defined by IEEE */ | |
| 478 | #define PHY_CTRL 0x00 /* Control Register */ | |
| 479 | #define PHY_STATUS 0x01 /* Status Regiser */ | |
| 480 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ | |
| 481 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ | |
| 482 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ | |
| 483 | #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ | |
| 484 | #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ | |
| 485 | #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ | |
| 486 | #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ | |
| 487 | #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ | |
| 488 | #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ | |
| 489 | #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ | |
| 490 | ||
| 06e7fa0a DF |
491 | /* 82574-specific registers */ |
| 492 | #define PHY_COPPER_CTRL1 0x10 /* Copper Specific Control Register 1 */ | |
| 493 | #define PHY_COPPER_STAT1 0x11 /* Copper Specific Status Register 1 */ | |
| 494 | #define PHY_COPPER_INT_ENABLE 0x12 /* Interrupt Enable Register */ | |
| 495 | #define PHY_COPPER_STAT2 0x13 /* Copper Specific Status Register 2 */ | |
| 496 | #define PHY_COPPER_CTRL3 0x14 /* Copper Specific Control Register 3 */ | |
| 497 | #define PHY_COPPER_CTRL2 0x1A /* Copper Specific Control Register 2 */ | |
| 498 | #define PHY_RX_ERR_CNTR 0x15 /* Receive Error Counter */ | |
| 499 | #define PHY_PAGE 0x16 /* Page Address (Any page) */ | |
| 500 | #define PHY_OEM_BITS 0x19 /* OEM Bits (Page 0) */ | |
| 501 | #define PHY_BIAS_1 0x1d /* Bias Setting Register */ | |
| 502 | #define PHY_BIAS_2 0x1e /* Bias Setting Register */ | |
| 503 | ||
| 504 | /* 82574-specific registers - page 2 */ | |
| 505 | #define PHY_MAC_CTRL1 0x10 /* MAC Specific Control Register 1 */ | |
| 506 | #define PHY_MAC_INT_ENABLE 0x12 /* MAC Interrupt Enable Register */ | |
| 507 | #define PHY_MAC_STAT 0x13 /* MAC Specific Status Register */ | |
| 508 | #define PHY_MAC_CTRL2 0x15 /* MAC Specific Control Register 2 */ | |
| 509 | ||
| 510 | /* 82574-specific registers - page 3 */ | |
| 511 | #define PHY_LED_03_FUNC_CTRL1 0x10 /* LED[3:0] Function Control */ | |
| 512 | #define PHY_LED_03_POL_CTRL 0x11 /* LED[3:0] Polarity Control */ | |
| 513 | #define PHY_LED_TIMER_CTRL 0x12 /* LED Timer Control */ | |
| 514 | #define PHY_LED_45_CTRL 0x13 /* LED[5:4] Function Control and Polarity */ | |
| 515 | ||
| 516 | /* 82574-specific registers - page 5 */ | |
| 517 | #define PHY_1000T_SKEW 0x14 /* 1000 BASE - T Pair Skew Register */ | |
| 518 | #define PHY_1000T_SWAP 0x15 /* 1000 BASE - T Pair Swap and Polarity */ | |
| 519 | ||
| 520 | /* 82574-specific registers - page 6 */ | |
| 521 | #define PHY_CRC_COUNTERS 0x11 /* CRC Counters */ | |
| 522 | ||
| 523 | #define PHY_PAGE_RW_MASK 0x7F /* R/W part of page address register */ | |
| 524 | ||
| 7c23b892 AZ |
525 | #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ |
| 526 | #define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ | |
| 527 | ||
| 528 | /* M88E1000 Specific Registers */ | |
| 529 | #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ | |
| 530 | #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ | |
| 531 | #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ | |
| 532 | #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ | |
| 533 | #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ | |
| 534 | #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ | |
| 535 | ||
| 536 | #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ | |
| 537 | #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ | |
| 538 | #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ | |
| 539 | #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ | |
| 540 | #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ | |
| 541 | ||
| 2e54cc21 JW |
542 | /* PHY Control Register */ |
| 543 | #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ | |
| 544 | #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ | |
| 545 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ | |
| 546 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ | |
| 547 | #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ | |
| 548 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ | |
| 549 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ | |
| 550 | #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ | |
| 551 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ | |
| 552 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ | |
| 553 | ||
| d4044c2a BM |
554 | /* PHY Status Register */ |
| 555 | #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ | |
| 556 | #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ | |
| 557 | #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ | |
| 558 | #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ | |
| 559 | #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ | |
| 560 | #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ | |
| 561 | #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ | |
| 562 | #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ | |
| 563 | #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ | |
| 564 | #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ | |
| 565 | #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ | |
| 566 | #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ | |
| 567 | #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ | |
| 568 | #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ | |
| 569 | #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ | |
| 570 | ||
| 6883b591 GS |
571 | /* PHY Link Partner Ability Register */ |
| 572 | #define MII_LPAR_LPACK 0x4000 /* Acked by link partner */ | |
| 573 | ||
| 7c23b892 AZ |
574 | /* Interrupt Cause Read */ |
| 575 | #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ | |
| 576 | #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ | |
| 577 | #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ | |
| 578 | #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ | |
| 579 | #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ | |
| 580 | #define E1000_ICR_RXO 0x00000040 /* rx overrun */ | |
| 581 | #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ | |
| 582 | #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ | |
| 583 | #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ | |
| 584 | #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ | |
| 585 | #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ | |
| 586 | #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ | |
| 587 | #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ | |
| 588 | #define E1000_ICR_TXD_LOW 0x00008000 | |
| 589 | #define E1000_ICR_SRPD 0x00010000 | |
| 590 | #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ | |
| 591 | #define E1000_ICR_MNG 0x00040000 /* Manageability event */ | |
| 592 | #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ | |
| 593 | #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ | |
| 594 | #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ | |
| 595 | #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ | |
| 596 | #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ | |
| 597 | #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ | |
| 598 | #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ | |
| 599 | #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ | |
| 600 | #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ | |
| 601 | #define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ | |
| 602 | #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ | |
| 603 | #define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ | |
| 06e7fa0a DF |
604 | #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ |
| 605 | #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ | |
| 606 | #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ | |
| 607 | #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ | |
| 608 | #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ | |
| 609 | ||
| 610 | #define E1000_ICR_OTHER_CAUSES (E1000_ICR_LSC | \ | |
| 611 | E1000_ICR_RXO | \ | |
| 612 | E1000_ICR_MDAC | \ | |
| 613 | E1000_ICR_SRPD | \ | |
| 614 | E1000_ICR_ACK | \ | |
| 615 | E1000_ICR_MNG) | |
| 7c23b892 AZ |
616 | |
| 617 | /* Interrupt Cause Set */ | |
| 618 | #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | |
| 619 | #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ | |
| 620 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ | |
| 621 | #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ | |
| 622 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | |
| 623 | #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ | |
| 624 | #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | |
| 625 | #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ | |
| 626 | #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ | |
| 627 | #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ | |
| 628 | #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ | |
| 629 | #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ | |
| 630 | #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ | |
| 631 | #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW | |
| 632 | #define E1000_ICS_SRPD E1000_ICR_SRPD | |
| 633 | #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ | |
| 634 | #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ | |
| 635 | #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ | |
| 636 | #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ | |
| 637 | #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ | |
| 638 | #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ | |
| 639 | #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ | |
| 640 | #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ | |
| 641 | #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ | |
| 642 | #define E1000_ICS_DSW E1000_ICR_DSW | |
| 643 | #define E1000_ICS_PHYINT E1000_ICR_PHYINT | |
| 644 | #define E1000_ICS_EPRST E1000_ICR_EPRST | |
| 645 | ||
| 646 | /* Interrupt Mask Set */ | |
| 647 | #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | |
| 648 | #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ | |
| 649 | #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ | |
| 650 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ | |
| 651 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | |
| 652 | #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ | |
| 653 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | |
| 654 | #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ | |
| 655 | #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ | |
| 656 | #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ | |
| 657 | #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ | |
| 658 | #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ | |
| 659 | #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ | |
| 660 | #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW | |
| 661 | #define E1000_IMS_SRPD E1000_ICR_SRPD | |
| 662 | #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ | |
| 663 | #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ | |
| 06e7fa0a DF |
664 | #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 |
| 665 | #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 | |
| 666 | #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 | |
| 667 | #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 | |
| 668 | #define E1000_IMS_OTHER E1000_ICR_OTHER | |
| 7c23b892 AZ |
669 | #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ |
| 670 | #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ | |
| 671 | #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ | |
| 672 | #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ | |
| 673 | #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ | |
| 674 | #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ | |
| 675 | #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ | |
| 676 | #define E1000_IMS_DSW E1000_ICR_DSW | |
| 677 | #define E1000_IMS_PHYINT E1000_ICR_PHYINT | |
| 678 | #define E1000_IMS_EPRST E1000_ICR_EPRST | |
| 679 | ||
| 680 | /* Interrupt Mask Clear */ | |
| 681 | #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | |
| 682 | #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ | |
| 683 | #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ | |
| 684 | #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ | |
| 685 | #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | |
| 686 | #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ | |
| 687 | #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | |
| 688 | #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ | |
| 689 | #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ | |
| 690 | #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ | |
| 691 | #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ | |
| 692 | #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ | |
| 693 | #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ | |
| 694 | #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW | |
| 695 | #define E1000_IMC_SRPD E1000_ICR_SRPD | |
| 696 | #define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ | |
| 697 | #define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ | |
| 698 | #define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ | |
| 699 | #define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ | |
| 700 | #define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ | |
| 701 | #define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ | |
| 702 | #define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ | |
| 703 | #define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ | |
| 704 | #define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ | |
| 705 | #define E1000_IMC_DSW E1000_ICR_DSW | |
| 706 | #define E1000_IMC_PHYINT E1000_ICR_PHYINT | |
| 707 | #define E1000_IMC_EPRST E1000_ICR_EPRST | |
| 708 | ||
| 709 | /* Receive Control */ | |
| 710 | #define E1000_RCTL_RST 0x00000001 /* Software reset */ | |
| 711 | #define E1000_RCTL_EN 0x00000002 /* enable */ | |
| 712 | #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ | |
| 713 | #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ | |
| 714 | #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ | |
| 715 | #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ | |
| 716 | #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ | |
| 717 | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ | |
| 718 | #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ | |
| 719 | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ | |
| 720 | #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ | |
| 721 | #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ | |
| 722 | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ | |
| 723 | #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ | |
| 724 | #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ | |
| 725 | #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ | |
| 726 | #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ | |
| 727 | #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ | |
| 728 | #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ | |
| 729 | #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ | |
| 730 | #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ | |
| 731 | #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ | |
| 732 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ | |
| 733 | #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ | |
| 734 | #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ | |
| 735 | #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ | |
| 736 | #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ | |
| 737 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ | |
| 738 | #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ | |
| 739 | #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ | |
| 740 | #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ | |
| 741 | #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ | |
| 742 | #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ | |
| 743 | #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ | |
| 744 | #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ | |
| 745 | #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ | |
| 746 | #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ | |
| 747 | #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ | |
| 748 | #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ | |
| 749 | #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ | |
| 750 | ||
| 751 | ||
| 752 | #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ | |
| 753 | #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ | |
| 754 | #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ | |
| 457044d1 | 755 | #define E1000_EEPROM_RW_REG_DONE 0x10 /* Offset to READ/WRITE done bit */ |
| 7c23b892 | 756 | #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ |
| 457044d1 | 757 | #define E1000_EEPROM_RW_ADDR_SHIFT 8 /* Shift to the address bits */ |
| 7c23b892 AZ |
758 | #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ |
| 759 | #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ | |
| 06e7fa0a DF |
760 | |
| 761 | /* 82574 EERD/EEWR registers layout */ | |
| 762 | #define E1000_EERW_START BIT(0) | |
| 763 | #define E1000_EERW_DONE BIT(1) | |
| 764 | #define E1000_EERW_ADDR_SHIFT 2 | |
| 765 | #define E1000_EERW_ADDR_MASK ((1L << 14) - 1) | |
| 766 | #define E1000_EERW_DATA_SHIFT 16 | |
| 767 | #define E1000_EERW_DATA_MASK ((1L << 16) - 1) | |
| 768 | ||
| 7c23b892 AZ |
769 | /* Register Bit Masks */ |
| 770 | /* Device Control */ | |
| 771 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ | |
| 772 | #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ | |
| 773 | #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ | |
| 774 | #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ | |
| 775 | #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ | |
| 776 | #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ | |
| 777 | #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ | |
| 778 | #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ | |
| 779 | #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ | |
| 780 | #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ | |
| 781 | #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ | |
| 782 | #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ | |
| 783 | #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ | |
| 784 | #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ | |
| 785 | #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ | |
| 786 | #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ | |
| 787 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ | |
| 788 | #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ | |
| 789 | #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ | |
| 790 | #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ | |
| 06e7fa0a DF |
791 | #define E1000_CTRL_SPD_SHIFT 8 /* Speed Select Shift */ |
| 792 | ||
| 793 | #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* auto speed detection check */ | |
| 794 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* EEPROM reset */ | |
| 7c23b892 | 795 | #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ |
| 06e7fa0a DF |
796 | #define E1000_CTRL_EXT_EIAME 0x01000000 |
| 797 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ | |
| 798 | #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ | |
| 799 | #define E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA 0x20000000 | |
| 800 | #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ | |
| 801 | ||
| 7c23b892 AZ |
802 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ |
| 803 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ | |
| 804 | #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ | |
| 805 | #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ | |
| 806 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ | |
| 807 | #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ | |
| 808 | #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ | |
| 809 | #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ | |
| 06e7fa0a | 810 | #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ |
| 7c23b892 AZ |
811 | #define E1000_CTRL_RST 0x04000000 /* Global reset */ |
| 812 | #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ | |
| 813 | #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ | |
| 814 | #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ | |
| 815 | #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ | |
| 816 | #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ | |
| 817 | #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ | |
| 818 | ||
| 819 | /* Device Status */ | |
| 820 | #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ | |
| 821 | #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ | |
| 822 | #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ | |
| 823 | #define E1000_STATUS_FUNC_SHIFT 2 | |
| 824 | #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ | |
| 825 | #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ | |
| 826 | #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ | |
| 827 | #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ | |
| 828 | #define E1000_STATUS_SPEED_MASK 0x000000C0 | |
| 829 | #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ | |
| 830 | #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ | |
| 831 | #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ | |
| 832 | #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion | |
| 833 | by EEPROM/Flash */ | |
| 834 | #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ | |
| 06e7fa0a DF |
835 | #define E1000_STATUS_ASDV_10 0x00000000 /* ASDV 10Mb */ |
| 836 | #define E1000_STATUS_ASDV_100 0x00000100 /* ASDV 100Mb */ | |
| 837 | #define E1000_STATUS_ASDV_1000 0x00000200 /* ASDV 1Gb */ | |
| 7c23b892 AZ |
838 | #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ |
| 839 | #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ | |
| 840 | #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ | |
| 06e7fa0a | 841 | #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ |
| 7c23b892 AZ |
842 | #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ |
| 843 | #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ | |
| 844 | #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ | |
| 845 | #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ | |
| 846 | #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ | |
| 847 | #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ | |
| 848 | #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ | |
| 849 | #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ | |
| 850 | #define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ | |
| 851 | #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ | |
| 852 | #define E1000_STATUS_FUSE_8 0x04000000 | |
| 853 | #define E1000_STATUS_FUSE_9 0x08000000 | |
| 854 | #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ | |
| 855 | #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ | |
| 06e7fa0a DF |
856 | #define E1000_STATUS_SPEED_SHIFT 6 |
| 857 | #define E1000_STATUS_ASDV_SHIFT 8 | |
| 7c23b892 AZ |
858 | |
| 859 | /* EEPROM/Flash Control */ | |
| 860 | #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ | |
| 861 | #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ | |
| 862 | #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ | |
| 863 | #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ | |
| 864 | #define E1000_EECD_FWE_MASK 0x00000030 | |
| 865 | #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ | |
| 866 | #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ | |
| 867 | #define E1000_EECD_FWE_SHIFT 4 | |
| 868 | #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ | |
| 869 | #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ | |
| 870 | #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ | |
| 871 | #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ | |
| 872 | #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type | |
| 873 | * (0-small, 1-large) */ | |
| 874 | #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ | |
| 875 | #ifndef E1000_EEPROM_GRANT_ATTEMPTS | |
| 876 | #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ | |
| 877 | #endif | |
| 878 | #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ | |
| 879 | #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ | |
| 880 | #define E1000_EECD_SIZE_EX_SHIFT 11 | |
| 881 | #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ | |
| 882 | #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ | |
| 883 | #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ | |
| 884 | #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ | |
| 885 | #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ | |
| 886 | #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ | |
| 887 | #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ | |
| 06e7fa0a DF |
888 | |
| 889 | ||
| 7c23b892 AZ |
890 | #define E1000_EECD_SECVAL_SHIFT 22 |
| 891 | #define E1000_STM_OPCODE 0xDB00 | |
| 892 | #define E1000_HICR_FW_RESET 0xC0 | |
| 893 | ||
| 894 | #define E1000_SHADOW_RAM_WORDS 2048 | |
| 895 | #define E1000_ICH_NVM_SIG_WORD 0x13 | |
| 896 | #define E1000_ICH_NVM_SIG_MASK 0xC0 | |
| 897 | ||
| 898 | /* MDI Control */ | |
| 899 | #define E1000_MDIC_DATA_MASK 0x0000FFFF | |
| 900 | #define E1000_MDIC_REG_MASK 0x001F0000 | |
| 901 | #define E1000_MDIC_REG_SHIFT 16 | |
| 902 | #define E1000_MDIC_PHY_MASK 0x03E00000 | |
| 903 | #define E1000_MDIC_PHY_SHIFT 21 | |
| 904 | #define E1000_MDIC_OP_WRITE 0x04000000 | |
| 905 | #define E1000_MDIC_OP_READ 0x08000000 | |
| 906 | #define E1000_MDIC_READY 0x10000000 | |
| 907 | #define E1000_MDIC_INT_EN 0x20000000 | |
| 908 | #define E1000_MDIC_ERROR 0x40000000 | |
| 909 | ||
| 06e7fa0a DF |
910 | /* Rx Interrupt Delay Timer */ |
| 911 | #define E1000_RDTR_FPD BIT(31) | |
| 912 | ||
| 913 | /* Tx Interrupt Delay Timer */ | |
| 914 | #define E1000_TIDV_FPD BIT(31) | |
| 915 | ||
| 916 | /* Delay increments in nanoseconds for delayed interrupts registers */ | |
| 917 | #define E1000_INTR_DELAY_NS_RES (1024) | |
| 918 | ||
| 919 | /* Delay increments in nanoseconds for interrupt throttling registers */ | |
| 920 | #define E1000_INTR_THROTTLING_NS_RES (256) | |
| 921 | ||
| 7c23b892 AZ |
922 | /* EEPROM Commands - Microwire */ |
| 923 | #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ | |
| 924 | #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ | |
| 925 | #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ | |
| 926 | #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ | |
| 927 | #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ | |
| 928 | ||
| 929 | /* EEPROM Word Offsets */ | |
| 930 | #define EEPROM_COMPAT 0x0003 | |
| 931 | #define EEPROM_ID_LED_SETTINGS 0x0004 | |
| 932 | #define EEPROM_VERSION 0x0005 | |
| 933 | #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ | |
| 934 | #define EEPROM_PHY_CLASS_WORD 0x0007 | |
| 935 | #define EEPROM_INIT_CONTROL1_REG 0x000A | |
| 936 | #define EEPROM_INIT_CONTROL2_REG 0x000F | |
| 937 | #define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010 | |
| 938 | #define EEPROM_INIT_CONTROL3_PORT_B 0x0014 | |
| 939 | #define EEPROM_INIT_3GIO_3 0x001A | |
| 940 | #define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020 | |
| 941 | #define EEPROM_INIT_CONTROL3_PORT_A 0x0024 | |
| 942 | #define EEPROM_CFG 0x0012 | |
| 943 | #define EEPROM_FLASH_VERSION 0x0032 | |
| 944 | #define EEPROM_CHECKSUM_REG 0x003F | |
| 945 | ||
| 946 | #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ | |
| 947 | #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ | |
| 948 | ||
| 06e7fa0a DF |
949 | /* PCI Express Control */ |
| 950 | /* 3GIO Control Register - GCR (0x05B00; RW) */ | |
| 951 | #define E1000_L0S_ADJUST (1 << 9) | |
| 952 | #define E1000_L1_ENTRY_LATENCY_MSB (1 << 23) | |
| 953 | #define E1000_L1_ENTRY_LATENCY_LSB (1 << 25 | 1 << 26) | |
| 954 | ||
| 955 | #define E1000_L0S_ADJUST (1 << 9) | |
| 956 | #define E1000_L1_ENTRY_LATENCY_MSB (1 << 23) | |
| 957 | #define E1000_L1_ENTRY_LATENCY_LSB (1 << 25 | 1 << 26) | |
| 958 | ||
| 959 | #define E1000_GCR_RO_BITS (1 << 23 | 1 << 25 | 1 << 26) | |
| 960 | ||
| 961 | /* MSI-X PBA Clear register */ | |
| 962 | #define E1000_PBACLR_VALID_MASK (BIT(5) - 1) | |
| 963 | ||
| 7c23b892 AZ |
964 | /* Transmit Descriptor */ |
| 965 | struct e1000_tx_desc { | |
| 966 | uint64_t buffer_addr; /* Address of the descriptor's data buffer */ | |
| 967 | union { | |
| 968 | uint32_t data; | |
| 969 | struct { | |
| 970 | uint16_t length; /* Data buffer length */ | |
| 971 | uint8_t cso; /* Checksum offset */ | |
| 972 | uint8_t cmd; /* Descriptor control */ | |
| 973 | } flags; | |
| 974 | } lower; | |
| 975 | union { | |
| 976 | uint32_t data; | |
| 977 | struct { | |
| 978 | uint8_t status; /* Descriptor status */ | |
| 979 | uint8_t css; /* Checksum start */ | |
| 980 | uint16_t special; | |
| 981 | } fields; | |
| 982 | } upper; | |
| 983 | }; | |
| 984 | ||
| 985 | /* Transmit Descriptor bit definitions */ | |
| 986 | #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ | |
| 987 | #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ | |
| 988 | #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ | |
| 989 | #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ | |
| 990 | #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ | |
| 991 | #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ | |
| 992 | #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ | |
| 993 | #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ | |
| 994 | #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ | |
| 995 | #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ | |
| 996 | #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ | |
| 997 | #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ | |
| 998 | #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ | |
| 999 | #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ | |
| 1000 | #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ | |
| 1001 | #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ | |
| 1002 | #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ | |
| 1003 | #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ | |
| 1004 | #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ | |
| 06e7fa0a | 1005 | #define E1000_TXD_CMD_SNAP 0x40000000 /* Update SNAP header */ |
| 7c23b892 | 1006 | #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ |
| 06e7fa0a | 1007 | #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ |
| 7c23b892 AZ |
1008 | |
| 1009 | /* Transmit Control */ | |
| 1010 | #define E1000_TCTL_RST 0x00000001 /* software reset */ | |
| 1011 | #define E1000_TCTL_EN 0x00000002 /* enable tx */ | |
| 1012 | #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ | |
| 1013 | #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ | |
| 1014 | #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ | |
| 1015 | #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ | |
| 1016 | #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ | |
| 1017 | #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ | |
| 1018 | #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ | |
| 1019 | #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ | |
| 1020 | #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ | |
| 1021 | ||
| 06e7fa0a | 1022 | /* Legacy Receive Descriptor */ |
| 7c23b892 AZ |
1023 | struct e1000_rx_desc { |
| 1024 | uint64_t buffer_addr; /* Address of the descriptor's data buffer */ | |
| 1025 | uint16_t length; /* Length of data DMAed into data buffer */ | |
| 1026 | uint16_t csum; /* Packet checksum */ | |
| 1027 | uint8_t status; /* Descriptor status */ | |
| 1028 | uint8_t errors; /* Descriptor Errors */ | |
| 1029 | uint16_t special; | |
| 1030 | }; | |
| 1031 | ||
| 06e7fa0a DF |
1032 | /* Extended Receive Descriptor */ |
| 1033 | union e1000_rx_desc_extended { | |
| 1034 | struct { | |
| 1035 | uint64_t buffer_addr; | |
| 1036 | uint64_t reserved; | |
| 1037 | } read; | |
| 1038 | struct { | |
| 1039 | struct { | |
| 1040 | uint32_t mrq; /* Multiple Rx Queues */ | |
| 1041 | union { | |
| 1042 | uint32_t rss; /* RSS Hash */ | |
| 1043 | struct { | |
| 1044 | uint16_t ip_id; /* IP id */ | |
| 1045 | uint16_t csum; /* Packet Checksum */ | |
| 1046 | } csum_ip; | |
| 1047 | } hi_dword; | |
| 1048 | } lower; | |
| 1049 | struct { | |
| 1050 | uint32_t status_error; /* ext status/error */ | |
| 1051 | uint16_t length; | |
| 1052 | uint16_t vlan; /* VLAN tag */ | |
| 1053 | } upper; | |
| 1054 | } wb; /* writeback */ | |
| 1055 | }; | |
| 1056 | ||
| 1057 | #define MAX_PS_BUFFERS 4 | |
| 1058 | ||
| 1059 | /* Number of packet split data buffers (not including the header buffer) */ | |
| 1060 | #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) | |
| 1061 | ||
| 1062 | /* Receive Descriptor - Packet Split */ | |
| 1063 | union e1000_rx_desc_packet_split { | |
| 1064 | struct { | |
| 1065 | /* one buffer for protocol header(s), three data buffers */ | |
| 1066 | uint64_t buffer_addr[MAX_PS_BUFFERS]; | |
| 1067 | } read; | |
| 1068 | struct { | |
| 1069 | struct { | |
| 1070 | uint32_t mrq; /* Multiple Rx Queues */ | |
| 1071 | union { | |
| 1072 | uint32_t rss; /* RSS Hash */ | |
| 1073 | struct { | |
| 1074 | uint16_t ip_id; /* IP id */ | |
| 1075 | uint16_t csum; /* Packet Checksum */ | |
| 1076 | } csum_ip; | |
| 1077 | } hi_dword; | |
| 1078 | } lower; | |
| 1079 | struct { | |
| 1080 | uint32_t status_error; /* ext status/error */ | |
| 1081 | uint16_t length0; /* length of buffer 0 */ | |
| 1082 | uint16_t vlan; /* VLAN tag */ | |
| 1083 | } middle; | |
| 1084 | struct { | |
| 1085 | uint16_t header_status; | |
| 1086 | /* length of buffers 1-3 */ | |
| 1087 | uint16_t length[PS_PAGE_BUFFERS]; | |
| 1088 | } upper; | |
| 1089 | uint64_t reserved; | |
| 1090 | } wb; /* writeback */ | |
| 1091 | }; | |
| 1092 | ||
| 1093 | /* Receive Checksum Control bits */ | |
| 1094 | #define E1000_RXCSUM_IPOFLD 0x100 /* IP Checksum Offload Enable */ | |
| 1095 | #define E1000_RXCSUM_TUOFLD 0x200 /* TCP/UDP Checksum Offload Enable */ | |
| 1096 | #define E1000_RXCSUM_PCSD 0x2000 /* Packet Checksum Disable */ | |
| 1097 | ||
| 1098 | #define E1000_RING_DESC_LEN (16) | |
| 1099 | #define E1000_RING_DESC_LEN_SHIFT (4) | |
| 1100 | ||
| 1101 | #define E1000_MIN_RX_DESC_LEN E1000_RING_DESC_LEN | |
| 1102 | #define E1000_MAX_RX_DESC_LEN (sizeof(union e1000_rx_desc_packet_split)) | |
| 1103 | ||
| 1654b2d6 | 1104 | /* Receive Descriptor bit definitions */ |
| 7c23b892 AZ |
1105 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
| 1106 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ | |
| 1107 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ | |
| 1108 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | |
| 1109 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ | |
| 1110 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ | |
| 1111 | #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ | |
| 1112 | #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ | |
| 1113 | #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ | |
| 1114 | #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ | |
| 1115 | #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ | |
| 1116 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ | |
| 1117 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ | |
| 1118 | #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ | |
| 1119 | #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ | |
| 1120 | #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ | |
| 1121 | #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ | |
| 1122 | #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ | |
| 1123 | #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ | |
| 1124 | #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ | |
| 1125 | #define E1000_RXD_SPC_PRI_SHIFT 13 | |
| 1126 | #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ | |
| 1127 | #define E1000_RXD_SPC_CFI_SHIFT 12 | |
| 1128 | ||
| 06e7fa0a DF |
1129 | /* RX packet types */ |
| 1130 | #define E1000_RXD_PKT_MAC (0) | |
| 1131 | #define E1000_RXD_PKT_IP4 (1) | |
| 1132 | #define E1000_RXD_PKT_IP4_XDP (2) | |
| 1133 | #define E1000_RXD_PKT_IP6 (5) | |
| 1134 | #define E1000_RXD_PKT_IP6_XDP (6) | |
| 1135 | ||
| 1136 | #define E1000_RXD_PKT_TYPE(t) ((t) << 16) | |
| 1137 | ||
| 7c23b892 AZ |
1138 | #define E1000_RXDEXT_STATERR_CE 0x01000000 |
| 1139 | #define E1000_RXDEXT_STATERR_SE 0x02000000 | |
| 1140 | #define E1000_RXDEXT_STATERR_SEQ 0x04000000 | |
| 1141 | #define E1000_RXDEXT_STATERR_CXE 0x10000000 | |
| 1142 | #define E1000_RXDEXT_STATERR_TCPE 0x20000000 | |
| 1143 | #define E1000_RXDEXT_STATERR_IPE 0x40000000 | |
| 1144 | #define E1000_RXDEXT_STATERR_RXE 0x80000000 | |
| 1145 | ||
| 1146 | #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 | |
| 1147 | #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF | |
| 1148 | ||
| 1149 | /* Receive Address */ | |
| 1150 | #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ | |
| 1151 | ||
| 1152 | /* Offload Context Descriptor */ | |
| 1153 | struct e1000_context_desc { | |
| 1154 | union { | |
| 1155 | uint32_t ip_config; | |
| 1156 | struct { | |
| 1157 | uint8_t ipcss; /* IP checksum start */ | |
| 1158 | uint8_t ipcso; /* IP checksum offset */ | |
| 1159 | uint16_t ipcse; /* IP checksum end */ | |
| 1160 | } ip_fields; | |
| 1161 | } lower_setup; | |
| 1162 | union { | |
| 1163 | uint32_t tcp_config; | |
| 1164 | struct { | |
| 1165 | uint8_t tucss; /* TCP checksum start */ | |
| 1166 | uint8_t tucso; /* TCP checksum offset */ | |
| 1167 | uint16_t tucse; /* TCP checksum end */ | |
| 1168 | } tcp_fields; | |
| 1169 | } upper_setup; | |
| 1170 | uint32_t cmd_and_length; /* */ | |
| 1171 | union { | |
| 1172 | uint32_t data; | |
| 1173 | struct { | |
| 1174 | uint8_t status; /* Descriptor status */ | |
| 1175 | uint8_t hdr_len; /* Header length */ | |
| 1176 | uint16_t mss; /* Maximum segment size */ | |
| 1177 | } fields; | |
| 1178 | } tcp_seg_setup; | |
| 1179 | }; | |
| 1180 | ||
| 1181 | /* Offload data descriptor */ | |
| 1182 | struct e1000_data_desc { | |
| 1183 | uint64_t buffer_addr; /* Address of the descriptor's buffer address */ | |
| 1184 | union { | |
| 1185 | uint32_t data; | |
| 1186 | struct { | |
| 1187 | uint16_t length; /* Data buffer length */ | |
| 1188 | uint8_t typ_len_ext; /* */ | |
| 1189 | uint8_t cmd; /* */ | |
| 1190 | } flags; | |
| 1191 | } lower; | |
| 1192 | union { | |
| 1193 | uint32_t data; | |
| 1194 | struct { | |
| 1195 | uint8_t status; /* Descriptor status */ | |
| 1196 | uint8_t popts; /* Packet Options */ | |
| 1197 | uint16_t special; /* */ | |
| 1198 | } fields; | |
| 1199 | } upper; | |
| 1200 | }; | |
| 1201 | ||
| 1202 | /* Management Control */ | |
| 1203 | #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ | |
| 1204 | #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ | |
| 1205 | #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ | |
| 1206 | #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ | |
| 1207 | #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ | |
| 1208 | #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ | |
| 1209 | #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ | |
| 1210 | #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ | |
| 1211 | #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ | |
| 1212 | #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery | |
| 1213 | * Filtering */ | |
| 1214 | #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ | |
| 06e7fa0a DF |
1215 | #define E1000_MANC_DIS_IP_CHK_ARP 0x10000000 /* Disable IP address chacking */ |
| 1216 | /*for ARP packets - in 82574 */ | |
| 7c23b892 AZ |
1217 | #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ |
| 1218 | #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ | |
| 1219 | #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ | |
| 1220 | #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ | |
| 1221 | #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ | |
| 1222 | #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address | |
| 1223 | * filtering */ | |
| 1224 | #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host | |
| 1225 | * memory */ | |
| 1226 | #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address | |
| 1227 | * filtering */ | |
| 1228 | #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ | |
| 1229 | #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ | |
| 1230 | #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ | |
| 1231 | #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ | |
| 1232 | #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ | |
| 1233 | #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ | |
| 1234 | #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ | |
| 1235 | #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ | |
| 1236 | ||
| 1237 | #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ | |
| 1238 | #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ | |
| 1239 | ||
| 06e7fa0a DF |
1240 | /* FACTPS Control */ |
| 1241 | #define E1000_FACTPS_LAN0_ON 0x00000004 /* Lan 0 enable */ | |
| 1242 | ||
| 7c23b892 AZ |
1243 | /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ |
| 1244 | #define EEPROM_SUM 0xBABA | |
| 1245 | ||
| 06e7fa0a DF |
1246 | /* I/O-Mapped Access to Internal Registers, Memories, and Flash */ |
| 1247 | #define E1000_IOADDR 0x00 | |
| 1248 | #define E1000_IODATA 0x04 | |
| 1249 | ||
| 121d0712 | 1250 | #endif /* HW_E1000_REGS_H */ |