[qemu.git] / target-xtensa / xtensa-semi.c

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <errno.h>
#include <unistd.h>
#include <string.h>
#include <stddef.h>
#include "cpu.h"
#include "helper.h"
#include "qemu-log.h"

enum {
    TARGET_SYS_exit = 1,
    TARGET_SYS_read = 3,
    TARGET_SYS_write = 4,
    TARGET_SYS_open = 5,
    TARGET_SYS_close = 6,
    TARGET_SYS_lseek = 19,
    TARGET_SYS_select_one = 29,

    TARGET_SYS_argc = 1000,
    TARGET_SYS_argv_sz = 1001,
    TARGET_SYS_argv = 1002,
    TARGET_SYS_memset = 1004,
};

enum {
    SELECT_ONE_READ   = 1,
    SELECT_ONE_WRITE  = 2,
    SELECT_ONE_EXCEPT = 3,
};

enum {
    TARGET_EPERM        =  1,
    TARGET_ENOENT       =  2,
    TARGET_ESRCH        =  3,
    TARGET_EINTR        =  4,
    TARGET_EIO          =  5,
    TARGET_ENXIO        =  6,
    TARGET_E2BIG        =  7,
    TARGET_ENOEXEC      =  8,
    TARGET_EBADF        =  9,
    TARGET_ECHILD       = 10,
    TARGET_EAGAIN       = 11,
    TARGET_ENOMEM       = 12,
    TARGET_EACCES       = 13,
    TARGET_EFAULT       = 14,
    TARGET_ENOTBLK      = 15,
    TARGET_EBUSY        = 16,
    TARGET_EEXIST       = 17,
    TARGET_EXDEV        = 18,
    TARGET_ENODEV       = 19,
    TARGET_ENOTDIR      = 20,
    TARGET_EISDIR       = 21,
    TARGET_EINVAL       = 22,
    TARGET_ENFILE       = 23,
    TARGET_EMFILE       = 24,
    TARGET_ENOTTY       = 25,
    TARGET_ETXTBSY      = 26,
    TARGET_EFBIG        = 27,
    TARGET_ENOSPC       = 28,
    TARGET_ESPIPE       = 29,
    TARGET_EROFS        = 30,
    TARGET_EMLINK       = 31,
    TARGET_EPIPE        = 32,
    TARGET_EDOM         = 33,
    TARGET_ERANGE       = 34,
    TARGET_ENOSYS       = 88,
    TARGET_ELOOP        = 92,
};

static uint32_t errno_h2g(int host_errno)
{
    static const uint32_t guest_errno[] = {
        [EPERM]         = TARGET_EPERM,
        [ENOENT]        = TARGET_ENOENT,
        [ESRCH]         = TARGET_ESRCH,
        [EINTR]         = TARGET_EINTR,
        [EIO]           = TARGET_EIO,
        [ENXIO]         = TARGET_ENXIO,
        [E2BIG]         = TARGET_E2BIG,
        [ENOEXEC]       = TARGET_ENOEXEC,
        [EBADF]         = TARGET_EBADF,
        [ECHILD]        = TARGET_ECHILD,
        [EAGAIN]        = TARGET_EAGAIN,
        [ENOMEM]        = TARGET_ENOMEM,
        [EACCES]        = TARGET_EACCES,
        [EFAULT]        = TARGET_EFAULT,
#ifdef ENOTBLK
        [ENOTBLK]       = TARGET_ENOTBLK,
#endif
        [EBUSY]         = TARGET_EBUSY,
        [EEXIST]        = TARGET_EEXIST,
        [EXDEV]         = TARGET_EXDEV,
        [ENODEV]        = TARGET_ENODEV,
        [ENOTDIR]       = TARGET_ENOTDIR,
        [EISDIR]        = TARGET_EISDIR,
        [EINVAL]        = TARGET_EINVAL,
        [ENFILE]        = TARGET_ENFILE,
        [EMFILE]        = TARGET_EMFILE,
        [ENOTTY]        = TARGET_ENOTTY,
#ifdef ETXTBSY
        [ETXTBSY]       = TARGET_ETXTBSY,
#endif
        [EFBIG]         = TARGET_EFBIG,
        [ENOSPC]        = TARGET_ENOSPC,
        [ESPIPE]        = TARGET_ESPIPE,
        [EROFS]         = TARGET_EROFS,
        [EMLINK]        = TARGET_EMLINK,
        [EPIPE]         = TARGET_EPIPE,
        [EDOM]          = TARGET_EDOM,
        [ERANGE]        = TARGET_ERANGE,
        [ENOSYS]        = TARGET_ENOSYS,
#ifdef ELOOP
        [ELOOP]         = TARGET_ELOOP,
#endif
    };

    if (host_errno == 0) {
        return 0;
    } else if (host_errno > 0 && host_errno < ARRAY_SIZE(guest_errno) &&
            guest_errno[host_errno]) {
        return guest_errno[host_errno];
    } else {
        return TARGET_EINVAL;
    }
}

void HELPER(simcall)(CPUXtensaState *env)
{
    uint32_t *regs = env->regs;

    switch (regs[2]) {
    case TARGET_SYS_exit:
        qemu_log("exit(%d) simcall\n", regs[3]);
        exit(regs[3]);
        break;

    case TARGET_SYS_read:
    case TARGET_SYS_write:
        {
            bool is_write = regs[2] == TARGET_SYS_write;
            uint32_t fd = regs[3];
            uint32_t vaddr = regs[4];
            uint32_t len = regs[5];

            while (len > 0) {
                hwaddr paddr =
                    cpu_get_phys_page_debug(env, vaddr);
                uint32_t page_left =
                    TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1));
                uint32_t io_sz = page_left < len ? page_left : len;
                hwaddr sz = io_sz;
                void *buf = cpu_physical_memory_map(paddr, &sz, is_write);

                if (buf) {
                    vaddr += io_sz;
                    len -= io_sz;
                    regs[2] = is_write ?
                        write(fd, buf, io_sz) :
                        read(fd, buf, io_sz);
                    regs[3] = errno_h2g(errno);
                    cpu_physical_memory_unmap(buf, sz, is_write, sz);
                    if (regs[2] == -1) {
                        break;
                    }
                } else {
                    regs[2] = -1;
                    regs[3] = TARGET_EINVAL;
                    break;
                }
            }
        }
        break;

    case TARGET_SYS_open:
        {
            char name[1024];
            int rc;
            int i;

            for (i = 0; i < ARRAY_SIZE(name); ++i) {
                rc = cpu_memory_rw_debug(
                        env, regs[3] + i, (uint8_t *)name + i, 1, 0);
                if (rc != 0 || name[i] == 0) {
                    break;
                }
            }

            if (rc == 0 && i < ARRAY_SIZE(name)) {
                regs[2] = open(name, regs[4], regs[5]);
                regs[3] = errno_h2g(errno);
            } else {
                regs[2] = -1;
                regs[3] = TARGET_EINVAL;
            }
        }
        break;

    case TARGET_SYS_close:
        if (regs[3] < 3) {
            regs[2] = regs[3] = 0;
        } else {
            regs[2] = close(regs[3]);
            regs[3] = errno_h2g(errno);
        }
        break;

    case TARGET_SYS_lseek:
        regs[2] = lseek(regs[3], (off_t)(int32_t)regs[4], regs[5]);
        regs[3] = errno_h2g(errno);
        break;

    case TARGET_SYS_select_one:
        {
            uint32_t fd = regs[3];
            uint32_t rq = regs[4];
            uint32_t target_tv = regs[5];
            uint32_t target_tvv[2];

            struct timeval tv = {0};
            fd_set fdset;

            FD_ZERO(&fdset);
            FD_SET(fd, &fdset);

            if (target_tv) {
                cpu_memory_rw_debug(env, target_tv,
                        (uint8_t *)target_tvv, sizeof(target_tvv), 0);
                tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
                tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
            }
            regs[2] = select(fd + 1,
                    rq == SELECT_ONE_READ   ? &fdset : NULL,
                    rq == SELECT_ONE_WRITE  ? &fdset : NULL,
                    rq == SELECT_ONE_EXCEPT ? &fdset : NULL,
                    target_tv ? &tv : NULL);
            regs[3] = errno_h2g(errno);
        }
        break;

    case TARGET_SYS_argc:
        regs[2] = 1;
        regs[3] = 0;
        break;

    case TARGET_SYS_argv_sz:
        regs[2] = 128;
        regs[3] = 0;
        break;

    case TARGET_SYS_argv:
        {
            struct Argv {
                uint32_t argptr[2];
                char text[120];
            } argv = {
                {0, 0},
                "test"
            };

            argv.argptr[0] = tswap32(regs[3] + offsetof(struct Argv, text));
            cpu_memory_rw_debug(
                    env, regs[3], (uint8_t *)&argv, sizeof(argv), 1);
        }
        break;

    case TARGET_SYS_memset:
        {
            uint32_t base = regs[3];
            uint32_t sz = regs[5];

            while (sz) {
                hwaddr len = sz;
                void *buf = cpu_physical_memory_map(base, &len, 1);

                if (buf && len) {
                    memset(buf, regs[4], len);
                    cpu_physical_memory_unmap(buf, len, 1, len);
                } else {
                    len = 1;
                }
                base += len;
                sz -= len;
            }
            regs[2] = regs[3];
            regs[3] = 0;
        }
        break;

    default:
        qemu_log("%s(%d): not implemented\n", __func__, regs[2]);
        regs[2] = -1;
        regs[3] = TARGET_ENOSYS;
        break;
    }
}
Commit	Line	Data
1ddeaa5d MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
	28	#include <errno.h>
	29	#include <unistd.h>
	30	#include <string.h>
	31	#include <stddef.h>
	32	#include "cpu.h"
16c1deae	33	#include "helper.h"
1ddeaa5d MF	34	#include "qemu-log.h"
	35
	36	enum {
	37	TARGET_SYS_exit = 1,
	38	TARGET_SYS_read = 3,
	39	TARGET_SYS_write = 4,
	40	TARGET_SYS_open = 5,
	41	TARGET_SYS_close = 6,
	42	TARGET_SYS_lseek = 19,
	43	TARGET_SYS_select_one = 29,
	44
	45	TARGET_SYS_argc = 1000,
	46	TARGET_SYS_argv_sz = 1001,
	47	TARGET_SYS_argv = 1002,
	48	TARGET_SYS_memset = 1004,
	49	};
	50
	51	enum {
	52	SELECT_ONE_READ = 1,
	53	SELECT_ONE_WRITE = 2,
	54	SELECT_ONE_EXCEPT = 3,
	55	};
	56
d6ce52c1 MF	57	enum {
	58	TARGET_EPERM = 1,
	59	TARGET_ENOENT = 2,
	60	TARGET_ESRCH = 3,
	61	TARGET_EINTR = 4,
	62	TARGET_EIO = 5,
	63	TARGET_ENXIO = 6,
	64	TARGET_E2BIG = 7,
	65	TARGET_ENOEXEC = 8,
	66	TARGET_EBADF = 9,
	67	TARGET_ECHILD = 10,
	68	TARGET_EAGAIN = 11,
	69	TARGET_ENOMEM = 12,
	70	TARGET_EACCES = 13,
	71	TARGET_EFAULT = 14,
	72	TARGET_ENOTBLK = 15,
	73	TARGET_EBUSY = 16,
	74	TARGET_EEXIST = 17,
	75	TARGET_EXDEV = 18,
	76	TARGET_ENODEV = 19,
	77	TARGET_ENOTDIR = 20,
	78	TARGET_EISDIR = 21,
	79	TARGET_EINVAL = 22,
	80	TARGET_ENFILE = 23,
	81	TARGET_EMFILE = 24,
	82	TARGET_ENOTTY = 25,
	83	TARGET_ETXTBSY = 26,
	84	TARGET_EFBIG = 27,
	85	TARGET_ENOSPC = 28,
	86	TARGET_ESPIPE = 29,
	87	TARGET_EROFS = 30,
	88	TARGET_EMLINK = 31,
	89	TARGET_EPIPE = 32,
	90	TARGET_EDOM = 33,
	91	TARGET_ERANGE = 34,
	92	TARGET_ENOSYS = 88,
	93	TARGET_ELOOP = 92,
	94	};
	95
	96	static uint32_t errno_h2g(int host_errno)
	97	{
	98	static const uint32_t guest_errno[] = {
	99	[EPERM] = TARGET_EPERM,
	100	[ENOENT] = TARGET_ENOENT,
	101	[ESRCH] = TARGET_ESRCH,
	102	[EINTR] = TARGET_EINTR,
	103	[EIO] = TARGET_EIO,
	104	[ENXIO] = TARGET_ENXIO,
	105	[E2BIG] = TARGET_E2BIG,
	106	[ENOEXEC] = TARGET_ENOEXEC,
	107	[EBADF] = TARGET_EBADF,
	108	[ECHILD] = TARGET_ECHILD,
	109	[EAGAIN] = TARGET_EAGAIN,
	110	[ENOMEM] = TARGET_ENOMEM,
	111	[EACCES] = TARGET_EACCES,
	112	[EFAULT] = TARGET_EFAULT,
c29b1bee	113	#ifdef ENOTBLK
d6ce52c1	114	[ENOTBLK] = TARGET_ENOTBLK,
c29b1bee	115	#endif
d6ce52c1 MF	116	[EBUSY] = TARGET_EBUSY,
	117	[EEXIST] = TARGET_EEXIST,
	118	[EXDEV] = TARGET_EXDEV,
	119	[ENODEV] = TARGET_ENODEV,
	120	[ENOTDIR] = TARGET_ENOTDIR,
	121	[EISDIR] = TARGET_EISDIR,
	122	[EINVAL] = TARGET_EINVAL,
	123	[ENFILE] = TARGET_ENFILE,
	124	[EMFILE] = TARGET_EMFILE,
	125	[ENOTTY] = TARGET_ENOTTY,
c29b1bee	126	#ifdef ETXTBSY
d6ce52c1	127	[ETXTBSY] = TARGET_ETXTBSY,
c29b1bee	128	#endif
d6ce52c1 MF	129	[EFBIG] = TARGET_EFBIG,
	130	[ENOSPC] = TARGET_ENOSPC,
	131	[ESPIPE] = TARGET_ESPIPE,
	132	[EROFS] = TARGET_EROFS,
	133	[EMLINK] = TARGET_EMLINK,
	134	[EPIPE] = TARGET_EPIPE,
	135	[EDOM] = TARGET_EDOM,
	136	[ERANGE] = TARGET_ERANGE,
	137	[ENOSYS] = TARGET_ENOSYS,
c29b1bee	138	#ifdef ELOOP
d6ce52c1	139	[ELOOP] = TARGET_ELOOP,
c29b1bee	140	#endif
d6ce52c1 MF	141	};
	142
	143	if (host_errno == 0) {
	144	return 0;
	145	} else if (host_errno > 0 && host_errno < ARRAY_SIZE(guest_errno) &&
	146	guest_errno[host_errno]) {
	147	return guest_errno[host_errno];
	148	} else {
	149	return TARGET_EINVAL;
	150	}
	151	}
	152
d4a5b622	153	void HELPER(simcall)(CPUXtensaState *env)
1ddeaa5d MF	154	{
	155	uint32_t *regs = env->regs;
	156
	157	switch (regs[2]) {
	158	case TARGET_SYS_exit:
	159	qemu_log("exit(%d) simcall\n", regs[3]);
	160	exit(regs[3]);
	161	break;
	162
	163	case TARGET_SYS_read:
	164	case TARGET_SYS_write:
	165	{
	166	bool is_write = regs[2] == TARGET_SYS_write;
	167	uint32_t fd = regs[3];
	168	uint32_t vaddr = regs[4];
	169	uint32_t len = regs[5];
	170
	171	while (len > 0) {
a8170e5e	172	hwaddr paddr =
1ddeaa5d MF	173	cpu_get_phys_page_debug(env, vaddr);
	174	uint32_t page_left =
	175	TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1));
	176	uint32_t io_sz = page_left < len ? page_left : len;
a8170e5e	177	hwaddr sz = io_sz;
1ddeaa5d MF	178	void *buf = cpu_physical_memory_map(paddr, &sz, is_write);
	179
	180	if (buf) {
	181	vaddr += io_sz;
	182	len -= io_sz;
	183	regs[2] = is_write ?
	184	write(fd, buf, io_sz) :
	185	read(fd, buf, io_sz);
d6ce52c1	186	regs[3] = errno_h2g(errno);
1ddeaa5d MF	187	cpu_physical_memory_unmap(buf, sz, is_write, sz);
	188	if (regs[2] == -1) {
	189	break;
	190	}
	191	} else {
	192	regs[2] = -1;
d6ce52c1	193	regs[3] = TARGET_EINVAL;
1ddeaa5d MF	194	break;
	195	}
	196	}
	197	}
	198	break;
	199
	200	case TARGET_SYS_open:
	201	{
	202	char name[1024];
	203	int rc;
	204	int i;
	205
	206	for (i = 0; i < ARRAY_SIZE(name); ++i) {
	207	rc = cpu_memory_rw_debug(
	208	env, regs[3] + i, (uint8_t *)name + i, 1, 0);
	209	if (rc != 0 \|\| name[i] == 0) {
	210	break;
	211	}
	212	}
	213
	214	if (rc == 0 && i < ARRAY_SIZE(name)) {
	215	regs[2] = open(name, regs[4], regs[5]);
d6ce52c1	216	regs[3] = errno_h2g(errno);
1ddeaa5d MF	217	} else {
1ddeaa5d MF	218	regs[2] = -1;
d6ce52c1	219	regs[3] = TARGET_EINVAL;
1ddeaa5d MF	220	}
	221	}
	222	break;
	223
	224	case TARGET_SYS_close:
	225	if (regs[3] < 3) {
	226	regs[2] = regs[3] = 0;
	227	} else {
	228	regs[2] = close(regs[3]);
d6ce52c1	229	regs[3] = errno_h2g(errno);
1ddeaa5d MF	230	}
	231	break;
	232
	233	case TARGET_SYS_lseek:
	234	regs[2] = lseek(regs[3], (off_t)(int32_t)regs[4], regs[5]);
d6ce52c1	235	regs[3] = errno_h2g(errno);
1ddeaa5d MF	236	break;
	237
	238	case TARGET_SYS_select_one:
	239	{
	240	uint32_t fd = regs[3];
	241	uint32_t rq = regs[4];
	242	uint32_t target_tv = regs[5];
	243	uint32_t target_tvv[2];
	244
	245	struct timeval tv = {0};
	246	fd_set fdset;
	247
	248	FD_ZERO(&fdset);
	249	FD_SET(fd, &fdset);
	250
	251	if (target_tv) {
	252	cpu_memory_rw_debug(env, target_tv,
	253	(uint8_t *)target_tvv, sizeof(target_tvv), 0);
	254	tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
	255	tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
	256	}
	257	regs[2] = select(fd + 1,
	258	rq == SELECT_ONE_READ ? &fdset : NULL,
	259	rq == SELECT_ONE_WRITE ? &fdset : NULL,
	260	rq == SELECT_ONE_EXCEPT ? &fdset : NULL,
	261	target_tv ? &tv : NULL);
d6ce52c1	262	regs[3] = errno_h2g(errno);
1ddeaa5d MF	263	}
	264	break;
	265
	266	case TARGET_SYS_argc:
	267	regs[2] = 1;
	268	regs[3] = 0;
	269	break;
	270
	271	case TARGET_SYS_argv_sz:
	272	regs[2] = 128;
	273	regs[3] = 0;
	274	break;
	275
	276	case TARGET_SYS_argv:
	277	{
	278	struct Argv {
	279	uint32_t argptr[2];
	280	char text[120];
	281	} argv = {
	282	{0, 0},
	283	"test"
	284	};
	285
	286	argv.argptr[0] = tswap32(regs[3] + offsetof(struct Argv, text));
	287	cpu_memory_rw_debug(
	288	env, regs[3], (uint8_t *)&argv, sizeof(argv), 1);
	289	}
	290	break;
	291
	292	case TARGET_SYS_memset:
	293	{
	294	uint32_t base = regs[3];
	295	uint32_t sz = regs[5];
	296
	297	while (sz) {
a8170e5e	298	hwaddr len = sz;
1ddeaa5d MF	299	void *buf = cpu_physical_memory_map(base, &len, 1);
	300
	301	if (buf && len) {
	302	memset(buf, regs[4], len);
	303	cpu_physical_memory_unmap(buf, len, 1, len);
	304	} else {
	305	len = 1;
	306	}
	307	base += len;
	308	sz -= len;
	309	}
	310	regs[2] = regs[3];
	311	regs[3] = 0;
	312	}
	313	break;
	314
	315	default:
	316	qemu_log("%s(%d): not implemented\n", __func__, regs[2]);
e7eee62a	317	regs[2] = -1;
d6ce52c1	318	regs[3] = TARGET_ENOSYS;
1ddeaa5d MF	319	break;
	320	}
	321	}