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[qemu.git] / hw / intc / xics_kvm.c
CommitLineData
11ad93f6
DG
1/*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics, in-kernel emulation
5 *
6 * Copyright (c) 2013 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27
0d75590d 28#include "qemu/osdep.h"
da34e65c 29#include "qapi/error.h"
4771d756
PB
30#include "qemu-common.h"
31#include "cpu.h"
11ad93f6
DG
32#include "hw/hw.h"
33#include "trace.h"
77ac58dd 34#include "sysemu/kvm.h"
11ad93f6
DG
35#include "hw/ppc/spapr.h"
36#include "hw/ppc/xics.h"
37#include "kvm_ppc.h"
38#include "qemu/config-file.h"
39#include "qemu/error-report.h"
40
41#include <sys/ioctl.h>
42
729f8a4f
CLG
43static int kernel_xics_fd = -1;
44
de86eccc
GK
45typedef struct KVMEnabledICP {
46 unsigned long vcpu_id;
47 QLIST_ENTRY(KVMEnabledICP) node;
48} KVMEnabledICP;
49
50static QLIST_HEAD(, KVMEnabledICP)
51 kvm_enabled_icps = QLIST_HEAD_INITIALIZER(&kvm_enabled_icps);
52
11ad93f6
DG
53/*
54 * ICP-KVM
55 */
8e4fba20 56static void icp_get_kvm_state(ICPState *icp)
11ad93f6
DG
57{
58 uint64_t state;
11ad93f6
DG
59 int ret;
60
61 /* ICP for this CPU thread is not in use, exiting */
8e4fba20 62 if (!icp->cs) {
11ad93f6
DG
63 return;
64 }
65
bf358b54 66 ret = kvm_get_one_reg(icp->cs, KVM_REG_PPC_ICP_STATE, &state);
11ad93f6
DG
67 if (ret != 0) {
68 error_report("Unable to retrieve KVM interrupt controller state"
8e4fba20 69 " for CPU %ld: %s", kvm_arch_vcpu_id(icp->cs), strerror(errno));
11ad93f6
DG
70 exit(1);
71 }
72
8e4fba20
CLG
73 icp->xirr = state >> KVM_REG_PPC_ICP_XISR_SHIFT;
74 icp->mfrr = (state >> KVM_REG_PPC_ICP_MFRR_SHIFT)
11ad93f6 75 & KVM_REG_PPC_ICP_MFRR_MASK;
8e4fba20 76 icp->pending_priority = (state >> KVM_REG_PPC_ICP_PPRI_SHIFT)
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DG
77 & KVM_REG_PPC_ICP_PPRI_MASK;
78}
79
dcb556fc
GK
80static void do_icp_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
81{
82 icp_get_kvm_state(arg.host_ptr);
83}
84
85static void icp_synchronize_state(ICPState *icp)
86{
87 if (icp->cs) {
88 run_on_cpu(icp->cs, do_icp_synchronize_state, RUN_ON_CPU_HOST_PTR(icp));
89 }
90}
91
8e4fba20 92static int icp_set_kvm_state(ICPState *icp, int version_id)
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DG
93{
94 uint64_t state;
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DG
95 int ret;
96
97 /* ICP for this CPU thread is not in use, exiting */
8e4fba20 98 if (!icp->cs) {
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99 return 0;
100 }
101
8e4fba20
CLG
102 state = ((uint64_t)icp->xirr << KVM_REG_PPC_ICP_XISR_SHIFT)
103 | ((uint64_t)icp->mfrr << KVM_REG_PPC_ICP_MFRR_SHIFT)
104 | ((uint64_t)icp->pending_priority << KVM_REG_PPC_ICP_PPRI_SHIFT);
11ad93f6 105
bf358b54 106 ret = kvm_set_one_reg(icp->cs, KVM_REG_PPC_ICP_STATE, &state);
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DG
107 if (ret != 0) {
108 error_report("Unable to restore KVM interrupt controller state (0x%"
8e4fba20 109 PRIx64 ") for CPU %ld: %s", state, kvm_arch_vcpu_id(icp->cs),
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DG
110 strerror(errno));
111 return ret;
112 }
113
114 return 0;
115}
116
a4d4edce 117static void icp_kvm_reset(ICPState *icp)
11ad93f6 118{
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DG
119 icp_set_kvm_state(icp, 1);
120}
121
b1fd36c3 122static void icp_kvm_realize(ICPState *icp, Error **errp)
f0232434 123{
b1fd36c3 124 CPUState *cs = icp->cs;
de86eccc
GK
125 KVMEnabledICP *enabled_icp;
126 unsigned long vcpu_id = kvm_arch_vcpu_id(cs);
f0232434
CLG
127 int ret;
128
129 if (kernel_xics_fd == -1) {
130 abort();
131 }
132
133 /*
134 * If we are reusing a parked vCPU fd corresponding to the CPU
135 * which was hot-removed earlier we don't have to renable
136 * KVM_CAP_IRQ_XICS capability again.
137 */
de86eccc
GK
138 QLIST_FOREACH(enabled_icp, &kvm_enabled_icps, node) {
139 if (enabled_icp->vcpu_id == vcpu_id) {
140 return;
141 }
f0232434
CLG
142 }
143
de86eccc 144 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_XICS, 0, kernel_xics_fd, vcpu_id);
f0232434 145 if (ret < 0) {
b1fd36c3
GK
146 error_setg(errp, "Unable to connect CPU%ld to kernel XICS: %s", vcpu_id,
147 strerror(errno));
148 return;
f0232434 149 }
de86eccc
GK
150 enabled_icp = g_malloc(sizeof(*enabled_icp));
151 enabled_icp->vcpu_id = vcpu_id;
152 QLIST_INSERT_HEAD(&kvm_enabled_icps, enabled_icp, node);
f0232434
CLG
153}
154
11ad93f6
DG
155static void icp_kvm_class_init(ObjectClass *klass, void *data)
156{
11ad93f6
DG
157 ICPStateClass *icpc = ICP_CLASS(klass);
158
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DG
159 icpc->pre_save = icp_get_kvm_state;
160 icpc->post_load = icp_set_kvm_state;
b1fd36c3 161 icpc->realize = icp_kvm_realize;
a4d4edce 162 icpc->reset = icp_kvm_reset;
dcb556fc 163 icpc->synchronize_state = icp_synchronize_state;
11ad93f6
DG
164}
165
166static const TypeInfo icp_kvm_info = {
167 .name = TYPE_KVM_ICP,
168 .parent = TYPE_ICP,
169 .instance_size = sizeof(ICPState),
170 .class_init = icp_kvm_class_init,
171 .class_size = sizeof(ICPStateClass),
172};
173
174/*
175 * ICS-KVM
176 */
177static void ics_get_kvm_state(ICSState *ics)
178{
11ad93f6 179 uint64_t state;
11ad93f6 180 int i;
bf358b54 181 Error *local_err = NULL;
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DG
182
183 for (i = 0; i < ics->nr_irqs; i++) {
184 ICSIRQState *irq = &ics->irqs[i];
11ad93f6 185
bf358b54
CLG
186 kvm_device_access(kernel_xics_fd, KVM_DEV_XICS_GRP_SOURCES,
187 i + ics->offset, &state, false, &local_err);
188 if (local_err) {
52b43881 189 error_report_err(local_err);
11ad93f6
DG
190 exit(1);
191 }
192
193 irq->server = state & KVM_XICS_DESTINATION_MASK;
194 irq->saved_priority = (state >> KVM_XICS_PRIORITY_SHIFT)
195 & KVM_XICS_PRIORITY_MASK;
196 /*
197 * To be consistent with the software emulation in xics.c, we
198 * split out the masked state + priority that we get from the
199 * kernel into 'current priority' (0xff if masked) and
200 * 'saved priority' (if masked, this is the priority the
201 * interrupt had before it was masked). Masking and unmasking
202 * are done with the ibm,int-off and ibm,int-on RTAS calls.
203 */
204 if (state & KVM_XICS_MASKED) {
205 irq->priority = 0xff;
206 } else {
207 irq->priority = irq->saved_priority;
208 }
209
063cb7cb 210 irq->status = 0;
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DG
211 if (state & KVM_XICS_PENDING) {
212 if (state & KVM_XICS_LEVEL_SENSITIVE) {
213 irq->status |= XICS_STATUS_ASSERTED;
214 } else {
215 /*
216 * A pending edge-triggered interrupt (or MSI)
217 * must have been rejected previously when we
218 * first detected it and tried to deliver it,
219 * so mark it as pending and previously rejected
220 * for consistency with how xics.c works.
221 */
222 irq->status |= XICS_STATUS_MASKED_PENDING
223 | XICS_STATUS_REJECTED;
224 }
225 }
229e16fd
SB
226 if (state & KVM_XICS_PRESENTED) {
227 irq->status |= XICS_STATUS_PRESENTED;
228 }
229 if (state & KVM_XICS_QUEUED) {
230 irq->status |= XICS_STATUS_QUEUED;
231 }
11ad93f6
DG
232 }
233}
234
dcb556fc
GK
235static void ics_synchronize_state(ICSState *ics)
236{
237 ics_get_kvm_state(ics);
238}
239
11ad93f6
DG
240static int ics_set_kvm_state(ICSState *ics, int version_id)
241{
11ad93f6 242 uint64_t state;
11ad93f6 243 int i;
bf358b54 244 Error *local_err = NULL;
11ad93f6
DG
245
246 for (i = 0; i < ics->nr_irqs; i++) {
247 ICSIRQState *irq = &ics->irqs[i];
248 int ret;
249
11ad93f6
DG
250 state = irq->server;
251 state |= (uint64_t)(irq->saved_priority & KVM_XICS_PRIORITY_MASK)
252 << KVM_XICS_PRIORITY_SHIFT;
253 if (irq->priority != irq->saved_priority) {
254 assert(irq->priority == 0xff);
255 state |= KVM_XICS_MASKED;
256 }
257
4af88944 258 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
11ad93f6
DG
259 state |= KVM_XICS_LEVEL_SENSITIVE;
260 if (irq->status & XICS_STATUS_ASSERTED) {
261 state |= KVM_XICS_PENDING;
262 }
263 } else {
264 if (irq->status & XICS_STATUS_MASKED_PENDING) {
265 state |= KVM_XICS_PENDING;
266 }
267 }
229e16fd
SB
268 if (irq->status & XICS_STATUS_PRESENTED) {
269 state |= KVM_XICS_PRESENTED;
270 }
271 if (irq->status & XICS_STATUS_QUEUED) {
272 state |= KVM_XICS_QUEUED;
273 }
11ad93f6 274
52b43881
CLG
275 ret = kvm_device_access(kernel_xics_fd, KVM_DEV_XICS_GRP_SOURCES,
276 i + ics->offset, &state, true, &local_err);
bf358b54 277 if (local_err) {
52b43881 278 error_report_err(local_err);
11ad93f6
DG
279 return ret;
280 }
281 }
282
283 return 0;
284}
285
286static void ics_kvm_set_irq(void *opaque, int srcno, int val)
287{
288 ICSState *ics = opaque;
289 struct kvm_irq_level args;
290 int rc;
291
292 args.irq = srcno + ics->offset;
4af88944 293 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MSI) {
11ad93f6
DG
294 if (!val) {
295 return;
296 }
297 args.level = KVM_INTERRUPT_SET;
298 } else {
299 args.level = val ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
300 }
301 rc = kvm_vm_ioctl(kvm_state, KVM_IRQ_LINE, &args);
302 if (rc < 0) {
303 perror("kvm_irq_line");
304 }
305}
306
7ea6e067 307static void ics_kvm_reset(void *dev)
11ad93f6 308{
d4d7a59a 309 ICSState *ics = ICS_SIMPLE(dev);
fb0e843a 310 int i;
a7e519a8
AK
311 uint8_t flags[ics->nr_irqs];
312
313 for (i = 0; i < ics->nr_irqs; i++) {
314 flags[i] = ics->irqs[i].flags;
315 }
fb0e843a
AK
316
317 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
a7e519a8 318
fb0e843a
AK
319 for (i = 0; i < ics->nr_irqs; i++) {
320 ics->irqs[i].priority = 0xff;
321 ics->irqs[i].saved_priority = 0xff;
a7e519a8 322 ics->irqs[i].flags = flags[i];
fb0e843a
AK
323 }
324
325 ics_set_kvm_state(ics, 1);
11ad93f6
DG
326}
327
100f7388 328static void ics_kvm_realize(ICSState *ics, Error **errp)
11ad93f6 329{
11ad93f6
DG
330 if (!ics->nr_irqs) {
331 error_setg(errp, "Number of interrupts needs to be greater 0");
332 return;
333 }
334 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
11ad93f6 335 ics->qirqs = qemu_allocate_irqs(ics_kvm_set_irq, ics, ics->nr_irqs);
7ea6e067 336
100f7388 337 qemu_register_reset(ics_kvm_reset, ics);
11ad93f6
DG
338}
339
340static void ics_kvm_class_init(ObjectClass *klass, void *data)
341{
d4d7a59a 342 ICSStateClass *icsc = ICS_BASE_CLASS(klass);
11ad93f6 343
4e4169f7 344 icsc->realize = ics_kvm_realize;
11ad93f6
DG
345 icsc->pre_save = ics_get_kvm_state;
346 icsc->post_load = ics_set_kvm_state;
dcb556fc 347 icsc->synchronize_state = ics_synchronize_state;
11ad93f6
DG
348}
349
350static const TypeInfo ics_kvm_info = {
d4d7a59a
BH
351 .name = TYPE_ICS_KVM,
352 .parent = TYPE_ICS_SIMPLE,
11ad93f6
DG
353 .instance_size = sizeof(ICSState),
354 .class_init = ics_kvm_class_init,
355};
356
357/*
358 * XICS-KVM
359 */
11ad93f6 360
28e02042 361static void rtas_dummy(PowerPCCPU *cpu, sPAPRMachineState *spapr,
11ad93f6
DG
362 uint32_t token,
363 uint32_t nargs, target_ulong args,
364 uint32_t nret, target_ulong rets)
365{
366 error_report("pseries: %s must never be called for in-kernel XICS",
367 __func__);
368}
369
2192a930 370int xics_kvm_init(sPAPRMachineState *spapr, Error **errp)
11ad93f6 371{
817bb6a4 372 int rc;
11ad93f6
DG
373
374 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_IRQ_XICS)) {
375 error_setg(errp,
376 "KVM and IRQ_XICS capability must be present for in-kernel XICS");
377 goto fail;
378 }
379
3a3b8502
AK
380 spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_dummy);
381 spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_dummy);
382 spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_dummy);
383 spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_dummy);
11ad93f6 384
3a3b8502 385 rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_SET_XIVE, "ibm,set-xive");
11ad93f6
DG
386 if (rc < 0) {
387 error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,set-xive");
388 goto fail;
389 }
390
3a3b8502 391 rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_GET_XIVE, "ibm,get-xive");
11ad93f6
DG
392 if (rc < 0) {
393 error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,get-xive");
394 goto fail;
395 }
396
3a3b8502 397 rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_INT_ON, "ibm,int-on");
11ad93f6
DG
398 if (rc < 0) {
399 error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,int-on");
400 goto fail;
401 }
402
3a3b8502 403 rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_INT_OFF, "ibm,int-off");
11ad93f6
DG
404 if (rc < 0) {
405 error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,int-off");
406 goto fail;
407 }
408
bf358b54
CLG
409 /* Create the KVM XICS device */
410 rc = kvm_create_device(kvm_state, KVM_DEV_TYPE_XICS, false);
11ad93f6
DG
411 if (rc < 0) {
412 error_setg_errno(errp, -rc, "Error on KVM_CREATE_DEVICE for XICS");
413 goto fail;
414 }
415
bf358b54 416 kernel_xics_fd = rc;
9554233c 417 kvm_kernel_irqchip = true;
9554233c
AK
418 kvm_msi_via_irqfd_allowed = true;
419 kvm_gsi_direct_mapping = true;
420
bf358b54 421 return 0;
11ad93f6
DG
422
423fail:
424 kvmppc_define_rtas_kernel_token(0, "ibm,set-xive");
425 kvmppc_define_rtas_kernel_token(0, "ibm,get-xive");
426 kvmppc_define_rtas_kernel_token(0, "ibm,int-on");
427 kvmppc_define_rtas_kernel_token(0, "ibm,int-off");
2192a930 428 return -1;
11ad93f6
DG
429}
430
11ad93f6
DG
431static void xics_kvm_register_types(void)
432{
11ad93f6
DG
433 type_register_static(&ics_kvm_info);
434 type_register_static(&icp_kvm_info);
435}
436
437type_init(xics_kvm_register_types)
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