[qemu.git] / hw / intc / omap_intc.c

/*
 * TI OMAP interrupt controller emulation.
 *
 * Copyright (C) 2006-2008 Andrzej Zaborowski  <[email protected]>
 * Copyright (C) 2007-2008 Nokia Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) version 3 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/arm/omap.h"
#include "hw/sysbus.h"
#include "qemu/error-report.h"
#include "qapi/error.h"

/* Interrupt Handlers */
struct omap_intr_handler_bank_s {
    uint32_t irqs;
    uint32_t inputs;
    uint32_t mask;
    uint32_t fiq;
    uint32_t sens_edge;
    uint32_t swi;
    unsigned char priority[32];
};

#define TYPE_OMAP_INTC "common-omap-intc"
#define OMAP_INTC(obj) \
    OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC)

struct omap_intr_handler_s {
    SysBusDevice parent_obj;

    qemu_irq *pins;
    qemu_irq parent_intr[2];
    MemoryRegion mmio;
    void *iclk;
    void *fclk;
    unsigned char nbanks;
    int level_only;
    uint32_t size;

    uint8_t revision;

    /* state */
    uint32_t new_agr[2];
    int sir_intr[2];
    int autoidle;
    uint32_t mask;
    struct omap_intr_handler_bank_s bank[3];
};

static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
{
    int i, j, sir_intr, p_intr, p;
    uint32_t level;
    sir_intr = 0;
    p_intr = 255;

    /* Find the interrupt line with the highest dynamic priority.
     * Note: 0 denotes the hightest priority.
     * If all interrupts have the same priority, the default order is IRQ_N,
     * IRQ_N-1,...,IRQ_0. */
    for (j = 0; j < s->nbanks; ++j) {
        level = s->bank[j].irqs & ~s->bank[j].mask &
                (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);

        while (level != 0) {
            i = ctz32(level);
            p = s->bank[j].priority[i];
            if (p <= p_intr) {
                p_intr = p;
                sir_intr = 32 * j + i;
            }
            level &= level - 1;
        }
    }
    s->sir_intr[is_fiq] = sir_intr;
}

static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
{
    int i;
    uint32_t has_intr = 0;

    for (i = 0; i < s->nbanks; ++i)
        has_intr |= s->bank[i].irqs & ~s->bank[i].mask &
                (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);

    if (s->new_agr[is_fiq] & has_intr & s->mask) {
        s->new_agr[is_fiq] = 0;
        omap_inth_sir_update(s, is_fiq);
        qemu_set_irq(s->parent_intr[is_fiq], 1);
    }
}

#define INT_FALLING_EDGE	0
#define INT_LOW_LEVEL		1

static void omap_set_intr(void *opaque, int irq, int req)
{
    struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
    uint32_t rise;

    struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
    int n = irq & 31;

    if (req) {
        rise = ~bank->irqs & (1 << n);
        if (~bank->sens_edge & (1 << n))
            rise &= ~bank->inputs;

        bank->inputs |= (1 << n);
        if (rise) {
            bank->irqs |= rise;
            omap_inth_update(ih, 0);
            omap_inth_update(ih, 1);
        }
    } else {
        rise = bank->sens_edge & bank->irqs & (1 << n);
        bank->irqs &= ~rise;
        bank->inputs &= ~(1 << n);
    }
}

/* Simplified version with no edge detection */
static void omap_set_intr_noedge(void *opaque, int irq, int req)
{
    struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
    uint32_t rise;

    struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
    int n = irq & 31;

    if (req) {
        rise = ~bank->inputs & (1 << n);
        if (rise) {
            bank->irqs |= bank->inputs |= rise;
            omap_inth_update(ih, 0);
            omap_inth_update(ih, 1);
        }
    } else
        bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
}

static uint64_t omap_inth_read(void *opaque, hwaddr addr,
                               unsigned size)
{
    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
    int i, offset = addr;
    int bank_no = offset >> 8;
    int line_no;
    struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
    offset &= 0xff;

    switch (offset) {
    case 0x00:	/* ITR */
        return bank->irqs;

    case 0x04:	/* MIR */
        return bank->mask;

    case 0x10:	/* SIR_IRQ_CODE */
    case 0x14:  /* SIR_FIQ_CODE */
        if (bank_no != 0)
            break;
        line_no = s->sir_intr[(offset - 0x10) >> 2];
        bank = &s->bank[line_no >> 5];
        i = line_no & 31;
        if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
            bank->irqs &= ~(1 << i);
        return line_no;

    case 0x18:	/* CONTROL_REG */
        if (bank_no != 0)
            break;
        return 0;

    case 0x1c:	/* ILR0 */
    case 0x20:	/* ILR1 */
    case 0x24:	/* ILR2 */
    case 0x28:	/* ILR3 */
    case 0x2c:	/* ILR4 */
    case 0x30:	/* ILR5 */
    case 0x34:	/* ILR6 */
    case 0x38:	/* ILR7 */
    case 0x3c:	/* ILR8 */
    case 0x40:	/* ILR9 */
    case 0x44:	/* ILR10 */
    case 0x48:	/* ILR11 */
    case 0x4c:	/* ILR12 */
    case 0x50:	/* ILR13 */
    case 0x54:	/* ILR14 */
    case 0x58:	/* ILR15 */
    case 0x5c:	/* ILR16 */
    case 0x60:	/* ILR17 */
    case 0x64:	/* ILR18 */
    case 0x68:	/* ILR19 */
    case 0x6c:	/* ILR20 */
    case 0x70:	/* ILR21 */
    case 0x74:	/* ILR22 */
    case 0x78:	/* ILR23 */
    case 0x7c:	/* ILR24 */
    case 0x80:	/* ILR25 */
    case 0x84:	/* ILR26 */
    case 0x88:	/* ILR27 */
    case 0x8c:	/* ILR28 */
    case 0x90:	/* ILR29 */
    case 0x94:	/* ILR30 */
    case 0x98:	/* ILR31 */
        i = (offset - 0x1c) >> 2;
        return (bank->priority[i] << 2) |
                (((bank->sens_edge >> i) & 1) << 1) |
                ((bank->fiq >> i) & 1);

    case 0x9c:	/* ISR */
        return 0x00000000;

    }
    OMAP_BAD_REG(addr);
    return 0;
}

static void omap_inth_write(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size)
{
    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
    int i, offset = addr;
    int bank_no = offset >> 8;
    struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
    offset &= 0xff;

    switch (offset) {
    case 0x00:	/* ITR */
        /* Important: ignore the clearing if the IRQ is level-triggered and
           the input bit is 1 */
        bank->irqs &= value | (bank->inputs & bank->sens_edge);
        return;

    case 0x04:	/* MIR */
        bank->mask = value;
        omap_inth_update(s, 0);
        omap_inth_update(s, 1);
        return;

    case 0x10:	/* SIR_IRQ_CODE */
    case 0x14:	/* SIR_FIQ_CODE */
        OMAP_RO_REG(addr);
        break;

    case 0x18:	/* CONTROL_REG */
        if (bank_no != 0)
            break;
        if (value & 2) {
            qemu_set_irq(s->parent_intr[1], 0);
            s->new_agr[1] = ~0;
            omap_inth_update(s, 1);
        }
        if (value & 1) {
            qemu_set_irq(s->parent_intr[0], 0);
            s->new_agr[0] = ~0;
            omap_inth_update(s, 0);
        }
        return;

    case 0x1c:	/* ILR0 */
    case 0x20:	/* ILR1 */
    case 0x24:	/* ILR2 */
    case 0x28:	/* ILR3 */
    case 0x2c:	/* ILR4 */
    case 0x30:	/* ILR5 */
    case 0x34:	/* ILR6 */
    case 0x38:	/* ILR7 */
    case 0x3c:	/* ILR8 */
    case 0x40:	/* ILR9 */
    case 0x44:	/* ILR10 */
    case 0x48:	/* ILR11 */
    case 0x4c:	/* ILR12 */
    case 0x50:	/* ILR13 */
    case 0x54:	/* ILR14 */
    case 0x58:	/* ILR15 */
    case 0x5c:	/* ILR16 */
    case 0x60:	/* ILR17 */
    case 0x64:	/* ILR18 */
    case 0x68:	/* ILR19 */
    case 0x6c:	/* ILR20 */
    case 0x70:	/* ILR21 */
    case 0x74:	/* ILR22 */
    case 0x78:	/* ILR23 */
    case 0x7c:	/* ILR24 */
    case 0x80:	/* ILR25 */
    case 0x84:	/* ILR26 */
    case 0x88:	/* ILR27 */
    case 0x8c:	/* ILR28 */
    case 0x90:	/* ILR29 */
    case 0x94:	/* ILR30 */
    case 0x98:	/* ILR31 */
        i = (offset - 0x1c) >> 2;
        bank->priority[i] = (value >> 2) & 0x1f;
        bank->sens_edge &= ~(1 << i);
        bank->sens_edge |= ((value >> 1) & 1) << i;
        bank->fiq &= ~(1 << i);
        bank->fiq |= (value & 1) << i;
        return;

    case 0x9c:	/* ISR */
        for (i = 0; i < 32; i ++)
            if (value & (1 << i)) {
                omap_set_intr(s, 32 * bank_no + i, 1);
                return;
            }
        return;
    }
    OMAP_BAD_REG(addr);
}

static const MemoryRegionOps omap_inth_mem_ops = {
    .read = omap_inth_read,
    .write = omap_inth_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void omap_inth_reset(DeviceState *dev)
{
    struct omap_intr_handler_s *s = OMAP_INTC(dev);
    int i;

    for (i = 0; i < s->nbanks; ++i){
        s->bank[i].irqs = 0x00000000;
        s->bank[i].mask = 0xffffffff;
        s->bank[i].sens_edge = 0x00000000;
        s->bank[i].fiq = 0x00000000;
        s->bank[i].inputs = 0x00000000;
        s->bank[i].swi = 0x00000000;
        memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));

        if (s->level_only)
            s->bank[i].sens_edge = 0xffffffff;
    }

    s->new_agr[0] = ~0;
    s->new_agr[1] = ~0;
    s->sir_intr[0] = 0;
    s->sir_intr[1] = 0;
    s->autoidle = 0;
    s->mask = ~0;

    qemu_set_irq(s->parent_intr[0], 0);
    qemu_set_irq(s->parent_intr[1], 0);
}

static void omap_intc_init(Object *obj)
{
    DeviceState *dev = DEVICE(obj);
    struct omap_intr_handler_s *s = OMAP_INTC(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    s->nbanks = 1;
    sysbus_init_irq(sbd, &s->parent_intr[0]);
    sysbus_init_irq(sbd, &s->parent_intr[1]);
    qdev_init_gpio_in(dev, omap_set_intr, s->nbanks * 32);
    memory_region_init_io(&s->mmio, obj, &omap_inth_mem_ops, s,
                          "omap-intc", s->size);
    sysbus_init_mmio(sbd, &s->mmio);
}

static void omap_intc_realize(DeviceState *dev, Error **errp)
{
    struct omap_intr_handler_s *s = OMAP_INTC(dev);

    if (!s->iclk) {
        error_setg(errp, "omap-intc: clk not connected");
    }
}

static Property omap_intc_properties[] = {
    DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
    DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk),
    DEFINE_PROP_END_OF_LIST(),
};

static void omap_intc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = omap_inth_reset;
    dc->props = omap_intc_properties;
    /* Reason: pointer property "clk" */
    dc->user_creatable = false;
    dc->realize = omap_intc_realize;
}

static const TypeInfo omap_intc_info = {
    .name          = "omap-intc",
    .parent        = TYPE_OMAP_INTC,
    .instance_init = omap_intc_init,
    .class_init    = omap_intc_class_init,
};

static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
                                unsigned size)
{
    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
    int offset = addr;
    int bank_no, line_no;
    struct omap_intr_handler_bank_s *bank = NULL;

    if ((offset & 0xf80) == 0x80) {
        bank_no = (offset & 0x60) >> 5;
        if (bank_no < s->nbanks) {
            offset &= ~0x60;
            bank = &s->bank[bank_no];
        } else {
            OMAP_BAD_REG(addr);
            return 0;
        }
    }

    switch (offset) {
    case 0x00:	/* INTC_REVISION */
        return s->revision;

    case 0x10:	/* INTC_SYSCONFIG */
        return (s->autoidle >> 2) & 1;

    case 0x14:	/* INTC_SYSSTATUS */
        return 1;						/* RESETDONE */

    case 0x40:	/* INTC_SIR_IRQ */
        return s->sir_intr[0];

    case 0x44:	/* INTC_SIR_FIQ */
        return s->sir_intr[1];

    case 0x48:	/* INTC_CONTROL */
        return (!s->mask) << 2;					/* GLOBALMASK */

    case 0x4c:	/* INTC_PROTECTION */
        return 0;

    case 0x50:	/* INTC_IDLE */
        return s->autoidle & 3;

    /* Per-bank registers */
    case 0x80:	/* INTC_ITR */
        return bank->inputs;

    case 0x84:	/* INTC_MIR */
        return bank->mask;

    case 0x88:	/* INTC_MIR_CLEAR */
    case 0x8c:	/* INTC_MIR_SET */
        return 0;

    case 0x90:	/* INTC_ISR_SET */
        return bank->swi;

    case 0x94:	/* INTC_ISR_CLEAR */
        return 0;

    case 0x98:	/* INTC_PENDING_IRQ */
        return bank->irqs & ~bank->mask & ~bank->fiq;

    case 0x9c:	/* INTC_PENDING_FIQ */
        return bank->irqs & ~bank->mask & bank->fiq;

    /* Per-line registers */
    case 0x100 ... 0x300:	/* INTC_ILR */
        bank_no = (offset - 0x100) >> 7;
        if (bank_no > s->nbanks)
            break;
        bank = &s->bank[bank_no];
        line_no = (offset & 0x7f) >> 2;
        return (bank->priority[line_no] << 2) |
                ((bank->fiq >> line_no) & 1);
    }
    OMAP_BAD_REG(addr);
    return 0;
}

static void omap2_inth_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
{
    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
    int offset = addr;
    int bank_no, line_no;
    struct omap_intr_handler_bank_s *bank = NULL;

    if ((offset & 0xf80) == 0x80) {
        bank_no = (offset & 0x60) >> 5;
        if (bank_no < s->nbanks) {
            offset &= ~0x60;
            bank = &s->bank[bank_no];
        } else {
            OMAP_BAD_REG(addr);
            return;
        }
    }

    switch (offset) {
    case 0x10:	/* INTC_SYSCONFIG */
        s->autoidle &= 4;
        s->autoidle |= (value & 1) << 2;
        if (value & 2) {                                        /* SOFTRESET */
            omap_inth_reset(DEVICE(s));
        }
        return;

    case 0x48:	/* INTC_CONTROL */
        s->mask = (value & 4) ? 0 : ~0;				/* GLOBALMASK */
        if (value & 2) {					/* NEWFIQAGR */
            qemu_set_irq(s->parent_intr[1], 0);
            s->new_agr[1] = ~0;
            omap_inth_update(s, 1);
        }
        if (value & 1) {					/* NEWIRQAGR */
            qemu_set_irq(s->parent_intr[0], 0);
            s->new_agr[0] = ~0;
            omap_inth_update(s, 0);
        }
        return;

    case 0x4c:	/* INTC_PROTECTION */
        /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
         * for every register, see Chapter 3 and 4 for privileged mode.  */
        if (value & 1)
            fprintf(stderr, "%s: protection mode enable attempt\n",
                            __func__);
        return;

    case 0x50:	/* INTC_IDLE */
        s->autoidle &= ~3;
        s->autoidle |= value & 3;
        return;

    /* Per-bank registers */
    case 0x84:	/* INTC_MIR */
        bank->mask = value;
        omap_inth_update(s, 0);
        omap_inth_update(s, 1);
        return;

    case 0x88:	/* INTC_MIR_CLEAR */
        bank->mask &= ~value;
        omap_inth_update(s, 0);
        omap_inth_update(s, 1);
        return;

    case 0x8c:	/* INTC_MIR_SET */
        bank->mask |= value;
        return;

    case 0x90:	/* INTC_ISR_SET */
        bank->irqs |= bank->swi |= value;
        omap_inth_update(s, 0);
        omap_inth_update(s, 1);
        return;

    case 0x94:	/* INTC_ISR_CLEAR */
        bank->swi &= ~value;
        bank->irqs = bank->swi & bank->inputs;
        return;

    /* Per-line registers */
    case 0x100 ... 0x300:	/* INTC_ILR */
        bank_no = (offset - 0x100) >> 7;
        if (bank_no > s->nbanks)
            break;
        bank = &s->bank[bank_no];
        line_no = (offset & 0x7f) >> 2;
        bank->priority[line_no] = (value >> 2) & 0x3f;
        bank->fiq &= ~(1 << line_no);
        bank->fiq |= (value & 1) << line_no;
        return;

    case 0x00:	/* INTC_REVISION */
    case 0x14:	/* INTC_SYSSTATUS */
    case 0x40:	/* INTC_SIR_IRQ */
    case 0x44:	/* INTC_SIR_FIQ */
    case 0x80:	/* INTC_ITR */
    case 0x98:	/* INTC_PENDING_IRQ */
    case 0x9c:	/* INTC_PENDING_FIQ */
        OMAP_RO_REG(addr);
        return;
    }
    OMAP_BAD_REG(addr);
}

static const MemoryRegionOps omap2_inth_mem_ops = {
    .read = omap2_inth_read,
    .write = omap2_inth_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void omap2_intc_init(Object *obj)
{
    DeviceState *dev = DEVICE(obj);
    struct omap_intr_handler_s *s = OMAP_INTC(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    s->level_only = 1;
    s->nbanks = 3;
    sysbus_init_irq(sbd, &s->parent_intr[0]);
    sysbus_init_irq(sbd, &s->parent_intr[1]);
    qdev_init_gpio_in(dev, omap_set_intr_noedge, s->nbanks * 32);
    memory_region_init_io(&s->mmio, obj, &omap2_inth_mem_ops, s,
                          "omap2-intc", 0x1000);
    sysbus_init_mmio(sbd, &s->mmio);
}

static void omap2_intc_realize(DeviceState *dev, Error **errp)
{
    struct omap_intr_handler_s *s = OMAP_INTC(dev);

    if (!s->iclk) {
        error_setg(errp, "omap2-intc: iclk not connected");
        return;
    }
    if (!s->fclk) {
        error_setg(errp, "omap2-intc: fclk not connected");
        return;
    }
}

static Property omap2_intc_properties[] = {
    DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
    revision, 0x21),
    DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk),
    DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk),
    DEFINE_PROP_END_OF_LIST(),
};

static void omap2_intc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = omap_inth_reset;
    dc->props = omap2_intc_properties;
    /* Reason: pointer property "iclk", "fclk" */
    dc->user_creatable = false;
    dc->realize = omap2_intc_realize;
}

static const TypeInfo omap2_intc_info = {
    .name          = "omap2-intc",
    .parent        = TYPE_OMAP_INTC,
    .instance_init = omap2_intc_init,
    .class_init    = omap2_intc_class_init,
};

static const TypeInfo omap_intc_type_info = {
    .name          = TYPE_OMAP_INTC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(struct omap_intr_handler_s),
    .abstract      = true,
};

static void omap_intc_register_types(void)
{
    type_register_static(&omap_intc_type_info);
    type_register_static(&omap_intc_info);
    type_register_static(&omap2_intc_info);
}

type_init(omap_intc_register_types)
Commit	Line	Data
7f132a21	1	/*
	2	* TI OMAP interrupt controller emulation.
	3	*
	4	* Copyright (C) 2006-2008 Andrzej Zaborowski <[email protected]>
	5	* Copyright (C) 2007-2008 Nokia Corporation
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 or
	10	* (at your option) version 3 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along
	18	* with this program; if not, see <http://www.gnu.org/licenses/>.
	19	*/
90191d07	20	#include "qemu/osdep.h"
83c9f4ca	21	#include "hw/hw.h"
0d09e41a	22	#include "hw/arm/omap.h"
83c9f4ca	23	#include "hw/sysbus.h"
84a3a53c	24	#include "qemu/error-report.h"
0a750e2a	25	#include "qapi/error.h"
7f132a21	26
	27	/* Interrupt Handlers */
	28	struct omap_intr_handler_bank_s {
	29	uint32_t irqs;
	30	uint32_t inputs;
	31	uint32_t mask;
	32	uint32_t fiq;
	33	uint32_t sens_edge;
	34	uint32_t swi;
	35	unsigned char priority[32];
	36	};
	37
47edc5a4 AF	38	#define TYPE_OMAP_INTC "common-omap-intc"
	39	#define OMAP_INTC(obj) \
	40	OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC)
	41
7f132a21	42	struct omap_intr_handler_s {
47edc5a4 AF	43	SysBusDevice parent_obj;
47edc5a4 AF	44
7f132a21	45	qemu_irq *pins;
7f132a21	46	qemu_irq parent_intr[2];
53bb614e	47	MemoryRegion mmio;
0919ac78 PM	48	void *iclk;
0919ac78 PM	49	void *fclk;
7f132a21	50	unsigned char nbanks;
7f132a21	51	int level_only;
0919ac78 PM	52	uint32_t size;
	53
	54	uint8_t revision;
7f132a21	55
	56	/* state */
	57	uint32_t new_agr[2];
	58	int sir_intr[2];
	59	int autoidle;
	60	uint32_t mask;
0919ac78	61	struct omap_intr_handler_bank_s bank[3];
7f132a21	62	};
7f132a21	63
7f132a21	64	static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
7f132a21	65	{
41074f3d	66	int i, j, sir_intr, p_intr, p;
7f132a21	67	uint32_t level;
	68	sir_intr = 0;
	69	p_intr = 255;
	70
	71	/* Find the interrupt line with the highest dynamic priority.
	72	* Note: 0 denotes the hightest priority.
	73	* If all interrupts have the same priority, the default order is IRQ_N,
	74	* IRQ_N-1,...,IRQ_0. */
	75	for (j = 0; j < s->nbanks; ++j) {
	76	level = s->bank[j].irqs & ~s->bank[j].mask &
	77	(is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
41074f3d PB	78
	79	while (level != 0) {
	80	i = ctz32(level);
7f132a21	81	p = s->bank[j].priority[i];
	82	if (p <= p_intr) {
	83	p_intr = p;
	84	sir_intr = 32 * j + i;
	85	}
41074f3d	86	level &= level - 1;
7f132a21	87	}
	88	}
	89	s->sir_intr[is_fiq] = sir_intr;
	90	}
	91
	92	static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
	93	{
	94	int i;
	95	uint32_t has_intr = 0;
	96
	97	for (i = 0; i < s->nbanks; ++i)
	98	has_intr \|= s->bank[i].irqs & ~s->bank[i].mask &
	99	(is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);
	100
	101	if (s->new_agr[is_fiq] & has_intr & s->mask) {
	102	s->new_agr[is_fiq] = 0;
	103	omap_inth_sir_update(s, is_fiq);
	104	qemu_set_irq(s->parent_intr[is_fiq], 1);
	105	}
	106	}
	107
	108	#define INT_FALLING_EDGE 0
	109	#define INT_LOW_LEVEL 1
	110
	111	static void omap_set_intr(void *opaque, int irq, int req)
	112	{
	113	struct omap_intr_handler_s ih = (struct omap_intr_handler_s ) opaque;
	114	uint32_t rise;
	115
	116	struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
	117	int n = irq & 31;
	118
	119	if (req) {
	120	rise = ~bank->irqs & (1 << n);
	121	if (~bank->sens_edge & (1 << n))
	122	rise &= ~bank->inputs;
	123
	124	bank->inputs \|= (1 << n);
	125	if (rise) {
	126	bank->irqs \|= rise;
	127	omap_inth_update(ih, 0);
	128	omap_inth_update(ih, 1);
	129	}
	130	} else {
	131	rise = bank->sens_edge & bank->irqs & (1 << n);
	132	bank->irqs &= ~rise;
	133	bank->inputs &= ~(1 << n);
	134	}
	135	}
	136
	137	/* Simplified version with no edge detection */
	138	static void omap_set_intr_noedge(void *opaque, int irq, int req)
	139	{
	140	struct omap_intr_handler_s ih = (struct omap_intr_handler_s ) opaque;
	141	uint32_t rise;
	142
	143	struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
	144	int n = irq & 31;
	145
	146	if (req) {
	147	rise = ~bank->inputs & (1 << n);
	148	if (rise) {
	149	bank->irqs \|= bank->inputs \|= rise;
	150	omap_inth_update(ih, 0);
151	omap_inth_update(ih, 1);
152	}
153	} else
154	bank->irqs = (bank->inputs &= ~(1 << n)) \| bank->swi;
155	}
156
a8170e5e	157	static uint64_t omap_inth_read(void *opaque, hwaddr addr,
53bb614e	158	unsigned size)
7f132a21	159	{
	160	struct omap_intr_handler_s s = (struct omap_intr_handler_s ) opaque;
	161	int i, offset = addr;
	162	int bank_no = offset >> 8;
	163	int line_no;
	164	struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
	165	offset &= 0xff;
	166
	167	switch (offset) {
	168	case 0x00: /* ITR */
	169	return bank->irqs;
	170
	171	case 0x04: /* MIR */
	172	return bank->mask;
	173
	174	case 0x10: /* SIR_IRQ_CODE */
	175	case 0x14: /* SIR_FIQ_CODE */
	176	if (bank_no != 0)
	177	break;
	178	line_no = s->sir_intr[(offset - 0x10) >> 2];
	179	bank = &s->bank[line_no >> 5];
	180	i = line_no & 31;
	181	if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
	182	bank->irqs &= ~(1 << i);
	183	return line_no;
	184
	185	case 0x18: /* CONTROL_REG */
	186	if (bank_no != 0)
	187	break;
	188	return 0;
	189
	190	case 0x1c: /* ILR0 */
	191	case 0x20: /* ILR1 */
	192	case 0x24: /* ILR2 */
	193	case 0x28: /* ILR3 */
	194	case 0x2c: /* ILR4 */
	195	case 0x30: /* ILR5 */
	196	case 0x34: /* ILR6 */
	197	case 0x38: /* ILR7 */
	198	case 0x3c: /* ILR8 */
	199	case 0x40: /* ILR9 */
	200	case 0x44: /* ILR10 */
	201	case 0x48: /* ILR11 */
	202	case 0x4c: /* ILR12 */
	203	case 0x50: /* ILR13 */
	204	case 0x54: /* ILR14 */
	205	case 0x58: /* ILR15 */
	206	case 0x5c: /* ILR16 */
	207	case 0x60: /* ILR17 */
	208	case 0x64: /* ILR18 */
	209	case 0x68: /* ILR19 */
	210	case 0x6c: /* ILR20 */
	211	case 0x70: /* ILR21 */
	212	case 0x74: /* ILR22 */
	213	case 0x78: /* ILR23 */
	214	case 0x7c: /* ILR24 */
	215	case 0x80: /* ILR25 */
	216	case 0x84: /* ILR26 */
	217	case 0x88: /* ILR27 */
	218	case 0x8c: /* ILR28 */
	219	case 0x90: /* ILR29 */
	220	case 0x94: /* ILR30 */
	221	case 0x98: /* ILR31 */
	222	i = (offset - 0x1c) >> 2;
223	return (bank->priority[i] << 2) \|
224	(((bank->sens_edge >> i) & 1) << 1) \|
225	((bank->fiq >> i) & 1);
226
227	case 0x9c: /* ISR */
228	return 0x00000000;
229
230	}
231	OMAP_BAD_REG(addr);
232	return 0;
233	}
234
a8170e5e	235	static void omap_inth_write(void *opaque, hwaddr addr,
53bb614e	236	uint64_t value, unsigned size)
7f132a21	237	{
	238	struct omap_intr_handler_s s = (struct omap_intr_handler_s ) opaque;
	239	int i, offset = addr;
	240	int bank_no = offset >> 8;
	241	struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
	242	offset &= 0xff;
	243
	244	switch (offset) {
	245	case 0x00: /* ITR */
	246	/* Important: ignore the clearing if the IRQ is level-triggered and
	247	the input bit is 1 */
	248	bank->irqs &= value \| (bank->inputs & bank->sens_edge);
	249	return;
	250
	251	case 0x04: /* MIR */
	252	bank->mask = value;
	253	omap_inth_update(s, 0);
	254	omap_inth_update(s, 1);
	255	return;
	256
	257	case 0x10: /* SIR_IRQ_CODE */
	258	case 0x14: /* SIR_FIQ_CODE */
	259	OMAP_RO_REG(addr);
	260	break;
	261
	262	case 0x18: /* CONTROL_REG */
	263	if (bank_no != 0)
	264	break;
	265	if (value & 2) {
	266	qemu_set_irq(s->parent_intr[1], 0);
	267	s->new_agr[1] = ~0;
	268	omap_inth_update(s, 1);
	269	}
	270	if (value & 1) {
	271	qemu_set_irq(s->parent_intr[0], 0);
	272	s->new_agr[0] = ~0;
	273	omap_inth_update(s, 0);
	274	}
	275	return;
	276
	277	case 0x1c: /* ILR0 */
	278	case 0x20: /* ILR1 */
	279	case 0x24: /* ILR2 */
	280	case 0x28: /* ILR3 */
	281	case 0x2c: /* ILR4 */
	282	case 0x30: /* ILR5 */
	283	case 0x34: /* ILR6 */
	284	case 0x38: /* ILR7 */
	285	case 0x3c: /* ILR8 */
	286	case 0x40: /* ILR9 */
	287	case 0x44: /* ILR10 */
	288	case 0x48: /* ILR11 */
	289	case 0x4c: /* ILR12 */
	290	case 0x50: /* ILR13 */
	291	case 0x54: /* ILR14 */
	292	case 0x58: /* ILR15 */
	293	case 0x5c: /* ILR16 */
	294	case 0x60: /* ILR17 */
	295	case 0x64: /* ILR18 */
	296	case 0x68: /* ILR19 */
	297	case 0x6c: /* ILR20 */
	298	case 0x70: /* ILR21 */
	299	case 0x74: /* ILR22 */
	300	case 0x78: /* ILR23 */
301	case 0x7c: /* ILR24 */
302	case 0x80: /* ILR25 */
303	case 0x84: /* ILR26 */
304	case 0x88: /* ILR27 */
305	case 0x8c: /* ILR28 */
306	case 0x90: /* ILR29 */
307	case 0x94: /* ILR30 */
308	case 0x98: /* ILR31 */
309	i = (offset - 0x1c) >> 2;
310	bank->priority[i] = (value >> 2) & 0x1f;
311	bank->sens_edge &= ~(1 << i);
312	bank->sens_edge \|= ((value >> 1) & 1) << i;
313	bank->fiq &= ~(1 << i);
314	bank->fiq \|= (value & 1) << i;
315	return;
316
317	case 0x9c: /* ISR */
318	for (i = 0; i < 32; i ++)
319	if (value & (1 << i)) {
320	omap_set_intr(s, 32 * bank_no + i, 1);
321	return;
322	}
323	return;
324	}
325	OMAP_BAD_REG(addr);
326	}
327
53bb614e PM	328	static const MemoryRegionOps omap_inth_mem_ops = {
	329	.read = omap_inth_read,
	330	.write = omap_inth_write,
	331	.endianness = DEVICE_NATIVE_ENDIAN,
	332	.valid = {
	333	.min_access_size = 4,
	334	.max_access_size = 4,
	335	},
7f132a21	336	};
7f132a21	337
0919ac78	338	static void omap_inth_reset(DeviceState *dev)
7f132a21	339	{
47edc5a4	340	struct omap_intr_handler_s *s = OMAP_INTC(dev);
7f132a21	341	int i;
	342
	343	for (i = 0; i < s->nbanks; ++i){
	344	s->bank[i].irqs = 0x00000000;
	345	s->bank[i].mask = 0xffffffff;
	346	s->bank[i].sens_edge = 0x00000000;
	347	s->bank[i].fiq = 0x00000000;
	348	s->bank[i].inputs = 0x00000000;
	349	s->bank[i].swi = 0x00000000;
	350	memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));
	351
	352	if (s->level_only)
	353	s->bank[i].sens_edge = 0xffffffff;
	354	}
	355
	356	s->new_agr[0] = ~0;
	357	s->new_agr[1] = ~0;
	358	s->sir_intr[0] = 0;
	359	s->sir_intr[1] = 0;
	360	s->autoidle = 0;
	361	s->mask = ~0;
	362
	363	qemu_set_irq(s->parent_intr[0], 0);
	364	qemu_set_irq(s->parent_intr[1], 0);
	365	}
	366
0a750e2a	367	static void omap_intc_init(Object *obj)
7f132a21	368	{
0a750e2a XZ	369	DeviceState *dev = DEVICE(obj);
	370	struct omap_intr_handler_s *s = OMAP_INTC(obj);
	371	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
47edc5a4	372
0919ac78	373	s->nbanks = 1;
47edc5a4 AF	374	sysbus_init_irq(sbd, &s->parent_intr[0]);
	375	sysbus_init_irq(sbd, &s->parent_intr[1]);
	376	qdev_init_gpio_in(dev, omap_set_intr, s->nbanks * 32);
0a750e2a	377	memory_region_init_io(&s->mmio, obj, &omap_inth_mem_ops, s,
0919ac78	378	"omap-intc", s->size);
47edc5a4	379	sysbus_init_mmio(sbd, &s->mmio);
0a750e2a XZ	380	}
	381
	382	static void omap_intc_realize(DeviceState dev, Error *errp)
	383	{
	384	struct omap_intr_handler_s *s = OMAP_INTC(dev);
	385
	386	if (!s->iclk) {
	387	error_setg(errp, "omap-intc: clk not connected");
	388	}
7f132a21	389	}
7f132a21	390
999e12bb AL	391	static Property omap_intc_properties[] = {
	392	DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
	393	DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk),
	394	DEFINE_PROP_END_OF_LIST(),
	395	};
	396
	397	static void omap_intc_class_init(ObjectClass klass, void data)
	398	{
39bffca2	399	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	400
39bffca2 AL	401	dc->reset = omap_inth_reset;
39bffca2 AL	402	dc->props = omap_intc_properties;
1b111dc1	403	/* Reason: pointer property "clk" */
e90f2a8c	404	dc->user_creatable = false;
0a750e2a	405	dc->realize = omap_intc_realize;
999e12bb AL	406	}
999e12bb AL	407
8c43a6f0	408	static const TypeInfo omap_intc_info = {
39bffca2	409	.name = "omap-intc",
47edc5a4	410	.parent = TYPE_OMAP_INTC,
0a750e2a	411	.instance_init = omap_intc_init,
39bffca2	412	.class_init = omap_intc_class_init,
0919ac78 PM	413	};
0919ac78 PM	414
a8170e5e	415	static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
53bb614e	416	unsigned size)
7f132a21	417	{
	418	struct omap_intr_handler_s s = (struct omap_intr_handler_s ) opaque;
	419	int offset = addr;
	420	int bank_no, line_no;
	421	struct omap_intr_handler_bank_s *bank = NULL;
	422
	423	if ((offset & 0xf80) == 0x80) {
	424	bank_no = (offset & 0x60) >> 5;
	425	if (bank_no < s->nbanks) {
	426	offset &= ~0x60;
	427	bank = &s->bank[bank_no];
096685fc PM	428	} else {
	429	OMAP_BAD_REG(addr);
	430	return 0;
7f132a21	431	}
	432	}
	433
	434	switch (offset) {
	435	case 0x00: /* INTC_REVISION */
0919ac78	436	return s->revision;
7f132a21	437
	438	case 0x10: /* INTC_SYSCONFIG */
	439	return (s->autoidle >> 2) & 1;
	440
	441	case 0x14: /* INTC_SYSSTATUS */
	442	return 1; /* RESETDONE */
	443
	444	case 0x40: /* INTC_SIR_IRQ */
	445	return s->sir_intr[0];
	446
	447	case 0x44: /* INTC_SIR_FIQ */
	448	return s->sir_intr[1];
	449
	450	case 0x48: /* INTC_CONTROL */
	451	return (!s->mask) << 2; /* GLOBALMASK */
	452
	453	case 0x4c: /* INTC_PROTECTION */
	454	return 0;
	455
	456	case 0x50: /* INTC_IDLE */
	457	return s->autoidle & 3;
	458
	459	/* Per-bank registers */
	460	case 0x80: /* INTC_ITR */
	461	return bank->inputs;
	462
	463	case 0x84: /* INTC_MIR */
	464	return bank->mask;
	465
	466	case 0x88: /* INTC_MIR_CLEAR */
	467	case 0x8c: /* INTC_MIR_SET */
	468	return 0;
	469
	470	case 0x90: /* INTC_ISR_SET */
	471	return bank->swi;
	472
	473	case 0x94: /* INTC_ISR_CLEAR */
	474	return 0;
	475
	476	case 0x98: /* INTC_PENDING_IRQ */
	477	return bank->irqs & ~bank->mask & ~bank->fiq;
	478
	479	case 0x9c: /* INTC_PENDING_FIQ */
	480	return bank->irqs & ~bank->mask & bank->fiq;
	481
	482	/* Per-line registers */
	483	case 0x100 ... 0x300: /* INTC_ILR */
	484	bank_no = (offset - 0x100) >> 7;
	485	if (bank_no > s->nbanks)
	486	break;
	487	bank = &s->bank[bank_no];
	488	line_no = (offset & 0x7f) >> 2;
	489	return (bank->priority[line_no] << 2) \|
	490	((bank->fiq >> line_no) & 1);
	491	}
	492	OMAP_BAD_REG(addr);
	493	return 0;
	494	}
	495
a8170e5e	496	static void omap2_inth_write(void *opaque, hwaddr addr,
53bb614e	497	uint64_t value, unsigned size)
7f132a21	498	{
	499	struct omap_intr_handler_s s = (struct omap_intr_handler_s ) opaque;
	500	int offset = addr;
	501	int bank_no, line_no;
	502	struct omap_intr_handler_bank_s *bank = NULL;
	503
	504	if ((offset & 0xf80) == 0x80) {
	505	bank_no = (offset & 0x60) >> 5;
	506	if (bank_no < s->nbanks) {
	507	offset &= ~0x60;
	508	bank = &s->bank[bank_no];
096685fc PM	509	} else {
	510	OMAP_BAD_REG(addr);
	511	return;
7f132a21	512	}
	513	}
	514
	515	switch (offset) {
	516	case 0x10: /* INTC_SYSCONFIG */
	517	s->autoidle &= 4;
	518	s->autoidle \|= (value & 1) << 2;
47edc5a4 AF	519	if (value & 2) { /* SOFTRESET */
	520	omap_inth_reset(DEVICE(s));
	521	}
7f132a21	522	return;
	523
	524	case 0x48: /* INTC_CONTROL */
	525	s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */
	526	if (value & 2) { /* NEWFIQAGR */
	527	qemu_set_irq(s->parent_intr[1], 0);
	528	s->new_agr[1] = ~0;
	529	omap_inth_update(s, 1);
	530	}
	531	if (value & 1) { /* NEWIRQAGR */
	532	qemu_set_irq(s->parent_intr[0], 0);
	533	s->new_agr[0] = ~0;
	534	omap_inth_update(s, 0);
	535	}
	536	return;
	537
	538	case 0x4c: /* INTC_PROTECTION */
	539	/* TODO: Make a bitmap (or sizeof(char)map) of access privileges
	540	* for every register, see Chapter 3 and 4 for privileged mode. */
	541	if (value & 1)
	542	fprintf(stderr, "%s: protection mode enable attempt\n",
a89f364a	543	__func__);
7f132a21	544	return;
	545
	546	case 0x50: /* INTC_IDLE */
	547	s->autoidle &= ~3;
	548	s->autoidle \|= value & 3;
	549	return;
	550
	551	/* Per-bank registers */
	552	case 0x84: /* INTC_MIR */
	553	bank->mask = value;
	554	omap_inth_update(s, 0);
	555	omap_inth_update(s, 1);
	556	return;
	557
	558	case 0x88: /* INTC_MIR_CLEAR */
	559	bank->mask &= ~value;
	560	omap_inth_update(s, 0);
	561	omap_inth_update(s, 1);
	562	return;
	563
	564	case 0x8c: /* INTC_MIR_SET */
	565	bank->mask \|= value;
	566	return;
	567
	568	case 0x90: /* INTC_ISR_SET */
	569	bank->irqs \|= bank->swi \|= value;
	570	omap_inth_update(s, 0);
	571	omap_inth_update(s, 1);
	572	return;
	573
	574	case 0x94: /* INTC_ISR_CLEAR */
	575	bank->swi &= ~value;
	576	bank->irqs = bank->swi & bank->inputs;
	577	return;
	578
	579	/* Per-line registers */
	580	case 0x100 ... 0x300: /* INTC_ILR */
	581	bank_no = (offset - 0x100) >> 7;
	582	if (bank_no > s->nbanks)
	583	break;
	584	bank = &s->bank[bank_no];
	585	line_no = (offset & 0x7f) >> 2;
	586	bank->priority[line_no] = (value >> 2) & 0x3f;
	587	bank->fiq &= ~(1 << line_no);
	588	bank->fiq \|= (value & 1) << line_no;
	589	return;
	590
	591	case 0x00: /* INTC_REVISION */
	592	case 0x14: /* INTC_SYSSTATUS */
	593	case 0x40: /* INTC_SIR_IRQ */
	594	case 0x44: /* INTC_SIR_FIQ */
	595	case 0x80: /* INTC_ITR */
	596	case 0x98: /* INTC_PENDING_IRQ */
	597	case 0x9c: /* INTC_PENDING_FIQ */
	598	OMAP_RO_REG(addr);
	599	return;
	600	}
	601	OMAP_BAD_REG(addr);
	602	}
	603
53bb614e PM	604	static const MemoryRegionOps omap2_inth_mem_ops = {
	605	.read = omap2_inth_read,
	606	.write = omap2_inth_write,
	607	.endianness = DEVICE_NATIVE_ENDIAN,
	608	.valid = {
	609	.min_access_size = 4,
	610	.max_access_size = 4,
	611	},
7f132a21	612	};
7f132a21	613
0a750e2a	614	static void omap2_intc_init(Object *obj)
7f132a21	615	{
0a750e2a XZ	616	DeviceState *dev = DEVICE(obj);
	617	struct omap_intr_handler_s *s = OMAP_INTC(obj);
	618	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
47edc5a4	619
7f132a21	620	s->level_only = 1;
0919ac78	621	s->nbanks = 3;
47edc5a4 AF	622	sysbus_init_irq(sbd, &s->parent_intr[0]);
	623	sysbus_init_irq(sbd, &s->parent_intr[1]);
	624	qdev_init_gpio_in(dev, omap_set_intr_noedge, s->nbanks * 32);
0a750e2a	625	memory_region_init_io(&s->mmio, obj, &omap2_inth_mem_ops, s,
0919ac78	626	"omap2-intc", 0x1000);
47edc5a4	627	sysbus_init_mmio(sbd, &s->mmio);
0a750e2a XZ	628	}
	629
	630	static void omap2_intc_realize(DeviceState dev, Error *errp)
	631	{
	632	struct omap_intr_handler_s *s = OMAP_INTC(dev);
	633
	634	if (!s->iclk) {
	635	error_setg(errp, "omap2-intc: iclk not connected");
	636	return;
	637	}
	638	if (!s->fclk) {
	639	error_setg(errp, "omap2-intc: fclk not connected");
	640	return;
	641	}
0919ac78	642	}
7f132a21	643
999e12bb AL	644	static Property omap2_intc_properties[] = {
	645	DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
	646	revision, 0x21),
	647	DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk),
	648	DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk),
	649	DEFINE_PROP_END_OF_LIST(),
	650	};
	651
	652	static void omap2_intc_class_init(ObjectClass klass, void data)
	653	{
39bffca2	654	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	655
39bffca2 AL	656	dc->reset = omap_inth_reset;
39bffca2 AL	657	dc->props = omap2_intc_properties;
1b111dc1	658	/* Reason: pointer property "iclk", "fclk" */
e90f2a8c	659	dc->user_creatable = false;
0a750e2a	660	dc->realize = omap2_intc_realize;
999e12bb AL	661	}
999e12bb AL	662
8c43a6f0	663	static const TypeInfo omap2_intc_info = {
39bffca2	664	.name = "omap2-intc",
47edc5a4	665	.parent = TYPE_OMAP_INTC,
0a750e2a	666	.instance_init = omap2_intc_init,
47edc5a4 AF	667	.class_init = omap2_intc_class_init,
	668	};
	669
	670	static const TypeInfo omap_intc_type_info = {
	671	.name = TYPE_OMAP_INTC,
39bffca2 AL	672	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	673	.instance_size = sizeof(struct omap_intr_handler_s),
47edc5a4	674	.abstract = true,
0919ac78	675	};
7f132a21	676
83f7d43a	677	static void omap_intc_register_types(void)
0919ac78	678	{
47edc5a4	679	type_register_static(&omap_intc_type_info);
39bffca2 AL	680	type_register_static(&omap_intc_info);
39bffca2 AL	681	type_register_static(&omap2_intc_info);
7f132a21	682	}
0919ac78	683
83f7d43a	684	type_init(omap_intc_register_types)