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b9adb4a6 1/* ppc-dis.c -- Disassemble PowerPC instructions
eca8f888
BS		 2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
b9adb4a6
FB		 4 Written by Ian Lance Taylor, Cygnus Support
5
6This file is part of GDB, GAS, and the GNU binutils.
7
8GDB, GAS, and the GNU binutils are free software; you can redistribute
9them and/or modify them under the terms of the GNU General Public
10License as published by the Free Software Foundation; either version
112, or (at your option) any later version.
12
13GDB, GAS, and the GNU binutils are distributed in the hope that they
14will be useful, but WITHOUT ANY WARRANTY; without even the implied
15warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16the GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this file; see the file COPYING. If not, write to the Free
fad6cb1a 20Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
b9adb4a6 21#include "dis-asm.h"
eca8f888 22#define BFD_DEFAULT_TARGET_SIZE 64
b9adb4a6
FB		 23
24/* ppc.h -- Header file for PowerPC opcode table
eca8f888
BS		 25 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005
26 Free Software Foundation, Inc.
b9adb4a6
FB		 27 Written by Ian Lance Taylor, Cygnus Support
28
29This file is part of GDB, GAS, and the GNU binutils.
30
31GDB, GAS, and the GNU binutils are free software; you can redistribute
32them and/or modify them under the terms of the GNU General Public
33License as published by the Free Software Foundation; either version
341, or (at your option) any later version.
35
36GDB, GAS, and the GNU binutils are distributed in the hope that they
37will be useful, but WITHOUT ANY WARRANTY; without even the implied
38warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
39the GNU General Public License for more details.
40
41You should have received a copy of the GNU General Public License
42along with this file; see the file COPYING. If not, write to the Free
eca8f888 43Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
b9adb4a6
FB		 44
45/* The opcode table is an array of struct powerpc_opcode. */
46
47struct powerpc_opcode
48{
49 /* The opcode name. */
50 const char *name;
51
52 /* The opcode itself. Those bits which will be filled in with
53 operands are zeroes. */
eca8f888 54 unsigned long opcode;
b9adb4a6
FB		 55
56 /* The opcode mask. This is used by the disassembler. This is a
57 mask containing ones indicating those bits which must match the
58 opcode field, and zeroes indicating those bits which need not
59 match (and are presumably filled in by operands). */
eca8f888 60 unsigned long mask;
b9adb4a6
FB		 61
62 /* One bit flags for the opcode. These are used to indicate which
63 specific processors support the instructions. The defined values
64 are listed below. */
eca8f888 65 unsigned long flags;
b9adb4a6
FB		 66
67 /* An array of operand codes. Each code is an index into the
68 operand table. They appear in the order which the operands must
69 appear in assembly code, and are terminated by a zero. */
70 unsigned char operands[8];
71};
72
73/* The table itself is sorted by major opcode number, and is otherwise
74 in the order in which the disassembler should consider
75 instructions. */
76extern const struct powerpc_opcode powerpc_opcodes[];
77extern const int powerpc_num_opcodes;
78
79/* Values defined for the flags field of a struct powerpc_opcode. */
80
81/* Opcode is defined for the PowerPC architecture. */
eca8f888 82#define PPC_OPCODE_PPC 1
b9adb4a6
FB		 83
84/* Opcode is defined for the POWER (RS/6000) architecture. */
eca8f888 85#define PPC_OPCODE_POWER 2
b9adb4a6
FB		 86
87/* Opcode is defined for the POWER2 (Rios 2) architecture. */
eca8f888 88#define PPC_OPCODE_POWER2 4
b9adb4a6
FB		 89
90/* Opcode is only defined on 32 bit architectures. */
eca8f888 91#define PPC_OPCODE_32 8
b9adb4a6
FB		 92
93/* Opcode is only defined on 64 bit architectures. */
eca8f888 94#define PPC_OPCODE_64 0x10
b9adb4a6
FB		 95
96/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
97 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
98 but it also supports many additional POWER instructions. */
eca8f888
BS		 99#define PPC_OPCODE_601 0x20
100
101/* Opcode is supported in both the Power and PowerPC architectures
102 (ie, compiler's -mcpu=common or assembler's -mcom). */
103#define PPC_OPCODE_COMMON 0x40
104
105/* Opcode is supported for any Power or PowerPC platform (this is
106 for the assembler's -many option, and it eliminates duplicates). */
107#define PPC_OPCODE_ANY 0x80
108
109/* Opcode is supported as part of the 64-bit bridge. */
110#define PPC_OPCODE_64_BRIDGE 0x100
111
112/* Opcode is supported by Altivec Vector Unit */
113#define PPC_OPCODE_ALTIVEC 0x200
114
115/* Opcode is supported by PowerPC 403 processor. */
116#define PPC_OPCODE_403 0x400
117
118/* Opcode is supported by PowerPC BookE processor. */
119#define PPC_OPCODE_BOOKE 0x800
120
121/* Opcode is only supported by 64-bit PowerPC BookE processor. */
122#define PPC_OPCODE_BOOKE64 0x1000
123
124/* Opcode is supported by PowerPC 440 processor. */
125#define PPC_OPCODE_440 0x2000
126
127/* Opcode is only supported by Power4 architecture. */
128#define PPC_OPCODE_POWER4 0x4000
129
130/* Opcode isn't supported by Power4 architecture. */
131#define PPC_OPCODE_NOPOWER4 0x8000
132
133/* Opcode is only supported by POWERPC Classic architecture. */
134#define PPC_OPCODE_CLASSIC 0x10000
135
136/* Opcode is only supported by e500x2 Core. */
137#define PPC_OPCODE_SPE 0x20000
138
139/* Opcode is supported by e500x2 Integer select APU. */
140#define PPC_OPCODE_ISEL 0x40000
141
142/* Opcode is an e500 SPE floating point instruction. */
143#define PPC_OPCODE_EFS 0x80000
144
145/* Opcode is supported by branch locking APU. */
146#define PPC_OPCODE_BRLOCK 0x100000
147
148/* Opcode is supported by performance monitor APU. */
149#define PPC_OPCODE_PMR 0x200000
150
151/* Opcode is supported by cache locking APU. */
152#define PPC_OPCODE_CACHELCK 0x400000
153
154/* Opcode is supported by machine check APU. */
155#define PPC_OPCODE_RFMCI 0x800000
156
157/* Opcode is only supported by Power5 architecture. */
158#define PPC_OPCODE_POWER5 0x1000000
159
160/* Opcode is supported by PowerPC e300 family. */
161#define PPC_OPCODE_E300 0x2000000
b9adb4a6
FB		 162
163/* A macro to extract the major opcode from an instruction. */
164#define PPC_OP(i) (((i) >> 26) & 0x3f)
165\f
166/* The operands table is an array of struct powerpc_operand. */
167
168struct powerpc_operand
169{
170 /* The number of bits in the operand. */
171 int bits;
172
173 /* How far the operand is left shifted in the instruction. */
174 int shift;
175
176 /* Insertion function. This is used by the assembler. To insert an
177 operand value into an instruction, check this field.
178
179 If it is NULL, execute
eca8f888 180 i |= (op & ((1 << o->bits) - 1)) << o->shift;
b9adb4a6
FB		 181 (i is the instruction which we are filling in, o is a pointer to
182 this structure, and op is the opcode value; this assumes twos
183 complement arithmetic).
184
185 If this field is not NULL, then simply call it with the
186 instruction and the operand value. It will return the new value
187 of the instruction. If the ERRMSG argument is not NULL, then if
188 the operand value is illegal, *ERRMSG will be set to a warning
189 string (the operand will be inserted in any case). If the
190 operand value is legal, *ERRMSG will be unchanged (most operands
191 can accept any value). */
eca8f888
BS		 192 unsigned long (*insert)
193 (unsigned long instruction, long op, int dialect, const char **errmsg);
b9adb4a6
FB		 194
195 /* Extraction function. This is used by the disassembler. To
196 extract this operand type from an instruction, check this field.
197
198 If it is NULL, compute
eca8f888 199 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
b9adb4a6
FB		 200 if ((o->flags & PPC_OPERAND_SIGNED) != 0
201 && (op & (1 << (o->bits - 1))) != 0)
202 op -= 1 << o->bits;
203 (i is the instruction, o is a pointer to this structure, and op
204 is the result; this assumes twos complement arithmetic).
205
206 If this field is not NULL, then simply call it with the
207 instruction value. It will return the value of the operand. If
208 the INVALID argument is not NULL, *INVALID will be set to
209 non-zero if this operand type can not actually be extracted from
210 this operand (i.e., the instruction does not match). If the
211 operand is valid, *INVALID will not be changed. */
eca8f888 212 long (*extract) (unsigned long instruction, int dialect, int *invalid);
b9adb4a6
FB		 213
214 /* One bit syntax flags. */
eca8f888 215 unsigned long flags;
b9adb4a6
FB		 216};
217
218/* Elements in the table are retrieved by indexing with values from
219 the operands field of the powerpc_opcodes table. */
220
221extern const struct powerpc_operand powerpc_operands[];
222
223/* Values defined for the flags field of a struct powerpc_operand. */
224
225/* This operand takes signed values. */
226#define PPC_OPERAND_SIGNED (01)
227
228/* This operand takes signed values, but also accepts a full positive
229 range of values when running in 32 bit mode. That is, if bits is
230 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
231 this flag is ignored. */
232#define PPC_OPERAND_SIGNOPT (02)
233
234/* This operand does not actually exist in the assembler input. This
235 is used to support extended mnemonics such as mr, for which two
236 operands fields are identical. The assembler should call the
237 insert function with any op value. The disassembler should call
238 the extract function, ignore the return value, and check the value
239 placed in the valid argument. */
240#define PPC_OPERAND_FAKE (04)
241
242/* The next operand should be wrapped in parentheses rather than
243 separated from this one by a comma. This is used for the load and
244 store instructions which want their operands to look like
245 reg,displacement(reg)
246 */
247#define PPC_OPERAND_PARENS (010)
248
249/* This operand may use the symbolic names for the CR fields, which
250 are
251 lt 0 gt 1 eq 2 so 3 un 3
252 cr0 0 cr1 1 cr2 2 cr3 3
253 cr4 4 cr5 5 cr6 6 cr7 7
254 These may be combined arithmetically, as in cr2*4+gt. These are
255 only supported on the PowerPC, not the POWER. */
256#define PPC_OPERAND_CR (020)
257
258/* This operand names a register. The disassembler uses this to print
259 register names with a leading 'r'. */
260#define PPC_OPERAND_GPR (040)
261
eca8f888
BS		 262/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
263#define PPC_OPERAND_GPR_0 (0100)
264
b9adb4a6
FB		 265/* This operand names a floating point register. The disassembler
266 prints these with a leading 'f'. */
eca8f888 267#define PPC_OPERAND_FPR (0200)
b9adb4a6
FB		 268
269/* This operand is a relative branch displacement. The disassembler
270 prints these symbolically if possible. */
eca8f888 271#define PPC_OPERAND_RELATIVE (0400)
b9adb4a6
FB		 272
273/* This operand is an absolute branch address. The disassembler
274 prints these symbolically if possible. */
eca8f888 275#define PPC_OPERAND_ABSOLUTE (01000)
b9adb4a6
FB		 276
277/* This operand is optional, and is zero if omitted. This is used for
eca8f888 278 example, in the optional BF field in the comparison instructions. The
b9adb4a6
FB		 279 assembler must count the number of operands remaining on the line,
280 and the number of operands remaining for the opcode, and decide
281 whether this operand is present or not. The disassembler should
282 print this operand out only if it is not zero. */
eca8f888 283#define PPC_OPERAND_OPTIONAL (02000)
b9adb4a6
FB		 284
285/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
286 is omitted, then for the next operand use this operand value plus
287 1, ignoring the next operand field for the opcode. This wretched
288 hack is needed because the Power rotate instructions can take
289 either 4 or 5 operands. The disassembler should print this operand
290 out regardless of the PPC_OPERAND_OPTIONAL field. */
eca8f888 291#define PPC_OPERAND_NEXT (04000)
b9adb4a6
FB		 292
293/* This operand should be regarded as a negative number for the
294 purposes of overflow checking (i.e., the normal most negative
295 number is disallowed and one more than the normal most positive
296 number is allowed). This flag will only be set for a signed
297 operand. */
eca8f888
BS		 298#define PPC_OPERAND_NEGATIVE (010000)
299
300/* This operand names a vector unit register. The disassembler
301 prints these with a leading 'v'. */
302#define PPC_OPERAND_VR (020000)
303
304/* This operand is for the DS field in a DS form instruction. */
305#define PPC_OPERAND_DS (040000)
306
307/* This operand is for the DQ field in a DQ form instruction. */
308#define PPC_OPERAND_DQ (0100000)
b9adb4a6
FB		 309\f
310/* The POWER and PowerPC assemblers use a few macros. We keep them
311 with the operands table for simplicity. The macro table is an
312 array of struct powerpc_macro. */
313
314struct powerpc_macro
315{
316 /* The macro name. */
317 const char *name;
318
319 /* The number of operands the macro takes. */
320 unsigned int operands;
321
322 /* One bit flags for the opcode. These are used to indicate which
323 specific processors support the instructions. The values are the
324 same as those for the struct powerpc_opcode flags field. */
eca8f888 325 unsigned long flags;
b9adb4a6
FB		 326
327 /* A format string to turn the macro into a normal instruction.
328 Each %N in the string is replaced with operand number N (zero
329 based). */
330 const char *format;
331};
332
333extern const struct powerpc_macro powerpc_macros[];
334extern const int powerpc_num_macros;
335
336/* ppc-opc.c -- PowerPC opcode list
eca8f888
BS		 337 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
338 2005 Free Software Foundation, Inc.
b9adb4a6
FB		 339 Written by Ian Lance Taylor, Cygnus Support
340
eca8f888 341 This file is part of GDB, GAS, and the GNU binutils.
b9adb4a6 342
eca8f888
BS		 343 GDB, GAS, and the GNU binutils are free software; you can redistribute
344 them and/or modify them under the terms of the GNU General Public
345 License as published by the Free Software Foundation; either version
346 2, or (at your option) any later version.
b9adb4a6 347
eca8f888
BS		 348 GDB, GAS, and the GNU binutils are distributed in the hope that they
349 will be useful, but WITHOUT ANY WARRANTY; without even the implied
350 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
351 the GNU General Public License for more details.
b9adb4a6 352
eca8f888
BS		 353 You should have received a copy of the GNU General Public License
354 along with this file; see the file COPYING. If not, write to the Free
355 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
356 02110-1301, USA. */
b9adb4a6
FB		 357
358/* This file holds the PowerPC opcode table. The opcode table
359 includes almost all of the extended instruction mnemonics. This
360 permits the disassembler to use them, and simplifies the assembler
361 logic, at the cost of increasing the table size. The table is
362 strictly constant data, so the compiler should be able to put it in
363 the .text section.
364
365 This file also holds the operand table. All knowledge about
366 inserting operands into instructions and vice-versa is kept in this
367 file. */
368\f
369/* Local insertion and extraction functions. */
370
eca8f888
BS		 371static unsigned long insert_bat (unsigned long, long, int, const char **);
372static long extract_bat (unsigned long, int, int *);
373static unsigned long insert_bba (unsigned long, long, int, const char **);
374static long extract_bba (unsigned long, int, int *);
375static unsigned long insert_bd (unsigned long, long, int, const char **);
376static long extract_bd (unsigned long, int, int *);
377static unsigned long insert_bdm (unsigned long, long, int, const char **);
378static long extract_bdm (unsigned long, int, int *);
379static unsigned long insert_bdp (unsigned long, long, int, const char **);
380static long extract_bdp (unsigned long, int, int *);
381static unsigned long insert_bo (unsigned long, long, int, const char **);
382static long extract_bo (unsigned long, int, int *);
383static unsigned long insert_boe (unsigned long, long, int, const char **);
384static long extract_boe (unsigned long, int, int *);
385static unsigned long insert_dq (unsigned long, long, int, const char **);
386static long extract_dq (unsigned long, int, int *);
387static unsigned long insert_ds (unsigned long, long, int, const char **);
388static long extract_ds (unsigned long, int, int *);
389static unsigned long insert_de (unsigned long, long, int, const char **);
390static long extract_de (unsigned long, int, int *);
391static unsigned long insert_des (unsigned long, long, int, const char **);
392static long extract_des (unsigned long, int, int *);
393static unsigned long insert_fxm (unsigned long, long, int, const char **);
394static long extract_fxm (unsigned long, int, int *);
395static unsigned long insert_li (unsigned long, long, int, const char **);
396static long extract_li (unsigned long, int, int *);
397static unsigned long insert_mbe (unsigned long, long, int, const char **);
398static long extract_mbe (unsigned long, int, int *);
399static unsigned long insert_mb6 (unsigned long, long, int, const char **);
400static long extract_mb6 (unsigned long, int, int *);
401static unsigned long insert_nb (unsigned long, long, int, const char **);
402static long extract_nb (unsigned long, int, int *);
403static unsigned long insert_nsi (unsigned long, long, int, const char **);
404static long extract_nsi (unsigned long, int, int *);
405static unsigned long insert_ral (unsigned long, long, int, const char **);
406static unsigned long insert_ram (unsigned long, long, int, const char **);
407static unsigned long insert_raq (unsigned long, long, int, const char **);
408static unsigned long insert_ras (unsigned long, long, int, const char **);
409static unsigned long insert_rbs (unsigned long, long, int, const char **);
410static long extract_rbs (unsigned long, int, int *);
411static unsigned long insert_rsq (unsigned long, long, int, const char **);
412static unsigned long insert_rtq (unsigned long, long, int, const char **);
413static unsigned long insert_sh6 (unsigned long, long, int, const char **);
414static long extract_sh6 (unsigned long, int, int *);
415static unsigned long insert_spr (unsigned long, long, int, const char **);
416static long extract_spr (unsigned long, int, int *);
417static unsigned long insert_sprg (unsigned long, long, int, const char **);
418static long extract_sprg (unsigned long, int, int *);
419static unsigned long insert_tbr (unsigned long, long, int, const char **);
420static long extract_tbr (unsigned long, int, int *);
421static unsigned long insert_ev2 (unsigned long, long, int, const char **);
422static long extract_ev2 (unsigned long, int, int *);
423static unsigned long insert_ev4 (unsigned long, long, int, const char **);
424static long extract_ev4 (unsigned long, int, int *);
425static unsigned long insert_ev8 (unsigned long, long, int, const char **);
426static long extract_ev8 (unsigned long, int, int *);
b9adb4a6
FB		 427\f
428/* The operands table.
429
eca8f888
BS		 430 The fields are bits, shift, insert, extract, flags.
431
432 We used to put parens around the various additions, like the one
433 for BA just below. However, that caused trouble with feeble
434 compilers with a limit on depth of a parenthesized expression, like
435 (reportedly) the compiler in Microsoft Developer Studio 5. So we
436 omit the parens, since the macros are never used in a context where
437 the addition will be ambiguous. */
b9adb4a6
FB		 438
439const struct powerpc_operand powerpc_operands[] =
440{
441 /* The zero index is used to indicate the end of the list of
442 operands. */
eca8f888
BS		 443#define UNUSED 0
444 { 0, 0, NULL, NULL, 0 },
b9adb4a6
FB		 445
446 /* The BA field in an XL form instruction. */
eca8f888 447#define BA UNUSED + 1
b9adb4a6 448#define BA_MASK (0x1f << 16)
eca8f888 449 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
b9adb4a6
FB		 450
451 /* The BA field in an XL form instruction when it must be the same
452 as the BT field in the same instruction. */
eca8f888 453#define BAT BA + 1
b9adb4a6
FB		 454 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
455
456 /* The BB field in an XL form instruction. */
eca8f888 457#define BB BAT + 1
b9adb4a6 458#define BB_MASK (0x1f << 11)
eca8f888 459 { 5, 11, NULL, NULL, PPC_OPERAND_CR },
b9adb4a6
FB		 460
461 /* The BB field in an XL form instruction when it must be the same
462 as the BA field in the same instruction. */
eca8f888 463#define BBA BB + 1
b9adb4a6
FB		 464 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
465
466 /* The BD field in a B form instruction. The lower two bits are
467 forced to zero. */
eca8f888 468#define BD BBA + 1
b9adb4a6
FB		 469 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
470
471 /* The BD field in a B form instruction when absolute addressing is
472 used. */
eca8f888 473#define BDA BD + 1
b9adb4a6
FB		 474 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
475
476 /* The BD field in a B form instruction when the - modifier is used.
477 This sets the y bit of the BO field appropriately. */
eca8f888 478#define BDM BDA + 1
b9adb4a6
FB		 479 { 16, 0, insert_bdm, extract_bdm,
480 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
481
482 /* The BD field in a B form instruction when the - modifier is used
483 and absolute address is used. */
eca8f888 484#define BDMA BDM + 1
b9adb4a6
FB		 485 { 16, 0, insert_bdm, extract_bdm,
486 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
487
488 /* The BD field in a B form instruction when the + modifier is used.
489 This sets the y bit of the BO field appropriately. */
eca8f888 490#define BDP BDMA + 1
b9adb4a6
FB		 491 { 16, 0, insert_bdp, extract_bdp,
492 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
493
494 /* The BD field in a B form instruction when the + modifier is used
495 and absolute addressing is used. */
eca8f888 496#define BDPA BDP + 1
b9adb4a6
FB		 497 { 16, 0, insert_bdp, extract_bdp,
498 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
499
500 /* The BF field in an X or XL form instruction. */
eca8f888
BS		 501#define BF BDPA + 1
502 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
b9adb4a6
FB		 503
504 /* An optional BF field. This is used for comparison instructions,
505 in which an omitted BF field is taken as zero. */
eca8f888
BS		 506#define OBF BF + 1
507 { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 508
509 /* The BFA field in an X or XL form instruction. */
eca8f888
BS		 510#define BFA OBF + 1
511 { 3, 18, NULL, NULL, PPC_OPERAND_CR },
b9adb4a6
FB		 512
513 /* The BI field in a B form or XL form instruction. */
eca8f888 514#define BI BFA + 1
b9adb4a6 515#define BI_MASK (0x1f << 16)
eca8f888 516 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
b9adb4a6
FB		 517
518 /* The BO field in a B form instruction. Certain values are
519 illegal. */
eca8f888 520#define BO BI + 1
b9adb4a6
FB		 521#define BO_MASK (0x1f << 21)
522 { 5, 21, insert_bo, extract_bo, 0 },
523
524 /* The BO field in a B form instruction when the + or - modifier is
525 used. This is like the BO field, but it must be even. */
eca8f888 526#define BOE BO + 1
b9adb4a6
FB		 527 { 5, 21, insert_boe, extract_boe, 0 },
528
eca8f888
BS		 529#define BH BOE + 1
530 { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
531
b9adb4a6 532 /* The BT field in an X or XL form instruction. */
eca8f888
BS		 533#define BT BH + 1
534 { 5, 21, NULL, NULL, PPC_OPERAND_CR },
b9adb4a6
FB		 535
536 /* The condition register number portion of the BI field in a B form
537 or XL form instruction. This is used for the extended
538 conditional branch mnemonics, which set the lower two bits of the
539 BI field. This field is optional. */
eca8f888
BS		 540#define CR BT + 1
541 { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
542
543 /* The CRB field in an X form instruction. */
544#define CRB CR + 1
545 { 5, 6, NULL, NULL, 0 },
546
547 /* The CRFD field in an X form instruction. */
548#define CRFD CRB + 1
549 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
550
551 /* The CRFS field in an X form instruction. */
552#define CRFS CRFD + 1
553 { 3, 0, NULL, NULL, PPC_OPERAND_CR },
554
555 /* The CT field in an X form instruction. */
556#define CT CRFS + 1
557 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 558
559 /* The D field in a D form instruction. This is a displacement off
560 a register, and implies that the next operand is a register in
561 parentheses. */
eca8f888
BS		 562#define D CT + 1
563 { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
564
565 /* The DE field in a DE form instruction. This is like D, but is 12
566 bits only. */
567#define DE D + 1
568 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
569
570 /* The DES field in a DES form instruction. This is like DS, but is 14
571 bits only (12 stored.) */
572#define DES DE + 1
573 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
574
575 /* The DQ field in a DQ form instruction. This is like D, but the
576 lower four bits are forced to zero. */
577#define DQ DES + 1
578 { 16, 0, insert_dq, extract_dq,
579 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
b9adb4a6
FB		 580
581 /* The DS field in a DS form instruction. This is like D, but the
582 lower two bits are forced to zero. */
eca8f888
BS		 583#define DS DQ + 1
584 { 16, 0, insert_ds, extract_ds,
585 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
586
587 /* The E field in a wrteei instruction. */
588#define E DS + 1
589 { 1, 15, NULL, NULL, 0 },
b9adb4a6
FB		 590
591 /* The FL1 field in a POWER SC form instruction. */
eca8f888
BS		 592#define FL1 E + 1
593 { 4, 12, NULL, NULL, 0 },
b9adb4a6
FB		 594
595 /* The FL2 field in a POWER SC form instruction. */
eca8f888
BS		 596#define FL2 FL1 + 1
597 { 3, 2, NULL, NULL, 0 },
b9adb4a6
FB		 598
599 /* The FLM field in an XFL form instruction. */
eca8f888
BS		 600#define FLM FL2 + 1
601 { 8, 17, NULL, NULL, 0 },
b9adb4a6
FB		 602
603 /* The FRA field in an X or A form instruction. */
eca8f888 604#define FRA FLM + 1
b9adb4a6 605#define FRA_MASK (0x1f << 16)
eca8f888 606 { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
b9adb4a6
FB		 607
608 /* The FRB field in an X or A form instruction. */
eca8f888 609#define FRB FRA + 1
b9adb4a6 610#define FRB_MASK (0x1f << 11)
eca8f888 611 { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
b9adb4a6
FB		 612
613 /* The FRC field in an A form instruction. */
eca8f888 614#define FRC FRB + 1
b9adb4a6 615#define FRC_MASK (0x1f << 6)
eca8f888 616 { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
b9adb4a6
FB		 617
618 /* The FRS field in an X form instruction or the FRT field in a D, X
619 or A form instruction. */
eca8f888
BS		 620#define FRS FRC + 1
621#define FRT FRS
622 { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
b9adb4a6
FB		 623
624 /* The FXM field in an XFX instruction. */
eca8f888 625#define FXM FRS + 1
b9adb4a6 626#define FXM_MASK (0xff << 12)
eca8f888
BS		 627 { 8, 12, insert_fxm, extract_fxm, 0 },
628
629 /* Power4 version for mfcr. */
630#define FXM4 FXM + 1
631 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 632
633 /* The L field in a D or X form instruction. */
eca8f888
BS		 634#define L FXM4 + 1
635 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
b9adb4a6 636
eca8f888
BS		 637 /* The LEV field in a POWER SVC form instruction. */
638#define SVC_LEV L + 1
639 { 7, 5, NULL, NULL, 0 },
640
641 /* The LEV field in an SC form instruction. */
642#define LEV SVC_LEV + 1
643 { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 644
645 /* The LI field in an I form instruction. The lower two bits are
646 forced to zero. */
eca8f888 647#define LI LEV + 1
b9adb4a6
FB		 648 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
649
650 /* The LI field in an I form instruction when used as an absolute
651 address. */
eca8f888 652#define LIA LI + 1
b9adb4a6
FB		 653 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
654
eca8f888
BS		 655 /* The LS field in an X (sync) form instruction. */
656#define LS LIA + 1
657 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
658
b9adb4a6 659 /* The MB field in an M form instruction. */
eca8f888 660#define MB LS + 1
b9adb4a6 661#define MB_MASK (0x1f << 6)
eca8f888 662 { 5, 6, NULL, NULL, 0 },
b9adb4a6
FB		 663
664 /* The ME field in an M form instruction. */
eca8f888 665#define ME MB + 1
b9adb4a6 666#define ME_MASK (0x1f << 1)
eca8f888 667 { 5, 1, NULL, NULL, 0 },
b9adb4a6
FB		 668
669 /* The MB and ME fields in an M form instruction expressed a single
670 operand which is a bitmask indicating which bits to select. This
671 is a two operand form using PPC_OPERAND_NEXT. See the
672 description in opcode/ppc.h for what this means. */
eca8f888
BS		 673#define MBE ME + 1
674 { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
b9adb4a6
FB		 675 { 32, 0, insert_mbe, extract_mbe, 0 },
676
677 /* The MB or ME field in an MD or MDS form instruction. The high
678 bit is wrapped to the low end. */
eca8f888
BS		 679#define MB6 MBE + 2
680#define ME6 MB6
b9adb4a6
FB		 681#define MB6_MASK (0x3f << 5)
682 { 6, 5, insert_mb6, extract_mb6, 0 },
683
eca8f888
BS		 684 /* The MO field in an mbar instruction. */
685#define MO MB6 + 1
686 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
687
b9adb4a6
FB		 688 /* The NB field in an X form instruction. The value 32 is stored as
689 0. */
eca8f888 690#define NB MO + 1
b9adb4a6
FB		 691 { 6, 11, insert_nb, extract_nb, 0 },
692
693 /* The NSI field in a D form instruction. This is the same as the
694 SI field, only negated. */
eca8f888 695#define NSI NB + 1
b9adb4a6
FB		 696 { 16, 0, insert_nsi, extract_nsi,
697 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
698
eca8f888
BS		 699 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
700#define RA NSI + 1
b9adb4a6 701#define RA_MASK (0x1f << 16)
eca8f888
BS		 702 { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
703
704 /* As above, but 0 in the RA field means zero, not r0. */
705#define RA0 RA + 1
706 { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
707
708 /* The RA field in the DQ form lq instruction, which has special
709 value restrictions. */
710#define RAQ RA0 + 1
711 { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
b9adb4a6
FB		 712
713 /* The RA field in a D or X form instruction which is an updating
714 load, which means that the RA field may not be zero and may not
715 equal the RT field. */
eca8f888
BS		 716#define RAL RAQ + 1
717 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
b9adb4a6
FB		 718
719 /* The RA field in an lmw instruction, which has special value
720 restrictions. */
eca8f888
BS		 721#define RAM RAL + 1
722 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
b9adb4a6
FB		 723
724 /* The RA field in a D or X form instruction which is an updating
725 store or an updating floating point load, which means that the RA
726 field may not be zero. */
eca8f888
BS		 727#define RAS RAM + 1
728 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
729
730 /* The RA field of the tlbwe instruction, which is optional. */
731#define RAOPT RAS + 1
732 { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 733
734 /* The RB field in an X, XO, M, or MDS form instruction. */
eca8f888 735#define RB RAOPT + 1
b9adb4a6 736#define RB_MASK (0x1f << 11)
eca8f888 737 { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
b9adb4a6
FB		 738
739 /* The RB field in an X form instruction when it must be the same as
740 the RS field in the instruction. This is used for extended
741 mnemonics like mr. */
eca8f888 742#define RBS RB + 1
b9adb4a6
FB		 743 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
744
745 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
746 instruction or the RT field in a D, DS, X, XFX or XO form
747 instruction. */
eca8f888
BS		 748#define RS RBS + 1
749#define RT RS
b9adb4a6 750#define RT_MASK (0x1f << 21)
eca8f888
BS		 751 { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
752
753 /* The RS field of the DS form stq instruction, which has special
754 value restrictions. */
755#define RSQ RS + 1
756 { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 },
757
758 /* The RT field of the DQ form lq instruction, which has special
759 value restrictions. */
760#define RTQ RSQ + 1
761 { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 },
762
763 /* The RS field of the tlbwe instruction, which is optional. */
764#define RSO RTQ + 1
765#define RTO RSO
766 { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 767
768 /* The SH field in an X or M form instruction. */
eca8f888 769#define SH RSO + 1
b9adb4a6 770#define SH_MASK (0x1f << 11)
eca8f888 771 { 5, 11, NULL, NULL, 0 },
b9adb4a6
FB		 772
773 /* The SH field in an MD form instruction. This is split. */
eca8f888 774#define SH6 SH + 1
b9adb4a6
FB		 775#define SH6_MASK ((0x1f << 11) | (1 << 1))
776 { 6, 1, insert_sh6, extract_sh6, 0 },
777
eca8f888
BS		 778 /* The SH field of the tlbwe instruction, which is optional. */
779#define SHO SH6 + 1
780 { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL },
781
b9adb4a6 782 /* The SI field in a D form instruction. */
eca8f888
BS		 783#define SI SHO + 1
784 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
b9adb4a6
FB		 785
786 /* The SI field in a D form instruction when we accept a wide range
787 of positive values. */
eca8f888
BS		 788#define SISIGNOPT SI + 1
789 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
b9adb4a6
FB		 790
791 /* The SPR field in an XFX form instruction. This is flipped--the
792 lower 5 bits are stored in the upper 5 and vice- versa. */
eca8f888
BS		 793#define SPR SISIGNOPT + 1
794#define PMR SPR
b9adb4a6
FB		 795#define SPR_MASK (0x3ff << 11)
796 { 10, 11, insert_spr, extract_spr, 0 },
797
798 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
eca8f888 799#define SPRBAT SPR + 1
b9adb4a6 800#define SPRBAT_MASK (0x3 << 17)
eca8f888 801 { 2, 17, NULL, NULL, 0 },
b9adb4a6
FB		 802
803 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
eca8f888
BS		 804#define SPRG SPRBAT + 1
805 { 5, 16, insert_sprg, extract_sprg, 0 },
b9adb4a6
FB		 806
807 /* The SR field in an X form instruction. */
eca8f888
BS		 808#define SR SPRG + 1
809 { 4, 16, NULL, NULL, 0 },
810
811 /* The STRM field in an X AltiVec form instruction. */
812#define STRM SR + 1
813#define STRM_MASK (0x3 << 21)
814 { 2, 21, NULL, NULL, 0 },
b9adb4a6
FB		 815
816 /* The SV field in a POWER SC form instruction. */
eca8f888
BS		 817#define SV STRM + 1
818 { 14, 2, NULL, NULL, 0 },
b9adb4a6
FB		 819
820 /* The TBR field in an XFX form instruction. This is like the SPR
821 field, but it is optional. */
eca8f888 822#define TBR SV + 1
b9adb4a6
FB		 823 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
824
825 /* The TO field in a D or X form instruction. */
eca8f888 826#define TO TBR + 1
b9adb4a6 827#define TO_MASK (0x1f << 21)
eca8f888 828 { 5, 21, NULL, NULL, 0 },
b9adb4a6
FB		 829
830 /* The U field in an X form instruction. */
eca8f888
BS		 831#define U TO + 1
832 { 4, 12, NULL, NULL, 0 },
b9adb4a6
FB		 833
834 /* The UI field in a D form instruction. */
eca8f888
BS		 835#define UI U + 1
836 { 16, 0, NULL, NULL, 0 },
837
838 /* The VA field in a VA, VX or VXR form instruction. */
839#define VA UI + 1
840#define VA_MASK (0x1f << 16)
841 { 5, 16, NULL, NULL, PPC_OPERAND_VR },
842
843 /* The VB field in a VA, VX or VXR form instruction. */
844#define VB VA + 1
845#define VB_MASK (0x1f << 11)
846 { 5, 11, NULL, NULL, PPC_OPERAND_VR },
847
848 /* The VC field in a VA form instruction. */
849#define VC VB + 1
850#define VC_MASK (0x1f << 6)
851 { 5, 6, NULL, NULL, PPC_OPERAND_VR },
852
853 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
854#define VD VC + 1
855#define VS VD
856#define VD_MASK (0x1f << 21)
857 { 5, 21, NULL, NULL, PPC_OPERAND_VR },
858
859 /* The SIMM field in a VX form instruction. */
860#define SIMM VD + 1
861 { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
862
863 /* The UIMM field in a VX form instruction. */
864#define UIMM SIMM + 1
865 { 5, 16, NULL, NULL, 0 },
866
867 /* The SHB field in a VA form instruction. */
868#define SHB UIMM + 1
869 { 4, 6, NULL, NULL, 0 },
870
871 /* The other UIMM field in a EVX form instruction. */
872#define EVUIMM SHB + 1
873 { 5, 11, NULL, NULL, 0 },
874
875 /* The other UIMM field in a half word EVX form instruction. */
876#define EVUIMM_2 EVUIMM + 1
877 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
878
879 /* The other UIMM field in a word EVX form instruction. */
880#define EVUIMM_4 EVUIMM_2 + 1
881 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
882
883 /* The other UIMM field in a double EVX form instruction. */
884#define EVUIMM_8 EVUIMM_4 + 1
885 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
886
887 /* The WS field. */
888#define WS EVUIMM_8 + 1
889#define WS_MASK (0x7 << 11)
890 { 3, 11, NULL, NULL, 0 },
891
892 /* The L field in an mtmsrd instruction */
893#define MTMSRD_L WS + 1
894 { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
895
b9adb4a6
FB		 896};
897
898/* The functions used to insert and extract complicated operands. */
899
900/* The BA field in an XL form instruction when it must be the same as
901 the BT field in the same instruction. This operand is marked FAKE.
902 The insertion function just copies the BT field into the BA field,
903 and the extraction function just checks that the fields are the
904 same. */
905
5fafdf24 906static unsigned long
eca8f888
BS		 907insert_bat (unsigned long insn,
908 long value ATTRIBUTE_UNUSED,
909 int dialect ATTRIBUTE_UNUSED,
910 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 911{
912 return insn | (((insn >> 21) & 0x1f) << 16);
913}
914
915static long
eca8f888
BS		 916extract_bat (unsigned long insn,
917 int dialect ATTRIBUTE_UNUSED,
918 int *invalid)
b9adb4a6 919{
eca8f888 920 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
b9adb4a6
FB		 921 *invalid = 1;
922 return 0;
923}
924
925/* The BB field in an XL form instruction when it must be the same as
926 the BA field in the same instruction. This operand is marked FAKE.
927 The insertion function just copies the BA field into the BB field,
928 and the extraction function just checks that the fields are the
929 same. */
930
b9adb4a6 931static unsigned long
eca8f888
BS		 932insert_bba (unsigned long insn,
933 long value ATTRIBUTE_UNUSED,
934 int dialect ATTRIBUTE_UNUSED,
935 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 936{
937 return insn | (((insn >> 16) & 0x1f) << 11);
938}
939
940static long
eca8f888
BS		 941extract_bba (unsigned long insn,
942 int dialect ATTRIBUTE_UNUSED,
943 int *invalid)
b9adb4a6 944{
eca8f888 945 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
b9adb4a6
FB		 946 *invalid = 1;
947 return 0;
948}
949
950/* The BD field in a B form instruction. The lower two bits are
951 forced to zero. */
952
b9adb4a6 953static unsigned long
eca8f888
BS		 954insert_bd (unsigned long insn,
955 long value,
956 int dialect ATTRIBUTE_UNUSED,
957 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 958{
959 return insn | (value & 0xfffc);
960}
961
b9adb4a6 962static long
eca8f888
BS		 963extract_bd (unsigned long insn,
964 int dialect ATTRIBUTE_UNUSED,
965 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6 966{
eca8f888 967 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
b9adb4a6
FB		 968}
969
970/* The BD field in a B form instruction when the - modifier is used.
971 This modifier means that the branch is not expected to be taken.
eca8f888
BS		 972 For chips built to versions of the architecture prior to version 2
973 (ie. not Power4 compatible), we set the y bit of the BO field to 1
974 if the offset is negative. When extracting, we require that the y
975 bit be 1 and that the offset be positive, since if the y bit is 0
976 we just want to print the normal form of the instruction.
977 Power4 compatible targets use two bits, "a", and "t", instead of
978 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
979 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
980 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
981 for branch on CTR. We only handle the taken/not-taken hint here. */
b9adb4a6 982
b9adb4a6 983static unsigned long
eca8f888
BS		 984insert_bdm (unsigned long insn,
985 long value,
986 int dialect,
987 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6 988{
eca8f888
BS		 989 if ((dialect & PPC_OPCODE_POWER4) == 0)
990 {
991 if ((value & 0x8000) != 0)
992 insn |= 1 << 21;
993 }
994 else
995 {
996 if ((insn & (0x14 << 21)) == (0x04 << 21))
997 insn |= 0x02 << 21;
998 else if ((insn & (0x14 << 21)) == (0x10 << 21))
999 insn |= 0x08 << 21;
1000 }
b9adb4a6
FB		 1001 return insn | (value & 0xfffc);
1002}
1003
1004static long
eca8f888
BS		 1005extract_bdm (unsigned long insn,
1006 int dialect,
1007 int *invalid)
b9adb4a6 1008{
eca8f888
BS		 1009 if ((dialect & PPC_OPCODE_POWER4) == 0)
1010 {
1011 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1012 *invalid = 1;
1013 }
b9adb4a6 1014 else
eca8f888
BS		 1015 {
1016 if ((insn & (0x17 << 21)) != (0x06 << 21)
1017 && (insn & (0x1d << 21)) != (0x18 << 21))
1018 *invalid = 1;
1019 }
1020
1021 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
b9adb4a6
FB		 1022}
1023
1024/* The BD field in a B form instruction when the + modifier is used.
1025 This is like BDM, above, except that the branch is expected to be
1026 taken. */
1027
b9adb4a6 1028static unsigned long
eca8f888
BS		 1029insert_bdp (unsigned long insn,
1030 long value,
1031 int dialect,
1032 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6 1033{
eca8f888
BS		 1034 if ((dialect & PPC_OPCODE_POWER4) == 0)
1035 {
1036 if ((value & 0x8000) == 0)
1037 insn |= 1 << 21;
1038 }
1039 else
1040 {
1041 if ((insn & (0x14 << 21)) == (0x04 << 21))
1042 insn |= 0x03 << 21;
1043 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1044 insn |= 0x09 << 21;
1045 }
b9adb4a6
FB		 1046 return insn | (value & 0xfffc);
1047}
1048
1049static long
eca8f888
BS		 1050extract_bdp (unsigned long insn,
1051 int dialect,
1052 int *invalid)
b9adb4a6 1053{
eca8f888
BS		 1054 if ((dialect & PPC_OPCODE_POWER4) == 0)
1055 {
1056 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1057 *invalid = 1;
1058 }
b9adb4a6 1059 else
eca8f888
BS		 1060 {
1061 if ((insn & (0x17 << 21)) != (0x07 << 21)
1062 && (insn & (0x1d << 21)) != (0x19 << 21))
1063 *invalid = 1;
1064 }
1065
1066 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
b9adb4a6
FB		 1067}
1068
1069/* Check for legal values of a BO field. */
1070
1071static int
eca8f888
BS		 1072valid_bo (long value, int dialect)
1073{
1074 if ((dialect & PPC_OPCODE_POWER4) == 0)
1075 {
1076 /* Certain encodings have bits that are required to be zero.
1077 These are (z must be zero, y may be anything):
1078 001zy
1079 011zy
1080 1z00y
1081 1z01y
1082 1z1zz
1083 */
1084 switch (value & 0x14)
1085 {
1086 default:
1087 case 0:
1088 return 1;
1089 case 0x4:
1090 return (value & 0x2) == 0;
1091 case 0x10:
1092 return (value & 0x8) == 0;
1093 case 0x14:
1094 return value == 0x14;
1095 }
1096 }
1097 else
b9adb4a6 1098 {
eca8f888
BS		 1099 /* Certain encodings have bits that are required to be zero.
1100 These are (z must be zero, a & t may be anything):
1101 0000z
1102 0001z
1103 0100z
1104 0101z
1105 001at
1106 011at
1107 1a00t
1108 1a01t
1109 1z1zz
1110 */
1111 if ((value & 0x14) == 0)
1112 return (value & 0x1) == 0;
1113 else if ((value & 0x14) == 0x14)
1114 return value == 0x14;
1115 else
1116 return 1;
b9adb4a6
FB		 1117 }
1118}
1119
1120/* The BO field in a B form instruction. Warn about attempts to set
1121 the field to an illegal value. */
1122
1123static unsigned long
eca8f888
BS		 1124insert_bo (unsigned long insn,
1125 long value,
1126 int dialect,
1127 const char **errmsg)
1128{
1129 if (!valid_bo (value, dialect))
1130 *errmsg = _("invalid conditional option");
b9adb4a6
FB		 1131 return insn | ((value & 0x1f) << 21);
1132}
1133
1134static long
eca8f888
BS		 1135extract_bo (unsigned long insn,
1136 int dialect,
1137 int *invalid)
b9adb4a6 1138{
eca8f888 1139 long value;
b9adb4a6
FB		 1140
1141 value = (insn >> 21) & 0x1f;
eca8f888 1142 if (!valid_bo (value, dialect))
b9adb4a6
FB		 1143 *invalid = 1;
1144 return value;
1145}
1146
1147/* The BO field in a B form instruction when the + or - modifier is
1148 used. This is like the BO field, but it must be even. When
1149 extracting it, we force it to be even. */
1150
1151static unsigned long
eca8f888
BS		 1152insert_boe (unsigned long insn,
1153 long value,
1154 int dialect,
1155 const char **errmsg)
b9adb4a6 1156{
eca8f888
BS		 1157 if (!valid_bo (value, dialect))
1158 *errmsg = _("invalid conditional option");
1159 else if ((value & 1) != 0)
1160 *errmsg = _("attempt to set y bit when using + or - modifier");
1161
b9adb4a6
FB		 1162 return insn | ((value & 0x1f) << 21);
1163}
1164
1165static long
eca8f888
BS		 1166extract_boe (unsigned long insn,
1167 int dialect,
1168 int *invalid)
b9adb4a6 1169{
eca8f888 1170 long value;
b9adb4a6
FB		 1171
1172 value = (insn >> 21) & 0x1f;
eca8f888 1173 if (!valid_bo (value, dialect))
b9adb4a6
FB		 1174 *invalid = 1;
1175 return value & 0x1e;
1176}
1177
eca8f888
BS		 1178/* The DQ field in a DQ form instruction. This is like D, but the
1179 lower four bits are forced to zero. */
1180
1181static unsigned long
1182insert_dq (unsigned long insn,
1183 long value,
1184 int dialect ATTRIBUTE_UNUSED,
1185 const char **errmsg)
1186{
1187 if ((value & 0xf) != 0)
1188 *errmsg = _("offset not a multiple of 16");
1189 return insn | (value & 0xfff0);
1190}
1191
1192static long
1193extract_dq (unsigned long insn,
1194 int dialect ATTRIBUTE_UNUSED,
1195 int *invalid ATTRIBUTE_UNUSED)
1196{
1197 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
1198}
1199
1200static unsigned long
1201insert_ev2 (unsigned long insn,
1202 long value,
1203 int dialect ATTRIBUTE_UNUSED,
1204 const char **errmsg)
1205{
1206 if ((value & 1) != 0)
1207 *errmsg = _("offset not a multiple of 2");
1208 if ((value > 62) != 0)
1209 *errmsg = _("offset greater than 62");
1210 return insn | ((value & 0x3e) << 10);
1211}
1212
1213static long
1214extract_ev2 (unsigned long insn,
1215 int dialect ATTRIBUTE_UNUSED,
1216 int *invalid ATTRIBUTE_UNUSED)
1217{
1218 return (insn >> 10) & 0x3e;
1219}
1220
1221static unsigned long
1222insert_ev4 (unsigned long insn,
1223 long value,
1224 int dialect ATTRIBUTE_UNUSED,
1225 const char **errmsg)
1226{
1227 if ((value & 3) != 0)
1228 *errmsg = _("offset not a multiple of 4");
1229 if ((value > 124) != 0)
1230 *errmsg = _("offset greater than 124");
1231 return insn | ((value & 0x7c) << 9);
1232}
1233
1234static long
1235extract_ev4 (unsigned long insn,
1236 int dialect ATTRIBUTE_UNUSED,
1237 int *invalid ATTRIBUTE_UNUSED)
1238{
1239 return (insn >> 9) & 0x7c;
1240}
1241
1242static unsigned long
1243insert_ev8 (unsigned long insn,
1244 long value,
1245 int dialect ATTRIBUTE_UNUSED,
1246 const char **errmsg)
1247{
1248 if ((value & 7) != 0)
1249 *errmsg = _("offset not a multiple of 8");
1250 if ((value > 248) != 0)
1251 *errmsg = _("offset greater than 248");
1252 return insn | ((value & 0xf8) << 8);
1253}
1254
1255static long
1256extract_ev8 (unsigned long insn,
1257 int dialect ATTRIBUTE_UNUSED,
1258 int *invalid ATTRIBUTE_UNUSED)
1259{
1260 return (insn >> 8) & 0xf8;
1261}
1262
b9adb4a6
FB		 1263/* The DS field in a DS form instruction. This is like D, but the
1264 lower two bits are forced to zero. */
1265
b9adb4a6 1266static unsigned long
eca8f888
BS		 1267insert_ds (unsigned long insn,
1268 long value,
1269 int dialect ATTRIBUTE_UNUSED,
1270 const char **errmsg)
b9adb4a6 1271{
eca8f888
BS		 1272 if ((value & 3) != 0)
1273 *errmsg = _("offset not a multiple of 4");
b9adb4a6
FB		 1274 return insn | (value & 0xfffc);
1275}
1276
b9adb4a6 1277static long
eca8f888
BS		 1278extract_ds (unsigned long insn,
1279 int dialect ATTRIBUTE_UNUSED,
1280 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6 1281{
eca8f888
BS		 1282 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1283}
1284
1285/* The DE field in a DE form instruction. */
1286
1287static unsigned long
1288insert_de (unsigned long insn,
1289 long value,
1290 int dialect ATTRIBUTE_UNUSED,
1291 const char **errmsg)
1292{
1293 if (value > 2047 || value < -2048)
1294 *errmsg = _("offset not between -2048 and 2047");
1295 return insn | ((value << 4) & 0xfff0);
1296}
1297
1298static long
1299extract_de (unsigned long insn,
1300 int dialect ATTRIBUTE_UNUSED,
1301 int *invalid ATTRIBUTE_UNUSED)
1302{
1303 return (insn & 0xfff0) >> 4;
1304}
1305
1306/* The DES field in a DES form instruction. */
1307
1308static unsigned long
1309insert_des (unsigned long insn,
1310 long value,
1311 int dialect ATTRIBUTE_UNUSED,
1312 const char **errmsg)
1313{
1314 if (value > 8191 || value < -8192)
1315 *errmsg = _("offset not between -8192 and 8191");
1316 else if ((value & 3) != 0)
1317 *errmsg = _("offset not a multiple of 4");
1318 return insn | ((value << 2) & 0xfff0);
1319}
1320
1321static long
1322extract_des (unsigned long insn,
1323 int dialect ATTRIBUTE_UNUSED,
1324 int *invalid ATTRIBUTE_UNUSED)
1325{
1326 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
1327}
1328
1329/* FXM mask in mfcr and mtcrf instructions. */
1330
1331static unsigned long
1332insert_fxm (unsigned long insn,
1333 long value,
1334 int dialect,
1335 const char **errmsg)
1336{
1337 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1338 one bit of the mask field is set. */
1339 if ((insn & (1 << 20)) != 0)
1340 {
1341 if (value == 0 || (value & -value) != value)
1342 {
1343 *errmsg = _("invalid mask field");
1344 value = 0;
1345 }
1346 }
1347
1348 /* If the optional field on mfcr is missing that means we want to use
1349 the old form of the instruction that moves the whole cr. In that
1350 case we'll have VALUE zero. There doesn't seem to be a way to
1351 distinguish this from the case where someone writes mfcr %r3,0. */
1352 else if (value == 0)
1353 ;
1354
1355 /* If only one bit of the FXM field is set, we can use the new form
1356 of the instruction, which is faster. Unlike the Power4 branch hint
1357 encoding, this is not backward compatible. Do not generate the
1358 new form unless -mpower4 has been given, or -many and the two
1359 operand form of mfcr was used. */
1360 else if ((value & -value) == value
1361 && ((dialect & PPC_OPCODE_POWER4) != 0
1362 || ((dialect & PPC_OPCODE_ANY) != 0
1363 && (insn & (0x3ff << 1)) == 19 << 1)))
1364 insn |= 1 << 20;
1365
1366 /* Any other value on mfcr is an error. */
1367 else if ((insn & (0x3ff << 1)) == 19 << 1)
1368 {
1369 *errmsg = _("ignoring invalid mfcr mask");
1370 value = 0;
1371 }
1372
1373 return insn | ((value & 0xff) << 12);
1374}
1375
1376static long
1377extract_fxm (unsigned long insn,
1378 int dialect ATTRIBUTE_UNUSED,
1379 int *invalid)
1380{
1381 long mask = (insn >> 12) & 0xff;
1382
1383 /* Is this a Power4 insn? */
1384 if ((insn & (1 << 20)) != 0)
1385 {
1386 /* Exactly one bit of MASK should be set. */
1387 if (mask == 0 || (mask & -mask) != mask)
1388 *invalid = 1;
1389 }
1390
1391 /* Check that non-power4 form of mfcr has a zero MASK. */
1392 else if ((insn & (0x3ff << 1)) == 19 << 1)
1393 {
1394 if (mask != 0)
1395 *invalid = 1;
1396 }
1397
1398 return mask;
b9adb4a6
FB		 1399}
1400
1401/* The LI field in an I form instruction. The lower two bits are
1402 forced to zero. */
1403
b9adb4a6 1404static unsigned long
eca8f888
BS		 1405insert_li (unsigned long insn,
1406 long value,
1407 int dialect ATTRIBUTE_UNUSED,
1408 const char **errmsg)
b9adb4a6 1409{
eca8f888
BS		 1410 if ((value & 3) != 0)
1411 *errmsg = _("ignoring least significant bits in branch offset");
b9adb4a6
FB		 1412 return insn | (value & 0x3fffffc);
1413}
1414
b9adb4a6 1415static long
eca8f888
BS		 1416extract_li (unsigned long insn,
1417 int dialect ATTRIBUTE_UNUSED,
1418 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6 1419{
eca8f888 1420 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
b9adb4a6
FB		 1421}
1422
1423/* The MB and ME fields in an M form instruction expressed as a single
1424 operand which is itself a bitmask. The extraction function always
1425 marks it as invalid, since we never want to recognize an
1426 instruction which uses a field of this type. */
1427
1428static unsigned long
eca8f888
BS		 1429insert_mbe (unsigned long insn,
1430 long value,
1431 int dialect ATTRIBUTE_UNUSED,
1432 const char **errmsg)
b9adb4a6 1433{
eca8f888
BS		 1434 unsigned long uval, mask;
1435 int mb, me, mx, count, last;
b9adb4a6
FB		 1436
1437 uval = value;
1438
1439 if (uval == 0)
1440 {
eca8f888 1441 *errmsg = _("illegal bitmask");
b9adb4a6
FB		 1442 return insn;
1443 }
1444
eca8f888
BS		 1445 mb = 0;
1446 me = 32;
1447 if ((uval & 1) != 0)
1448 last = 1;
1449 else
1450 last = 0;
1451 count = 0;
b9adb4a6 1452
eca8f888
BS		 1453 /* mb: location of last 0->1 transition */
1454 /* me: location of last 1->0 transition */
1455 /* count: # transitions */
b9adb4a6 1456
eca8f888 1457 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
b9adb4a6 1458 {
eca8f888
BS		 1459 if ((uval & mask) && !last)
1460 {
1461 ++count;
1462 mb = mx;
1463 last = 1;
1464 }
1465 else if (!(uval & mask) && last)
1466 {
1467 ++count;
1468 me = mx;
1469 last = 0;
1470 }
b9adb4a6 1471 }
eca8f888
BS		 1472 if (me == 0)
1473 me = 32;
b9adb4a6 1474
eca8f888
BS		 1475 if (count != 2 && (count != 0 || ! last))
1476 *errmsg = _("illegal bitmask");
1477
1478 return insn | (mb << 6) | ((me - 1) << 1);
b9adb4a6
FB		 1479}
1480
1481static long
eca8f888
BS		 1482extract_mbe (unsigned long insn,
1483 int dialect ATTRIBUTE_UNUSED,
1484 int *invalid)
b9adb4a6
FB		 1485{
1486 long ret;
1487 int mb, me;
1488 int i;
1489
eca8f888 1490 *invalid = 1;
b9adb4a6 1491
b9adb4a6
FB		 1492 mb = (insn >> 6) & 0x1f;
1493 me = (insn >> 1) & 0x1f;
eca8f888
BS		 1494 if (mb < me + 1)
1495 {
1496 ret = 0;
1497 for (i = mb; i <= me; i++)
1498 ret |= 1L << (31 - i);
1499 }
1500 else if (mb == me + 1)
1501 ret = ~0;
1502 else /* (mb > me + 1) */
1503 {
1504 ret = ~0;
1505 for (i = me + 1; i < mb; i++)
1506 ret &= ~(1L << (31 - i));
1507 }
b9adb4a6
FB		 1508 return ret;
1509}
1510
1511/* The MB or ME field in an MD or MDS form instruction. The high bit
1512 is wrapped to the low end. */
1513
b9adb4a6 1514static unsigned long
eca8f888
BS		 1515insert_mb6 (unsigned long insn,
1516 long value,
1517 int dialect ATTRIBUTE_UNUSED,
1518 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1519{
1520 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1521}
1522
b9adb4a6 1523static long
eca8f888
BS		 1524extract_mb6 (unsigned long insn,
1525 int dialect ATTRIBUTE_UNUSED,
1526 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1527{
1528 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1529}
1530
1531/* The NB field in an X form instruction. The value 32 is stored as
1532 0. */
1533
1534static unsigned long
eca8f888
BS		 1535insert_nb (unsigned long insn,
1536 long value,
1537 int dialect ATTRIBUTE_UNUSED,
1538 const char **errmsg)
b9adb4a6
FB		 1539{
1540 if (value < 0 || value > 32)
eca8f888 1541 *errmsg = _("value out of range");
b9adb4a6
FB		 1542 if (value == 32)
1543 value = 0;
1544 return insn | ((value & 0x1f) << 11);
1545}
1546
b9adb4a6 1547static long
eca8f888
BS		 1548extract_nb (unsigned long insn,
1549 int dialect ATTRIBUTE_UNUSED,
1550 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1551{
1552 long ret;
1553
1554 ret = (insn >> 11) & 0x1f;
1555 if (ret == 0)
1556 ret = 32;
1557 return ret;
1558}
1559
1560/* The NSI field in a D form instruction. This is the same as the SI
1561 field, only negated. The extraction function always marks it as
1562 invalid, since we never want to recognize an instruction which uses
1563 a field of this type. */
1564
b9adb4a6 1565static unsigned long
eca8f888
BS		 1566insert_nsi (unsigned long insn,
1567 long value,
1568 int dialect ATTRIBUTE_UNUSED,
1569 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6 1570{
eca8f888 1571 return insn | (-value & 0xffff);
b9adb4a6
FB		 1572}
1573
1574static long
eca8f888
BS		 1575extract_nsi (unsigned long insn,
1576 int dialect ATTRIBUTE_UNUSED,
1577 int *invalid)
b9adb4a6 1578{
eca8f888
BS		 1579 *invalid = 1;
1580 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
b9adb4a6
FB		 1581}
1582
1583/* The RA field in a D or X form instruction which is an updating
1584 load, which means that the RA field may not be zero and may not
1585 equal the RT field. */
1586
1587static unsigned long
eca8f888
BS		 1588insert_ral (unsigned long insn,
1589 long value,
1590 int dialect ATTRIBUTE_UNUSED,
1591 const char **errmsg)
b9adb4a6
FB		 1592{
1593 if (value == 0
eca8f888 1594 || (unsigned long) value == ((insn >> 21) & 0x1f))
b9adb4a6
FB		 1595 *errmsg = "invalid register operand when updating";
1596 return insn | ((value & 0x1f) << 16);
1597}
1598
1599/* The RA field in an lmw instruction, which has special value
1600 restrictions. */
1601
1602static unsigned long
eca8f888
BS		 1603insert_ram (unsigned long insn,
1604 long value,
1605 int dialect ATTRIBUTE_UNUSED,
1606 const char **errmsg)
b9adb4a6 1607{
eca8f888
BS		 1608 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1609 *errmsg = _("index register in load range");
1610 return insn | ((value & 0x1f) << 16);
1611}
1612
1613/* The RA field in the DQ form lq instruction, which has special
1614 value restrictions. */
1615
1616static unsigned long
1617insert_raq (unsigned long insn,
1618 long value,
1619 int dialect ATTRIBUTE_UNUSED,
1620 const char **errmsg)
1621{
1622 long rtvalue = (insn & RT_MASK) >> 21;
1623
1624 if (value == rtvalue)
1625 *errmsg = _("source and target register operands must be different");
b9adb4a6
FB		 1626 return insn | ((value & 0x1f) << 16);
1627}
1628
1629/* The RA field in a D or X form instruction which is an updating
1630 store or an updating floating point load, which means that the RA
1631 field may not be zero. */
1632
1633static unsigned long
eca8f888
BS		 1634insert_ras (unsigned long insn,
1635 long value,
1636 int dialect ATTRIBUTE_UNUSED,
1637 const char **errmsg)
b9adb4a6
FB		 1638{
1639 if (value == 0)
eca8f888 1640 *errmsg = _("invalid register operand when updating");
b9adb4a6
FB		 1641 return insn | ((value & 0x1f) << 16);
1642}
1643
1644/* The RB field in an X form instruction when it must be the same as
1645 the RS field in the instruction. This is used for extended
1646 mnemonics like mr. This operand is marked FAKE. The insertion
1647 function just copies the BT field into the BA field, and the
1648 extraction function just checks that the fields are the same. */
1649
5fafdf24 1650static unsigned long
eca8f888
BS		 1651insert_rbs (unsigned long insn,
1652 long value ATTRIBUTE_UNUSED,
1653 int dialect ATTRIBUTE_UNUSED,
1654 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1655{
1656 return insn | (((insn >> 21) & 0x1f) << 11);
1657}
1658
1659static long
eca8f888
BS		 1660extract_rbs (unsigned long insn,
1661 int dialect ATTRIBUTE_UNUSED,
1662 int *invalid)
b9adb4a6 1663{
eca8f888 1664 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
b9adb4a6
FB		 1665 *invalid = 1;
1666 return 0;
1667}
1668
eca8f888
BS		 1669/* The RT field of the DQ form lq instruction, which has special
1670 value restrictions. */
1671
1672static unsigned long
1673insert_rtq (unsigned long insn,
1674 long value,
1675 int dialect ATTRIBUTE_UNUSED,
1676 const char **errmsg)
1677{
1678 if ((value & 1) != 0)
1679 *errmsg = _("target register operand must be even");
1680 return insn | ((value & 0x1f) << 21);
1681}
1682
1683/* The RS field of the DS form stq instruction, which has special
1684 value restrictions. */
1685
1686static unsigned long
1687insert_rsq (unsigned long insn,
1688 long value ATTRIBUTE_UNUSED,
1689 int dialect ATTRIBUTE_UNUSED,
1690 const char **errmsg)
1691{
1692 if ((value & 1) != 0)
1693 *errmsg = _("source register operand must be even");
1694 return insn | ((value & 0x1f) << 21);
1695}
1696
b9adb4a6
FB		 1697/* The SH field in an MD form instruction. This is split. */
1698
b9adb4a6 1699static unsigned long
eca8f888
BS		 1700insert_sh6 (unsigned long insn,
1701 long value,
1702 int dialect ATTRIBUTE_UNUSED,
1703 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1704{
1705 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1706}
1707
b9adb4a6 1708static long
eca8f888
BS		 1709extract_sh6 (unsigned long insn,
1710 int dialect ATTRIBUTE_UNUSED,
1711 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1712{
1713 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1714}
1715
1716/* The SPR field in an XFX form instruction. This is flipped--the
1717 lower 5 bits are stored in the upper 5 and vice- versa. */
1718
1719static unsigned long
eca8f888
BS		 1720insert_spr (unsigned long insn,
1721 long value,
1722 int dialect ATTRIBUTE_UNUSED,
1723 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1724{
1725 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1726}
1727
1728static long
eca8f888
BS		 1729extract_spr (unsigned long insn,
1730 int dialect ATTRIBUTE_UNUSED,
1731 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1732{
1733 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1734}
1735
eca8f888
BS		 1736/* Some dialects have 8 SPRG registers instead of the standard 4. */
1737
1738static unsigned long
1739insert_sprg (unsigned long insn,
1740 long value,
1741 int dialect,
1742 const char **errmsg)
1743{
1744 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1745 as a synonym. If ever a 405 specific dialect is added this
1746 check should use that instead. */
1747 if (value > 7
1748 || (value > 3
1749 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1750 *errmsg = _("invalid sprg number");
1751
1752 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1753 user mode. Anything else must use spr 272..279. */
1754 if (value <= 3 || (insn & 0x100) != 0)
1755 value |= 0x10;
1756
1757 return insn | ((value & 0x17) << 16);
1758}
1759
1760static long
1761extract_sprg (unsigned long insn,
1762 int dialect,
1763 int *invalid)
1764{
1765 unsigned long val = (insn >> 16) & 0x1f;
1766
1767 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1768 If not BOOKE or 405, then both use only 272..275. */
1769 if (val <= 3
1770 || (val < 0x10 && (insn & 0x100) != 0)
1771 || (val - 0x10 > 3
1772 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1773 *invalid = 1;
1774 return val & 7;
1775}
1776
b9adb4a6
FB		 1777/* The TBR field in an XFX instruction. This is just like SPR, but it
1778 is optional. When TBR is omitted, it must be inserted as 268 (the
1779 magic number of the TB register). These functions treat 0
1780 (indicating an omitted optional operand) as 268. This means that
1781 ``mftb 4,0'' is not handled correctly. This does not matter very
1782 much, since the architecture manual does not define mftb as
1783 accepting any values other than 268 or 269. */
1784
1785#define TB (268)
1786
1787static unsigned long
eca8f888
BS		 1788insert_tbr (unsigned long insn,
1789 long value,
1790 int dialect ATTRIBUTE_UNUSED,
1791 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1792{
1793 if (value == 0)
1794 value = TB;
1795 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1796}
1797
1798static long
eca8f888
BS		 1799extract_tbr (unsigned long insn,
1800 int dialect ATTRIBUTE_UNUSED,
1801 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1802{
1803 long ret;
1804
1805 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1806 if (ret == TB)
1807 ret = 0;
1808 return ret;
1809}
1810\f
1811/* Macros used to form opcodes. */
1812
1813/* The main opcode. */
eca8f888 1814#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
b9adb4a6
FB		 1815#define OP_MASK OP (0x3f)
1816
1817/* The main opcode combined with a trap code in the TO field of a D
1818 form instruction. Used for extended mnemonics for the trap
1819 instructions. */
eca8f888 1820#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
b9adb4a6
FB		 1821#define OPTO_MASK (OP_MASK | TO_MASK)
1822
1823/* The main opcode combined with a comparison size bit in the L field
1824 of a D form or X form instruction. Used for extended mnemonics for
1825 the comparison instructions. */
eca8f888 1826#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
b9adb4a6
FB		 1827#define OPL_MASK OPL (0x3f,1)
1828
1829/* An A form instruction. */
eca8f888 1830#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
b9adb4a6
FB		 1831#define A_MASK A (0x3f, 0x1f, 1)
1832
1833/* An A_MASK with the FRB field fixed. */
1834#define AFRB_MASK (A_MASK | FRB_MASK)
1835
1836/* An A_MASK with the FRC field fixed. */
1837#define AFRC_MASK (A_MASK | FRC_MASK)
1838
1839/* An A_MASK with the FRA and FRC fields fixed. */
1840#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1841
1842/* A B form instruction. */
eca8f888 1843#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
b9adb4a6
FB		 1844#define B_MASK B (0x3f, 1, 1)
1845
1846/* A B form instruction setting the BO field. */
eca8f888 1847#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
b9adb4a6
FB		 1848#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1849
1850/* A BBO_MASK with the y bit of the BO field removed. This permits
1851 matching a conditional branch regardless of the setting of the y
eca8f888
BS		 1852 bit. Similarly for the 'at' bits used for power4 branch hints. */
1853#define Y_MASK (((unsigned long) 1) << 21)
1854#define AT1_MASK (((unsigned long) 3) << 21)
1855#define AT2_MASK (((unsigned long) 9) << 21)
1856#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1857#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
b9adb4a6
FB		 1858
1859/* A B form instruction setting the BO field and the condition bits of
1860 the BI field. */
1861#define BBOCB(op, bo, cb, aa, lk) \
eca8f888 1862 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
b9adb4a6
FB		 1863#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1864
1865/* A BBOCB_MASK with the y bit of the BO field removed. */
1866#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
eca8f888
BS		 1867#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1868#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
b9adb4a6
FB		 1869
1870/* A BBOYCB_MASK in which the BI field is fixed. */
1871#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
eca8f888
BS		 1872#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1873
1874/* An Context form instruction. */
1875#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1876#define CTX_MASK CTX(0x3f, 0x7)
1877
1878/* An User Context form instruction. */
1879#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1880#define UCTX_MASK UCTX(0x3f, 0x1f)
b9adb4a6
FB		 1881
1882/* The main opcode mask with the RA field clear. */
1883#define DRA_MASK (OP_MASK | RA_MASK)
1884
1885/* A DS form instruction. */
1886#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1887#define DS_MASK DSO (0x3f, 3)
1888
eca8f888
BS		 1889/* A DE form instruction. */
1890#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1891#define DE_MASK DEO (0x3e, 0xf)
1892
1893/* An EVSEL form instruction. */
1894#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1895#define EVSEL_MASK EVSEL(0x3f, 0xff)
1896
b9adb4a6
FB		 1897/* An M form instruction. */
1898#define M(op, rc) (OP (op) | ((rc) & 1))
1899#define M_MASK M (0x3f, 1)
1900
1901/* An M form instruction with the ME field specified. */
eca8f888 1902#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
b9adb4a6
FB		 1903
1904/* An M_MASK with the MB and ME fields fixed. */
1905#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1906
1907/* An M_MASK with the SH and ME fields fixed. */
1908#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1909
1910/* An MD form instruction. */
eca8f888 1911#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
b9adb4a6
FB		 1912#define MD_MASK MD (0x3f, 0x7, 1)
1913
1914/* An MD_MASK with the MB field fixed. */
1915#define MDMB_MASK (MD_MASK | MB6_MASK)
1916
1917/* An MD_MASK with the SH field fixed. */
1918#define MDSH_MASK (MD_MASK | SH6_MASK)
1919
1920/* An MDS form instruction. */
eca8f888 1921#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
b9adb4a6
FB		 1922#define MDS_MASK MDS (0x3f, 0xf, 1)
1923
1924/* An MDS_MASK with the MB field fixed. */
1925#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1926
1927/* An SC form instruction. */
eca8f888
BS		 1928#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1929#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1930
1931/* An VX form instruction. */
1932#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1933
1934/* The mask for an VX form instruction. */
1935#define VX_MASK VX(0x3f, 0x7ff)
1936
1937/* An VA form instruction. */
1938#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1939
1940/* The mask for an VA form instruction. */
1941#define VXA_MASK VXA(0x3f, 0x3f)
1942
1943/* An VXR form instruction. */
1944#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1945
1946/* The mask for a VXR form instruction. */
1947#define VXR_MASK VXR(0x3f, 0x3ff, 1)
b9adb4a6
FB		 1948
1949/* An X form instruction. */
eca8f888 1950#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
b9adb4a6
FB		 1951
1952/* An X form instruction with the RC bit specified. */
1953#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1954
1955/* The mask for an X form instruction. */
1956#define X_MASK XRC (0x3f, 0x3ff, 1)
1957
1958/* An X_MASK with the RA field fixed. */
1959#define XRA_MASK (X_MASK | RA_MASK)
1960
1961/* An X_MASK with the RB field fixed. */
1962#define XRB_MASK (X_MASK | RB_MASK)
1963
1964/* An X_MASK with the RT field fixed. */
1965#define XRT_MASK (X_MASK | RT_MASK)
1966
1967/* An X_MASK with the RA and RB fields fixed. */
1968#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1969
eca8f888
BS		 1970/* An XRARB_MASK, but with the L bit clear. */
1971#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1972
b9adb4a6
FB		 1973/* An X_MASK with the RT and RA fields fixed. */
1974#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1975
eca8f888
BS		 1976/* An XRTRA_MASK, but with L bit clear. */
1977#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1978
1979/* An X form instruction with the L bit specified. */
1980#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
b9adb4a6
FB		 1981
1982/* The mask for an X form comparison instruction. */
eca8f888 1983#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
b9adb4a6
FB		 1984
1985/* The mask for an X form comparison instruction with the L field
1986 fixed. */
eca8f888 1987#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
b9adb4a6
FB		 1988
1989/* An X form trap instruction with the TO field specified. */
eca8f888 1990#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
b9adb4a6
FB		 1991#define XTO_MASK (X_MASK | TO_MASK)
1992
eca8f888
BS		 1993/* An X form tlb instruction with the SH field specified. */
1994#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1995#define XTLB_MASK (X_MASK | SH_MASK)
1996
1997/* An X form sync instruction. */
1998#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1999
2000/* An X form sync instruction with everything filled in except the LS field. */
2001#define XSYNC_MASK (0xff9fffff)
2002
2003/* An X form AltiVec dss instruction. */
2004#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2005#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2006
b9adb4a6 2007/* An XFL form instruction. */
eca8f888
BS		 2008#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2009#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
2010
2011/* An X form isel instruction. */
2012#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2013#define XISEL_MASK XISEL(0x3f, 0x1f)
b9adb4a6
FB		 2014
2015/* An XL form instruction with the LK field set to 0. */
eca8f888 2016#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
b9adb4a6
FB		 2017
2018/* An XL form instruction which uses the LK field. */
2019#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2020
2021/* The mask for an XL form instruction. */
2022#define XL_MASK XLLK (0x3f, 0x3ff, 1)
2023
2024/* An XL form instruction which explicitly sets the BO field. */
2025#define XLO(op, bo, xop, lk) \
eca8f888 2026 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
b9adb4a6
FB		 2027#define XLO_MASK (XL_MASK | BO_MASK)
2028
2029/* An XL form instruction which explicitly sets the y bit of the BO
2030 field. */
eca8f888 2031#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
b9adb4a6
FB		 2032#define XLYLK_MASK (XL_MASK | Y_MASK)
2033
2034/* An XL form instruction which sets the BO field and the condition
2035 bits of the BI field. */
2036#define XLOCB(op, bo, cb, xop, lk) \
eca8f888 2037 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
b9adb4a6
FB		 2038#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2039
2040/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2041#define XLBB_MASK (XL_MASK | BB_MASK)
2042#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2043#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2044
eca8f888
BS		 2045/* A mask for branch instructions using the BH field. */
2046#define XLBH_MASK (XL_MASK | (0x1c << 11))
2047
b9adb4a6
FB		 2048/* An XL_MASK with the BO and BB fields fixed. */
2049#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2050
2051/* An XL_MASK with the BO, BI and BB fields fixed. */
2052#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2053
2054/* An XO form instruction. */
2055#define XO(op, xop, oe, rc) \
eca8f888 2056 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
b9adb4a6
FB		 2057#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2058
2059/* An XO_MASK with the RB field fixed. */
2060#define XORB_MASK (XO_MASK | RB_MASK)
2061
2062/* An XS form instruction. */
eca8f888 2063#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
b9adb4a6
FB		 2064#define XS_MASK XS (0x3f, 0x1ff, 1)
2065
2066/* A mask for the FXM version of an XFX form instruction. */
eca8f888 2067#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
b9adb4a6
FB		 2068
2069/* An XFX form instruction with the FXM field filled in. */
eca8f888
BS		 2070#define XFXM(op, xop, fxm, p4) \
2071 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2072 | ((unsigned long)(p4) << 20))
b9adb4a6
FB		 2073
2074/* An XFX form instruction with the SPR field filled in. */
2075#define XSPR(op, xop, spr) \
eca8f888 2076 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
b9adb4a6
FB		 2077#define XSPR_MASK (X_MASK | SPR_MASK)
2078
2079/* An XFX form instruction with the SPR field filled in except for the
2080 SPRBAT field. */
2081#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2082
2083/* An XFX form instruction with the SPR field filled in except for the
2084 SPRG field. */
eca8f888
BS		 2085#define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16))
2086
2087/* An X form instruction with everything filled in except the E field. */
2088#define XE_MASK (0xffff7fff)
2089
2090/* An X form user context instruction. */
2091#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2092#define XUC_MASK XUC(0x3f, 0x1f)
b9adb4a6
FB		 2093
2094/* The BO encodings used in extended conditional branch mnemonics. */
2095#define BODNZF (0x0)
2096#define BODNZFP (0x1)
2097#define BODZF (0x2)
2098#define BODZFP (0x3)
b9adb4a6
FB		 2099#define BODNZT (0x8)
2100#define BODNZTP (0x9)
2101#define BODZT (0xa)
2102#define BODZTP (0xb)
eca8f888
BS		 2103
2104#define BOF (0x4)
2105#define BOFP (0x5)
2106#define BOFM4 (0x6)
2107#define BOFP4 (0x7)
b9adb4a6
FB		 2108#define BOT (0xc)
2109#define BOTP (0xd)
eca8f888
BS		 2110#define BOTM4 (0xe)
2111#define BOTP4 (0xf)
2112
b9adb4a6
FB		 2113#define BODNZ (0x10)
2114#define BODNZP (0x11)
2115#define BODZ (0x12)
2116#define BODZP (0x13)
eca8f888
BS		 2117#define BODNZM4 (0x18)
2118#define BODNZP4 (0x19)
2119#define BODZM4 (0x1a)
2120#define BODZP4 (0x1b)
2121
b9adb4a6
FB		 2122#define BOU (0x14)
2123
2124/* The BI condition bit encodings used in extended conditional branch
2125 mnemonics. */
2126#define CBLT (0)
2127#define CBGT (1)
2128#define CBEQ (2)
2129#define CBSO (3)
2130
2131/* The TO encodings used in extended trap mnemonics. */
2132#define TOLGT (0x1)
2133#define TOLLT (0x2)
2134#define TOEQ (0x4)
2135#define TOLGE (0x5)
2136#define TOLNL (0x5)
2137#define TOLLE (0x6)
2138#define TOLNG (0x6)
2139#define TOGT (0x8)
2140#define TOGE (0xc)
2141#define TONL (0xc)
2142#define TOLT (0x10)
2143#define TOLE (0x14)
2144#define TONG (0x14)
2145#define TONE (0x18)
2146#define TOU (0x1f)
2147\f
2148/* Smaller names for the flags so each entry in the opcodes table will
2149 fit on a single line. */
eca8f888
BS		 2150#undef PPC
2151#define PPC PPC_OPCODE_PPC
2152#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2153#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
2154#define POWER4 PPC_OPCODE_POWER4
2155#define POWER5 PPC_OPCODE_POWER5
2156#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
2157#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
2158#define PPC403 PPC_OPCODE_403
2159#define PPC405 PPC403
2160#define PPC440 PPC_OPCODE_440
2161#define PPC750 PPC
2162#define PPC860 PPC
2163#define PPCVEC PPC_OPCODE_ALTIVEC
2164#define POWER PPC_OPCODE_POWER
2165#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2166#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2167#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
2168#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2169#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
2170#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
2171#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
2172#define MFDEC1 PPC_OPCODE_POWER
2173#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
2174#define BOOKE PPC_OPCODE_BOOKE
2175#define BOOKE64 PPC_OPCODE_BOOKE64
2176#define CLASSIC PPC_OPCODE_CLASSIC
2177#define PPCE300 PPC_OPCODE_E300
2178#define PPCSPE PPC_OPCODE_SPE
2179#define PPCISEL PPC_OPCODE_ISEL
2180#define PPCEFS PPC_OPCODE_EFS
2181#define PPCBRLK PPC_OPCODE_BRLOCK
2182#define PPCPMR PPC_OPCODE_PMR
2183#define PPCCHLK PPC_OPCODE_CACHELCK
2184#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
2185#define PPCRFMCI PPC_OPCODE_RFMCI
b9adb4a6
FB		 2186\f
2187/* The opcode table.
2188
2189 The format of the opcode table is:
2190
2191 NAME OPCODE MASK FLAGS { OPERANDS }
2192
2193 NAME is the name of the instruction.
2194 OPCODE is the instruction opcode.
2195 MASK is the opcode mask; this is used to tell the disassembler
2196 which bits in the actual opcode must match OPCODE.
2197 FLAGS are flags indicated what processors support the instruction.
2198 OPERANDS is the list of operands.
2199
2200 The disassembler reads the table in order and prints the first
2201 instruction which matches, so this table is sorted to put more
2202 specific instructions before more general instructions. It is also
2203 sorted by major opcode. */
2204
2205const struct powerpc_opcode powerpc_opcodes[] = {
eca8f888
BS		 2206{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
2207{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
2208{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
2209{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
2210{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
2211{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
2212{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2213{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
2214{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
2215{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
2216{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
2217{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
2218{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
2219{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
2220{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
2221{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
2222
2223{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
2224{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
2225{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
2226{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
2227{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
2228{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
2229{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
2230{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
2231{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
2232{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
2233{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2234{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
2235{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
2236{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
2237{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
2238{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
2239{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
2240{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
2241{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
2242{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
2243{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
2244{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
2245{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
2246{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
2247{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
2248{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
2249{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
2250{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
2251{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
2252{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2253
2254{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2255{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2256{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2257{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2258{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2259{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2260{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2261{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2262{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2263{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2264{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2265{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2266{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2267{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2268{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2269{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2270{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2271{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2272{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2273{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2274{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2275{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2276{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2277{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2278{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2279{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2280{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2281{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2282{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2283{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2284{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2285{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2286{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2287{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2288{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2289{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2290{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2291{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2292{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2293{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2294{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2295{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2296{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2297{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2298{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2299{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2300{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2301{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2302{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2303{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2304{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2305{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2306{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2307{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2308{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2309{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2310{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2311{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2312{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2313{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2314{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2315{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2316{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2317{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2318{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2319{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2320{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2321{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2322{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2323{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2324{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2325{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2326{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2327{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2328{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2329{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2330{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2331{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2332{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2333{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2334{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2335{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2336{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2337{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2338{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
2339{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
2340
2341 /* Double-precision opcodes. */
2342 /* Some of these conflict with AltiVec, so move them before, since
2343 PPCVEC includes the PPC_OPCODE_PPC set. */
2344{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
2345{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2346{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2347{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2348{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2349{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2350{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2351{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2352{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2353{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2354{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2355{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2356{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2357{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2358{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2359{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2360{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2361{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2362{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2363{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2364{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2365{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2366{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2367{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2368{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2369{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2370{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2371{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2372{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2373 /* End of double-precision opcodes. */
2374
2375{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2376{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2377{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2378{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2379{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2380{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2381{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2382{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2383{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2384{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2385{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2386{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2387{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2388{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2389{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2390{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2391{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2392{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2393{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2394{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2395{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2396{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2397{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2398{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2399{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2400{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2401{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2402{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2403{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2404{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2405{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2406{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2407{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2408{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2409{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2410{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2411{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2412{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2413{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2414{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2415{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2416{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2417{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2418{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2419{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2420{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2421{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2422{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2423{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2424{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2425{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2426{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2427{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2428{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2429{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2430{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2431{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2432{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2433{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2434{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2435{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2436{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2437{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2438{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2439{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2440{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2441{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2442{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2443{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2444{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2445{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2446{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2447{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2448{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2449{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2450{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2451{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2452{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2453{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2454{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2455{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2456{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2457{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2458{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2459{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2460{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2461{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2462{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2463{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2464{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2465{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2466{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2467{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2468{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2469{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2470{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2471{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2472{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2473{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2474{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2475{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2476{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2477{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2478{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2479{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2480{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2481{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2482{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2483{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2484{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2485{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2486{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2487{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2488{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2489{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2490{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2491{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2492{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2493{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2494{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2495{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2496{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2497{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2498{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2499{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2500{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2501{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2502{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2503{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2504{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2505{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2506{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2507{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2508{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2509{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2510{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2511{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2512{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2513{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2514{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2515{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2516{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2517{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2518{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2519{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2520{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2521{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2522{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2523{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2524{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2525{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2526{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2527{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2528{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2529{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2530
2531{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2532{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2533{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2534{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2535{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2536{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2537{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2538{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2539{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2540{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2541{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2542{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2543{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2544
2545{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2546
2547{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2548{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2549{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2550{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2551{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2552{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2553{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2554{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2555{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2556{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2557
2558{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2559{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2560{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2561{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2562{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2563{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2564{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2565{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2566{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2567{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2568{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2569{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2570{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2571{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2572
2573{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2574{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2575{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2576{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2577{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2578{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2579
2580{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2581{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2582{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2583{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2584{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2585{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2586{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2587{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2588{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2589{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2590{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2591{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2592{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2593{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2594{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2595{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2596{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2597{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2598{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2599{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2600{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2601{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2602
2603{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2604{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2605{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2606{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2607{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2608{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2609{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2610{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2611{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2612{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2613{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2614{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2615{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2616{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2617
2618{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2619{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2620{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2621{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2622{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2623{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2624{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2625{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2626{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2627{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2628{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2629{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2630{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2631{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2632{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2633{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2634{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2635{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2636{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2637{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2638{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2639{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2640{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2641
2642{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2643{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2644{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2645{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2646{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2647{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2648{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2649{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2650{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2651{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2652{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2653{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2654{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2655{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2656{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2657{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2658{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2659{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2660{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2661{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2662{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2663{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2664{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2665
2666{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2667{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2668{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2669{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2670{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2671{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2672{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2673{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2674{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2675{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2676{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2677{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2678{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2679{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2680{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2681{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2682
2683{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2684{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2685{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2686{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2687{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2688{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2689{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2690{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2691{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2692{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2693{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2694{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2695
2696{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2697{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2698{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2699{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2700{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2701{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2702{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2703{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2704{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2705{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2706{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2707{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2708
2709{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2710{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2711{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2712{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2713{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2714{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2715
2716{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2717{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2718{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2719{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2720{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2721{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2722
2723{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2724{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2725{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2726{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2727{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2728{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2729{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2730{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2731
2732{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2733{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2734
2735{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2736{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2737{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2738{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2739
2740{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2741{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2742{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2743{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2744
2745{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2746{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2747{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2748{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2749{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2750{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2751{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2752{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2753
2754{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2755{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2756{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2757{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2758
2759{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2760{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2761{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2762{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2763
2764{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2765{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2766{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2767{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2768
2769{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2770{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2771{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2772{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2773
2774{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2775
2776{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2777{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2778
2779{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2780{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2781
2782{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2783{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2784
2785{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2786
2787{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2788{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2789{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2790{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2791
2792{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2793{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
b9adb4a6 2794{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
eca8f888 2795{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
b9adb4a6 2796
eca8f888
BS		 2797{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2798{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
b9adb4a6 2799{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
eca8f888
BS		 2800{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2801
2802{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2803{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2804{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2805
2806{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2807{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2808{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2809
2810{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2811{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2812{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2813{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2814{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2815{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2816
2817{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2818{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2819{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2820{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2821{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2822
2823{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2824{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2825{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2826{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2827{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2828{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2829{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2830{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2831{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2832{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2833{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2834{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2835{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2836{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2837{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2838{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2839{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2840{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2841{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2842{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2843{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2844{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2845{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2846{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2847{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2848{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2849{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2850{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2851{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2852{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2853{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2854{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2855{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2856{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2857{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2858{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2859{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2860{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2861{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2862{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2863{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2864{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2865{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2866{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2867{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2868{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2869{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2870{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2871{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2872{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2873{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2874{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2875{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2876{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2877{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2878{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2879{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2880{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2881{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2882{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2883{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2884{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2885{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2886{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2887{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2888{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2889{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2890{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2891{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2892{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2893{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2894{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2895{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2896{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2897{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2898{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2899{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2900{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2901{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2902{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2903{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2904{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2905{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2906{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2907{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2908{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2909{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2910{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2911{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2912{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2913{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2914{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2915{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2916{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2917{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2918{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2919{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2920{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2921{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2922{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2923{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2924{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2925{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2926{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2927{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2928{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2929{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2930{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2931{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2932{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2933{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2934{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2935{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2936{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2937{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2938{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2939{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2940{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2941{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2942{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2943{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2944{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2945{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2946{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2947{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2948{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2949{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2950{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2951{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2952{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2953{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2954{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2955{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2956{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2957{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2958{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2959{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2960{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2961{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2962{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2963{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2964{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2965{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2966{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2967{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2968{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2969{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2970{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2971{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2972{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2973{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2974{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2975{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2976{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2977{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2978{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2979{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2980{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2981{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2982{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2983{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2984{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2985{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2986{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2987{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2988{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2989{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2990{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2991{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2992{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2993{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2994{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2995{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2996{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2997{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2998{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2999{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
3000{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
3001{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
3002{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
3003{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
3004{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
3005{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
3006{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
3007{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
3008{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
3009{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
3010{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
3011{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
3012{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
3013{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
3014{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
3015{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
3016{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
3017{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
3018{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
3019{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
3020{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
3021{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
3022{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
3023{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
3024{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
3025{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
3026{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
3027{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
3028{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
3029{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
3030{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
3031{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
3032{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
3033{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
3034{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
3035{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
3036{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
3037{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
3038{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
3039{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
3040{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
3041{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
3042{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
3043{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
3044{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
3045{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
3046{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
3047{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
3048{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
3049{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
3050{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
3051{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
3052{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
3053{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
3054{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
3055{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
3056{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
3057{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
3058{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
3059{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
3060{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
3061{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
3062{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
3063{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
3064{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
3065{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
3066{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
3067{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
3068{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
3069{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
3070{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
3071{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
3072{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
3073{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
3074{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
3075{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
3076{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
3077{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
3078{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
3079{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
3080{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
3081{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
3082{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
3083{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
3084{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
3085{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
3086{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
3087
3088{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
3089{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
3090{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
3091{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
b9adb4a6
FB		 3092{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
3093
eca8f888
BS		 3094{ "b", B(18,0,0), B_MASK, COM, { LI } },
3095{ "bl", B(18,0,1), B_MASK, COM, { LI } },
3096{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
3097{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
3098
3099{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
3100
3101{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
3102{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
3103{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
3104{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
3105{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
3106{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
3107{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
3108{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
3109{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
3110{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
3111{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
3112{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
3113{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
3114{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
3115{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
3116{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
3117{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
3118{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
3119{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
3120{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
3121{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
3122{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
3123{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
3124{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
3125{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3126{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3127{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3128{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3129{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3130{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3131{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3132{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3133{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3134{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3135{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3136{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3137{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3138{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3139{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3140{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3141{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3142{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3143{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3144{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3145{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3146{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3147{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3148{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3149{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3150{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3151{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3152{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3153{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3154{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3155{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3156{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3157{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3158{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3159{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3160{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3161{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3162{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3163{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3164{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3165{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3166{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3167{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3168{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3169{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3170{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3171{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3172{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3173{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3174{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3175{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3176{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3177{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3178{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3179{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3180{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3181{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3182{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3183{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3184{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3185{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3186{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3187{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3188{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3189{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3190{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3191{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3192{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3193{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3194{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3195{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3196{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3197{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3198{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3199{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3200{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3201{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3202{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3203{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3204{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3205{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3206{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3207{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3208{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3209{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3210{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3211{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3212{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3213{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3214{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3215{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3216{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3217{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3218{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3219{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3220{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3221{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3222{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3223{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3224{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3225{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3226{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3227{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3228{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3229{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3230{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3231{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3232{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3233{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3234{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3235{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3236{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3237{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3238{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3239{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3240{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3241{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3242{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3243{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3244{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3245{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3246{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3247{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3248{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3249{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3250{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3251{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3252{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3253{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3254{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3255{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3256{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3257{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3258{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3259{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3260{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3261{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3262{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3263{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3264{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3265{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3266{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3267{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3268{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3269{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3270{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
3271{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3272{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3273{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3274{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3275{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3276{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
3277{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3278{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3279{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3280{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3281{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3282{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
3283{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3284{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3285{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3286{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3287{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3288{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
3289{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3290{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3291{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3292{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3293{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3294{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3295{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3296{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3297{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3298{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3299{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3300{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3301{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3302{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3303{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3304{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3305{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3306{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3307{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3308{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3309{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3310{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3311{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3312{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3313{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3314{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3315{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3316{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3317{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3318{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3319{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
3320{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
3321{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
3322{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
3323
3324{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
3325
3326{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
3327{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
3328{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
3329
3330{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
3331{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
b9adb4a6
FB		 3332
3333{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
3334
eca8f888
BS		 3335{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
3336
3337{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
3338{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
3339
3340{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3341{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
3342
3343{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
3344
3345{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
3346
3347{ "hrfid", XL(19,274), 0xffffffff, POWER5, { 0 } },
3348
3349{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3350{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
3351
3352{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
3353
3354{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
3355{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
3356
3357{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
3358{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
3359{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3360{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3361{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3362{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3363{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3364{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3365{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3366{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3367{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3368{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3369{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3370{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3371{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3372{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3373{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3374{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3375{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3376{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3377{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3378{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3379{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3380{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3381{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3382{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3383{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3384{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3385{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3386{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3387{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3388{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3389{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3390{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3391{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3392{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3393{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3394{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3395{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3396{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3397{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3398{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3399{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3400{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3401{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3402{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3403{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3404{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3405{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3406{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3407{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3408{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3409{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3410{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3411{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3412{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3413{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3414{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3415{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3416{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3417{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3418{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3419{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3420{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3421{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3422{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3423{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3424{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3425{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3426{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3427{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3428{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3429{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3430{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3431{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3432{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3433{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3434{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3435{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3436{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3437{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3438{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3439{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3440{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3441{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3442{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3443{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3444{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3445{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3446{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3447{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3448{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3449{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3450{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3451{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3452{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3453{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3454{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3455{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3456{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3457{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3458{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3459{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3460{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3461{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3462{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3463{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3464{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3465{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3466{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3467{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3468{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3469{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3470{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3471{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3472{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3473{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3474{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3475{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3476{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3477{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3478{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3479{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3480{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3481{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3482{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3483{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3484{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3485{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3486{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3487{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3488{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3489{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3490{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3491{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3492{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3493{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3494{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3495{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3496{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3497{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3498{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3499{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3500{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3501{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3502{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3503{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3504{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3505{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3506{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3507{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3508{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3509
3510{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3511{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3512
3513{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3514{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3515
3516{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3517{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3518{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3519{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3520{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3521{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3522{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3523{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3524
3525{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3526{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3527
3528{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3529{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3530{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3531{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3532
3533{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3534{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3535{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3536{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3537{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3538{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3539
3540{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3541{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3542{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3543
3544{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3545{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3546
3547{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3548{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3549
3550{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3551{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3552
3553{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3554{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3555
3556{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3557{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3558
3559{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3560{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3561{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3562{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3563{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3564{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3565
3566{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3567{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3568
3569{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3570{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3571
3572{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3573{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3574
3575{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3576{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3577{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3578{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3579
3580{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3581{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3582
3583{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3584{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
b9adb4a6 3585{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
eca8f888
BS		 3586{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3587
3588{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3589{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3590{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3591{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3592{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3593{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3594{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3595{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3596{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3597{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3598{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3599{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3600{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3601{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3602{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3603{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3604{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3605{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3606{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3607{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3608{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3609{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3610{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3611{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3612{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3613{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3614{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3615{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3616{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3617{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3618{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3619
3620{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3621{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 3622{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
eca8f888
BS		 3623{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3624{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3625{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3626{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3627{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 3628{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
eca8f888
BS		 3629{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3630{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6
FB		 3631{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3632
eca8f888
BS		 3633{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3634{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
b9adb4a6 3635
eca8f888
BS		 3636{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3637{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3638{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3639{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3640{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3641{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3642{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3643{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6
FB		 3644
3645{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3646{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3647
eca8f888
BS		 3648{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3649{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3650{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3651{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3652
3653{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3654{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
3655{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3656
3657{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } },
3658
3659{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3660
3661{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
3662{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
b9adb4a6 3663
eca8f888
BS		 3664{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3665{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 3666
eca8f888
BS		 3667{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3668{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3669{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3670{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
b9adb4a6 3671
eca8f888
BS		 3672{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3673{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3674{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3675{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
b9adb4a6 3676
eca8f888
BS		 3677{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3678{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
b9adb4a6 3679
eca8f888
BS		 3680{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3681{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
b9adb4a6 3682
eca8f888
BS		 3683{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3684{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 3685
eca8f888 3686{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
b9adb4a6 3687
eca8f888 3688{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
b9adb4a6 3689
eca8f888
BS		 3690{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3691{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3692{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3693{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
b9adb4a6
FB		 3694
3695{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3696{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3697{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3698{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3699{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3700{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3701{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3702{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3703
eca8f888 3704{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
b9adb4a6
FB		 3705
3706{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3707
eca8f888
BS		 3708{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3709{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3710
3711{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3712
3713{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3714
3715{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3716{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3717
3718{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3719{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3720
3721{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3722{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3723{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3724{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3725{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3726{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3727{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3728{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3729{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3730{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3731{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3732{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3733{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3734{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3735{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3736
3737{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3738{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
b9adb4a6
FB		 3739
3740{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3741{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3742
eca8f888
BS		 3743{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3744{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
b9adb4a6 3745
eca8f888
BS		 3746{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3747
3748{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3749
3750{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } },
b9adb4a6
FB		 3751
3752{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3753
eca8f888
BS		 3754{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3755
3756{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3757
3758{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3759
3760{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3761{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3762{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3763{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3764
3765{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3766{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3767{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3768{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3769
3770{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3771
3772{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3773
3774{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3775
3776{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3777
3778{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3779{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3780{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3781{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3782
3783{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3784
3785{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3786
3787{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3788
3789{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3790
3791{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3792{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3793{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3794{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3795{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3796{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3797{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3798{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3799
3800{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3801{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3802{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3803{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3804{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3805{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3806{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3807{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3808
3809{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3810
3811{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3812{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
3813{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3814
3815{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3816
3817{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3818
3819{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3820
3821{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3822{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3823
3824{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3825
3826{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
b9adb4a6 3827
eca8f888
BS		 3828{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3829{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 3830
eca8f888
BS		 3831{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3832{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 3833
eca8f888 3834{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
b9adb4a6 3835
eca8f888
BS		 3836{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3837{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
b9adb4a6 3838
eca8f888 3839{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
b9adb4a6 3840
eca8f888 3841{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
b9adb4a6 3842
eca8f888
BS		 3843{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3844{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
b9adb4a6 3845
eca8f888
BS		 3846{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3847{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
b9adb4a6 3848
eca8f888 3849{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
b9adb4a6 3850
eca8f888
BS		 3851{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3852{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3853{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3854{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3855{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3856{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3857{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3858{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
b9adb4a6 3859
eca8f888
BS		 3860{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3861{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3862{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3863{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3864{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3865{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3866{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3867{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
b9adb4a6 3868
eca8f888 3869{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
b9adb4a6 3870
eca8f888 3871{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
b9adb4a6 3872
eca8f888 3873{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
b9adb4a6 3874
eca8f888
BS		 3875{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3876{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 3877
eca8f888
BS		 3878{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3879{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 3880
eca8f888 3881{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
b9adb4a6 3882
eca8f888 3883{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
b9adb4a6 3884
eca8f888
BS		 3885{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3886{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3887{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3888{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3889{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3890{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3891{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3892{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
b9adb4a6 3893
eca8f888
BS		 3894{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3895{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3896{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3897{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
b9adb4a6 3898
eca8f888
BS		 3899{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3900{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3901{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3902{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3903{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3904{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3905{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3906{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
b9adb4a6 3907
eca8f888
BS		 3908{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3909{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3910{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3911{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3912{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3913{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3914{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3915{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 3916
eca8f888
BS		 3917{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3918{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3919{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
b9adb4a6 3920
eca8f888 3921{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
b9adb4a6 3922
eca8f888
BS		 3923{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3924
3925{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3926{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3927
3928{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3929
3930{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3931
3932{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3933
3934{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3935{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3936{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3937{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3938
3939{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3940{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3941{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3942{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3943{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3944{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3945{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3946{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3947
3948{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3949
3950{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3951
3952{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3953{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3954
3955{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3956
3957{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3958
3959{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3960{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3961
3962{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3963
3964{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3965
3966{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3967{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
b9adb4a6
FB		 3968
3969{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3970
eca8f888
BS		 3971{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3972
3973{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3974{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3975
3976{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3977
3978{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3979{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3980{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3981{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3982{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3983{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3984{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3985{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3986{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3987{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3988{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3989{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3990{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3991{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3992{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3993{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3994{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3995{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3996{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3997{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3998{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3999{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
4000{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
4001{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
4002{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
4003{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
4004{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
4005{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
4006{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
4007{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
4008{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
4009{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
4010{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
4011{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
4012{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
4013
4014{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
4015{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
4016{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
4017{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
4018
4019{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
4020
4021{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
4022{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
4023{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
4024{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
4025{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
4026{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
4027{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
4028{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
4029{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
4030{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
4031{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
4032{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
4033{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
4034{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
4035{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
4036{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
4037{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
4038{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
4039{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
4040{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
4041{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
4042{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
4043{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
4044{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
4045{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
4046{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
4047{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
4048{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
4049{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
4050{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
4051{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
4052{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
4053{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
4054{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
4055{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
4056{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
4057{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
4058{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
4059{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
4060{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
4061{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
4062{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
4063{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
4064{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
4065{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
4066{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
4067{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
4068{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
4069{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
4070{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
4071{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
4072{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
4073{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
4074{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
4075{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
4076{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
4077{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
4078{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
4079{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
4080{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
4081{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
4082{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
4083{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
4084{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
4085{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
4086{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
4087{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
4088{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
4089{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
4090{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
4091{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
4092{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
4093{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
4094{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
4095{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
4096{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
4097{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
4098{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
4099{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
4100{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
4101{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
4102{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
4103{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
4104{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
4105{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
4106{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
4107{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
4108{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
4109{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
4110{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
4111{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
4112{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
4113{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
4114{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
4115{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
4116{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
4117{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
4118{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
4119{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
4120{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
4121{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
4122{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
4123{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
4124{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
4125{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
4126{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
4127{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
4128{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
4129{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
4130{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
4131{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4132{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
4133{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
4134{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
4135{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
4136{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
4137{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
4138{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
4139{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
4140{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
4141{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
4142{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
4143{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
4144{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
4145{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
4146{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
4147{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
4148{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
4149{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
4150{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
4151{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
4152{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
4153{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
4154{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
4155{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
4156{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
4157{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
4158{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
4159{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
4160{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
4161{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
4162{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
4163{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
4164{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
4165{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
4166{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
4167{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
4168{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
4169{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
4170{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
4171{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
4172{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
4173{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
4174{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
4175{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
4176{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
4177{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
4178{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
4179{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
4180{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
4181{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
4182{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
4183{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
4184{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
4185{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
4186{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
4187{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
4188{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
4189{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
4190{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
4191{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
4192{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
4193{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
4194{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
4195{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
4196{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
4197{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
4198{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
4199{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
4200{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
4201{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
4202{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
4203{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
4204{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
4205{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
4206{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
4207{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
4208
4209{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
4210
4211{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4212{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4213
4214{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
4215
4216{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
4217
4218{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4219{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4220
4221{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
4222
4223{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
4224{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
4225{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
4226{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
4227
4228{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
4229{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
4230{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
4231{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
b9adb4a6
FB		 4232
4233{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
4234
eca8f888
BS		 4235{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
4236
4237{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
4238
4239{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
4240
4241{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
4242
4243{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
b9adb4a6 4244
eca8f888
BS		 4245{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4246{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
b9adb4a6 4247
eca8f888
BS		 4248{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4249{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
b9adb4a6 4250
eca8f888
BS		 4251{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
4252
4253{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
4254
4255{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
b9adb4a6
FB		 4256
4257{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4258
4259{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4260
4261{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4262
4263{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4264
eca8f888
BS		 4265{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
4266{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
b9adb4a6 4267
eca8f888
BS		 4268{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
4269{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
b9adb4a6 4270
eca8f888 4271{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
b9adb4a6 4272
eca8f888 4273{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
b9adb4a6 4274
eca8f888 4275{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
b9adb4a6 4276
eca8f888
BS		 4277{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
4278
4279{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4280
4281{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
4282{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4283{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
4284{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
4285
4286{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
4287{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
4288{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
4289{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
4290{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
4291{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
4292{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
4293{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
4294{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
4295{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
4296{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
4297{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
4298{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
4299{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
4300{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
4301{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
4302{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
4303{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
4304{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
4305{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
4306{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
4307{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
4308{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
4309{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
4310{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
4311{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
4312{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
4313{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
4314{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
4315{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
4316{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
4317{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
4318{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
4319{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
4320{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
4321
4322{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4323{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4324
4325{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4326{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4327{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4328{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4329
4330{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4331{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
b9adb4a6
FB		 4332
4333{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4334{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4335{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4336{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4337
eca8f888
BS		 4338{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
4339{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
4340{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
4341{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
4342{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
4343{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
4344{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
4345{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
4346{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
4347{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
4348{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
4349{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
4350{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
4351{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
4352{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
4353{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
4354{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
4355{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
4356{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
4357{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
4358{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
4359{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
4360{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
4361{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
4362{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
4363{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
4364{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
4365{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
4366{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
4367{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
4368{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
4369{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
4370{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
4371{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
4372{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
4373{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
4374{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
4375{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
4376{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
4377{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
4378{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
4379{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
4380{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
4381{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
4382{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
4383{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
4384{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
4385{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
4386{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
4387{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
4388{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
4389{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4390{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4391{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4392{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4393{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
4394{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
4395{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
4396{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
4397{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
4398{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
4399{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4400{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
4401{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
4402{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
4403{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
4404{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
4405{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
4406{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
4407{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
4408{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
4409{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
4410{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
4411{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
4412{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
4413{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
4414{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
4415{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
4416{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
4417{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
4418{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4419{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
4420{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4421{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4422{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4423{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4424{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4425{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4426{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4427{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4428{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4429{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4430{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4431{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4432{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4433{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4434{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4435{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4436{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4437{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4438{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4439{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4440{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4441{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
4442{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4443{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4444{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4445{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4446{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4447{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4448{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4449{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4450{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4451{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4452{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4453{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4454{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4455{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4456{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4457{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4458{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4459{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4460{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4461{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4462{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4463{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4464{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4465{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4466{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4467{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4468{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4469{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4470{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4471{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4472{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4473{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4474{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4475{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4476{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4477{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4478{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4479{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4480{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4481{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4482{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4483{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4484{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4485{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4486{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4487{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4488{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4489{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
b9adb4a6
FB		 4490
4491{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4492
eca8f888
BS		 4493{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4494{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
b9adb4a6 4495
eca8f888 4496{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
b9adb4a6 4497
eca8f888
BS		 4498{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4499
4500{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4501
4502{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4503
4504{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4505{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4506{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4507{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4508{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4509{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4510
4511{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4512{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4513{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4514{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4515
4516{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4517{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
b9adb4a6
FB		 4518
4519{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4520{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4521{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4522{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4523
eca8f888
BS		 4524{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4525
4526{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
b9adb4a6
FB		 4527
4528{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4529
eca8f888
BS		 4530{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4531
4532{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
b9adb4a6 4533
eca8f888
BS		 4534{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4535{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
b9adb4a6 4536
eca8f888 4537{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
b9adb4a6 4538
eca8f888
BS		 4539{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4540{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 4541
eca8f888
BS		 4542{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4543{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 4544
eca8f888 4545{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
b9adb4a6 4546
eca8f888
BS		 4547{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4548{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4549{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4550{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
b9adb4a6 4551
eca8f888
BS		 4552{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4553{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4554
eca8f888
BS		 4555{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4556{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4557
4558{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4559{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4560
4561{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4562
4563{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4564
4565{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
b9adb4a6
FB		 4566
4567{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4568
eca8f888
BS		 4569{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4570
4571{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4572
4573{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4574
4575{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4576{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4577
4578{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4579{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4580{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4581{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4582{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4583
4584{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4585
4586{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4587
4588{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4589
4590{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4591
4592{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4593
4594{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4595
4596{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4597
4598{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4599{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4600
4601{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4602{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4603
4604{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
b9adb4a6 4605
eca8f888
BS		 4606{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4607{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4608
eca8f888
BS		 4609{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4610{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4611
eca8f888 4612{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
b9adb4a6 4613
eca8f888 4614{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
b9adb4a6 4615
eca8f888 4616{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
b9adb4a6 4617
eca8f888
BS		 4618{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4619{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
b9adb4a6 4620
eca8f888 4621{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
b9adb4a6 4622
eca8f888
BS		 4623{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4624{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
b9adb4a6 4625
eca8f888 4626{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
b9adb4a6 4627
eca8f888
BS		 4628{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4629{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4630
eca8f888
BS		 4631{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4632{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4633
eca8f888 4634{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
b9adb4a6 4635
eca8f888 4636{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
b9adb4a6 4637
eca8f888 4638{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
b9adb4a6 4639
eca8f888
BS		 4640{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4641{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
b9adb4a6 4642
eca8f888 4643{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
b9adb4a6 4644
eca8f888 4645{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
b9adb4a6 4646
eca8f888
BS		 4647{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4648{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
b9adb4a6 4649
eca8f888 4650{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
b9adb4a6 4651
eca8f888
BS		 4652{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4653{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4654{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4655{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
b9adb4a6 4656
eca8f888
BS		 4657{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4658{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
b9adb4a6 4659
eca8f888 4660{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
b9adb4a6 4661
eca8f888
BS		 4662{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4663{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
b9adb4a6 4664
eca8f888 4665{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 4666
eca8f888
BS		 4667{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4668{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
b9adb4a6 4669
eca8f888
BS		 4670{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4671{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4672{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4673{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
b9adb4a6 4674
eca8f888
BS		 4675{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4676
4677{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
b9adb4a6
FB		 4678{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4679
eca8f888
BS		 4680{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4681{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4682{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4683{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4684
4685{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4686
4687{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4688
4689{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4690{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4691
eca8f888
BS		 4692{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4693{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4694
eca8f888
BS		 4695{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4696{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4697{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4698{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
b9adb4a6 4699
eca8f888 4700{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
b9adb4a6 4701
eca8f888
BS		 4702{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4703
4704{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4705{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4706{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4707
4708{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4709{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
b9adb4a6
FB		 4710
4711{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4712{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4713
eca8f888
BS		 4714{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4715
4716{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4717
4718{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4719{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4720{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4721{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
b9adb4a6
FB		 4722
4723{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4724
eca8f888
BS		 4725{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4726
4727{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4728{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4729
4730{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
b9adb4a6 4731
eca8f888
BS		 4732{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4733{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
b9adb4a6 4734
eca8f888
BS		 4735{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4736
4737{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
b9adb4a6
FB		 4738{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4739{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4740
eca8f888
BS		 4741{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4742
4743{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4744{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4745{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4746{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4747{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4748{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4749{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4750{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4751{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4752{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4753{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4754{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4755
4756{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4757{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
b9adb4a6 4758
eca8f888
BS		 4759{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4760{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
b9adb4a6 4761
eca8f888 4762{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
b9adb4a6 4763
eca8f888 4764{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
b9adb4a6 4765
eca8f888
BS		 4766{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4767{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
b9adb4a6 4768
eca8f888
BS		 4769{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4770{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
b9adb4a6 4771
eca8f888 4772{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
b9adb4a6 4773
eca8f888 4774{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
b9adb4a6 4775
eca8f888 4776{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
b9adb4a6 4777
eca8f888 4778{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
b9adb4a6 4779
eca8f888 4780{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
b9adb4a6 4781
eca8f888 4782{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
b9adb4a6 4783
eca8f888 4784{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
b9adb4a6 4785
eca8f888 4786{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
b9adb4a6 4787
eca8f888
BS		 4788{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4789{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
b9adb4a6 4790
eca8f888
BS		 4791{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4792{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
b9adb4a6 4793
eca8f888 4794{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
b9adb4a6 4795
eca8f888 4796{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
b9adb4a6 4797
eca8f888 4798{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
b9adb4a6 4799
eca8f888 4800{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
b9adb4a6 4801
eca8f888 4802{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
b9adb4a6 4803
eca8f888 4804{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
b9adb4a6 4805
eca8f888 4806{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
b9adb4a6 4807
eca8f888 4808{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
b9adb4a6 4809
eca8f888 4810{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
b9adb4a6 4811
eca8f888 4812{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
b9adb4a6 4813
eca8f888 4814{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
b9adb4a6 4815
eca8f888
BS		 4816{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4817{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4818{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4819{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4820{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4821{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4822{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4823{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4824{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4825{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4826{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4827{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4828{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4829{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
b9adb4a6 4830
eca8f888
BS		 4831{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4832
4833{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4834
4835{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
b9adb4a6
FB		 4836
4837{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4838{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4839
4840{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4841{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4842
4843{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4844{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4845
4846{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4847{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4848
4849{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4850{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4851
4852{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4853{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4854
eca8f888
BS		 4855{ "frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER5, { FRT, FRB } },
4856{ "frsqrtes.",A(59,26,1), AFRAFRC_MASK, POWER5, { FRT, FRB } },
4857
b9adb4a6
FB		 4858{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4859{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4860
4861{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4862{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4863
4864{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4865{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4866
4867{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4868{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4869
4870{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4871
4872{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4873
eca8f888
BS		 4874{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4875{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4876{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4877{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4878{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4879{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4880{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4881{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4882{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4883{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4884{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4885{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
b9adb4a6 4886
eca8f888 4887{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
b9adb4a6 4888
eca8f888 4889{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
b9adb4a6 4890
eca8f888 4891{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
b9adb4a6 4892
eca8f888
BS		 4893{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4894
4895{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4896{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4897
4898{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
b9adb4a6 4899{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
eca8f888 4900{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
b9adb4a6
FB		 4901{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4902
eca8f888 4903{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
b9adb4a6 4904{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
eca8f888 4905{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
b9adb4a6
FB		 4906{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4907
eca8f888
BS		 4908{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4909{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4910{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4911{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
b9adb4a6 4912
eca8f888
BS		 4913{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4914{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4915{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4916{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
b9adb4a6 4917
eca8f888
BS		 4918{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4919{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4920{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4921{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
b9adb4a6 4922
eca8f888
BS		 4923{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4924{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
b9adb4a6
FB		 4925
4926{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4927{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4928
eca8f888
BS		 4929{ "fre", A(63,24,0), AFRAFRC_MASK, POWER5, { FRT, FRB } },
4930{ "fre.", A(63,24,1), AFRAFRC_MASK, POWER5, { FRT, FRB } },
4931
4932{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4933{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4934{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4935{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
b9adb4a6
FB		 4936
4937{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4938{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4939
eca8f888
BS		 4940{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4941{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4942{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4943{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
b9adb4a6 4944
eca8f888
BS		 4945{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4946{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4947{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4948{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
b9adb4a6 4949
eca8f888
BS		 4950{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4951{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4952{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4953{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
b9adb4a6 4954
eca8f888
BS		 4955{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4956{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4957{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4958{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
b9adb4a6 4959
eca8f888 4960{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
b9adb4a6 4961
eca8f888
BS		 4962{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4963{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
b9adb4a6 4964
eca8f888
BS		 4965{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4966{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
b9adb4a6 4967
eca8f888 4968{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
b9adb4a6 4969
eca8f888
BS		 4970{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4971{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
b9adb4a6 4972
eca8f888
BS		 4973{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4974{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
b9adb4a6 4975
eca8f888
BS		 4976{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4977{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
b9adb4a6 4978
eca8f888
BS		 4979{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4980{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
b9adb4a6 4981
eca8f888
BS		 4982{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4983{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
b9adb4a6 4984
eca8f888
BS		 4985{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
4986{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
4987{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
4988{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
4989{ "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
4990{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
4991{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
4992{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
b9adb4a6 4993
eca8f888
BS		 4994{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4995{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
b9adb4a6 4996
eca8f888
BS		 4997{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4998{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
b9adb4a6 4999
eca8f888
BS		 5000{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
5001{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
b9adb4a6 5002
eca8f888
BS		 5003{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
5004{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
5005
5006{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
5007{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
b9adb4a6
FB		 5008
5009};
5010
5011const int powerpc_num_opcodes =
5012 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
5013\f
5014/* The macro table. This is only used by the assembler. */
5015
eca8f888
BS		 5016/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
5017 when x=0; 32-x when x is between 1 and 31; are negative if x is
5018 negative; and are 32 or more otherwise. This is what you want
5019 when, for instance, you are emulating a right shift by a
5020 rotate-left-and-mask, because the underlying instructions support
5021 shifts of size 0 but not shifts of size 32. By comparison, when
5022 extracting x bits from some word you want to use just 32-x, because
5023 the underlying instructions don't support extracting 0 bits but do
5024 support extracting the whole word (32 bits in this case). */
b9adb4a6 5025
eca8f888
BS		 5026const struct powerpc_macro powerpc_macros[] = {
5027{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
5028{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
5029{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
5030{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
5031{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
5032{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
5033{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
5034{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
5035{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
5036{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
5037{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
5038{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
5039{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
5040{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
5041{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
5042{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
5043
5044{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
5045{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
5046{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
5047{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
5048{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
5049{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5050{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
5051{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5052{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
5053{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
5054{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
5055{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
5056{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
5057{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
5058{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5059{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5060{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5061{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5062{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
5063{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
5064{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
5065{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
b9adb4a6
FB		 5066};
5067
5068const int powerpc_num_macros =
5069 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
5070
eca8f888
BS		 5071/* This file provides several disassembler functions, all of which use
5072 the disassembler interface defined in dis-asm.h. Several functions
5073 are provided because this file handles disassembly for the PowerPC
5074 in both big and little endian mode and also for the POWER (RS/6000)
5075 chip. */
5076
5077static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int);
5078
5079/* Determine which set of machines to disassemble for. PPC403/601 or
5080 BookE. For convenience, also disassemble instructions supported
5081 by the AltiVec vector unit. */
5082
43ef9eb2 5083static int
eca8f888
BS		 5084powerpc_dialect (struct disassemble_info *info)
5085{
5086 int dialect = PPC_OPCODE_PPC;
5087
5088 if (BFD_DEFAULT_TARGET_SIZE == 64)
5089 dialect |= PPC_OPCODE_64;
5090
5091 if (info->disassembler_options
5092 && strstr (info->disassembler_options, "booke") != NULL)
5093 dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
5094 else if ((info->mach == bfd_mach_ppc_e500)
5095 || (info->disassembler_options
5096 && strstr (info->disassembler_options, "e500") != NULL))
5097 dialect |= (PPC_OPCODE_BOOKE
5098 | PPC_OPCODE_SPE | PPC_OPCODE_ISEL
5099 | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
5100 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
5101 | PPC_OPCODE_RFMCI);
5102 else if (info->disassembler_options
5103 && strstr (info->disassembler_options, "efs") != NULL)
5104 dialect |= PPC_OPCODE_EFS;
5105 else if (info->disassembler_options
5106 && strstr (info->disassembler_options, "e300") != NULL)
5107 dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON;
5108 else
5109 dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
5110 | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC);
5111
5112 if (info->disassembler_options
5113 && strstr (info->disassembler_options, "power4") != NULL)
5114 dialect |= PPC_OPCODE_POWER4;
5115
5116 if (info->disassembler_options
5117 && strstr (info->disassembler_options, "power5") != NULL)
5118 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
5119
5120 if (info->disassembler_options
5121 && strstr (info->disassembler_options, "any") != NULL)
5122 dialect |= PPC_OPCODE_ANY;
5123
5124 if (info->disassembler_options)
5125 {
5126 if (strstr (info->disassembler_options, "32") != NULL)
5127 dialect &= ~PPC_OPCODE_64;
5128 else if (strstr (info->disassembler_options, "64") != NULL)
5129 dialect |= PPC_OPCODE_64;
a2458627 5130 }
eca8f888
BS		 5131
5132 info->private_data = (char *) 0 + dialect;
5133 return dialect;
5134}
5135
5136/* Qemu default */
5137int
5138print_insn_ppc (bfd_vma memaddr, struct disassemble_info *info)
5139{
5140 int dialect = (char *) info->private_data - (char *) 0;
5141 return print_insn_powerpc (memaddr, info, 1, dialect);
5142}
5143
5144/* Print a big endian PowerPC instruction. */
5145
5146int
5147print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
5148{
5149 int dialect = (char *) info->private_data - (char *) 0;
5150 return print_insn_powerpc (memaddr, info, 1, dialect);
5151}
5152
5153/* Print a little endian PowerPC instruction. */
5154
5155int
5156print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
5157{
5158 int dialect = (char *) info->private_data - (char *) 0;
5159 return print_insn_powerpc (memaddr, info, 0, dialect);
5160}
5161
5162/* Print a POWER (RS/6000) instruction. */
5163
5164int
5165print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
5166{
5167 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
b9adb4a6
FB		 5168}
5169
5170/* Print a PowerPC or POWER instruction. */
5171
7c08dbf3 5172static int
eca8f888
BS		 5173print_insn_powerpc (bfd_vma memaddr,
5174 struct disassemble_info *info,
5175 int bigendian,
b9adb4a6
FB		 5176 int dialect)
5177{
eca8f888
BS		 5178 bfd_byte buffer[4];
5179 int status;
5180 unsigned long insn;
b9adb4a6
FB		 5181 const struct powerpc_opcode *opcode;
5182 const struct powerpc_opcode *opcode_end;
eca8f888
BS		 5183 unsigned long op;
5184
5185 if (dialect == 0)
5186 dialect = powerpc_dialect (info);
5187
5188 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
5189 if (status != 0)
5190 {
5191 (*info->memory_error_func) (status, memaddr, info);
5192 return -1;
5193 }
5194
5195 if (bigendian)
5196 insn = bfd_getb32 (buffer);
5197 else
5198 insn = bfd_getl32 (buffer);
b9adb4a6
FB		 5199
5200 /* Get the major opcode of the instruction. */
5201 op = PPC_OP (insn);
5202
5203 /* Find the first match in the opcode table. We could speed this up
5204 a bit by doing a binary search on the major opcode. */
5205 opcode_end = powerpc_opcodes + powerpc_num_opcodes;
eca8f888 5206 again:
b9adb4a6
FB		 5207 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
5208 {
eca8f888 5209 unsigned long table_op;
b9adb4a6
FB		 5210 const unsigned char *opindex;
5211 const struct powerpc_operand *operand;
5212 int invalid;
5213 int need_comma;
5214 int need_paren;
5215
5216 table_op = PPC_OP (opcode->opcode);
5217 if (op < table_op)
eca8f888 5218 break;
b9adb4a6 5219 if (op > table_op)
eca8f888 5220 continue;
b9adb4a6
FB		 5221
5222 if ((insn & opcode->mask) != opcode->opcode
5223 || (opcode->flags & dialect) == 0)
eca8f888 5224 continue;
b9adb4a6
FB		 5225
5226 /* Make two passes over the operands. First see if any of them
eca8f888
BS		 5227 have extraction functions, and, if they do, make sure the
5228 instruction is valid. */
b9adb4a6
FB		 5229 invalid = 0;
5230 for (opindex = opcode->operands; *opindex != 0; opindex++)
eca8f888
BS		 5231 {
5232 operand = powerpc_operands + *opindex;
5233 if (operand->extract)
5234 (*operand->extract) (insn, dialect, &invalid);
5235 }
b9adb4a6 5236 if (invalid)
eca8f888 5237 continue;
b9adb4a6
FB		 5238
5239 /* The instruction is valid. */
b9adb4a6 5240 if (opcode->operands[0] != 0)
eca8f888
BS		 5241 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
5242 else
5243 (*info->fprintf_func) (info->stream, "%s", opcode->name);
b9adb4a6
FB		 5244
5245 /* Now extract and print the operands. */
5246 need_comma = 0;
5247 need_paren = 0;
5248 for (opindex = opcode->operands; *opindex != 0; opindex++)
eca8f888
BS		 5249 {
5250 long value;
5251
5252 operand = powerpc_operands + *opindex;
5253
5254 /* Operands that are marked FAKE are simply ignored. We
5255 already made sure that the extract function considered
5256 the instruction to be valid. */
5257 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
5258 continue;
5259
5260 /* Extract the value from the instruction. */
5261 if (operand->extract)
5262 value = (*operand->extract) (insn, dialect, &invalid);
5263 else
5264 {
5265 value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
5266 if ((operand->flags & PPC_OPERAND_SIGNED) != 0
5267 && (value & (1 << (operand->bits - 1))) != 0)
5268 value -= 1 << operand->bits;
5269 }
5270
5271 /* If the operand is optional, and the value is zero, don't
5272 print anything. */
5273 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
5274 && (operand->flags & PPC_OPERAND_NEXT) == 0
5275 && value == 0)
5276 continue;
5277
5278 if (need_comma)
5279 {
5280 (*info->fprintf_func) (info->stream, ",");
5281 need_comma = 0;
5282 }
5283
5284 /* Print the operand as directed by the flags. */
5285 if ((operand->flags & PPC_OPERAND_GPR) != 0
5286 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
5287 (*info->fprintf_func) (info->stream, "r%ld", value);
5288 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
5289 (*info->fprintf_func) (info->stream, "f%ld", value);
5290 else if ((operand->flags & PPC_OPERAND_VR) != 0)
5291 (*info->fprintf_func) (info->stream, "v%ld", value);
5292 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
5293 (*info->print_address_func) (memaddr + value, info);
5294 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
5295 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
5296 else if ((operand->flags & PPC_OPERAND_CR) == 0
5297 || (dialect & PPC_OPCODE_PPC) == 0)
5298 (*info->fprintf_func) (info->stream, "%ld", value);
5299 else
5300 {
5301 if (operand->bits == 3)
5302 (*info->fprintf_func) (info->stream, "cr%ld", value);
5303 else
b9adb4a6 5304 {
eca8f888
BS		 5305 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
5306 int cr;
5307 int cc;
5308
5309 cr = value >> 2;
5310 if (cr != 0)
5311 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
5312 cc = value & 3;
5313 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
5314 }
b9adb4a6
FB		 5315 }
5316
5317 if (need_paren)
5318 {
eca8f888 5319 (*info->fprintf_func) (info->stream, ")");
b9adb4a6
FB		 5320 need_paren = 0;
5321 }
5322
5323 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
5324 need_comma = 1;
5325 else
5326 {
eca8f888 5327 (*info->fprintf_func) (info->stream, "(");
b9adb4a6
FB		 5328 need_paren = 1;
5329 }
5330 }
5331
5332 /* We have found and printed an instruction; return. */
5333 return 4;
5334 }
5335
eca8f888
BS		 5336 if ((dialect & PPC_OPCODE_ANY) != 0)
5337 {
5338 dialect = ~PPC_OPCODE_ANY;
5339 goto again;
5340 }
5341
b9adb4a6 5342 /* We could not find a match. */
eca8f888 5343 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
b9adb4a6
FB		 5344
5345 return 4;
5346}
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