[qemu.git] / hw / arm / xilinx_zynq.c

/*
 * Xilinx Zynq Baseboard System emulation.
 *
 * Copyright (c) 2010 Xilinx.
 * Copyright (c) 2012 Peter A.G. Crosthwaite ([email protected])
 * Copyright (c) 2012 Petalogix Pty Ltd.
 * Written by Haibing Ma
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "net/net.h"
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/block/flash.h"
#include "hw/loader.h"
#include "hw/misc/zynq-xadc.h"
#include "hw/ssi/ssi.h"
#include "qemu/error-report.h"
#include "hw/sd/sdhci.h"
#include "hw/char/cadence_uart.h"
#include "hw/net/cadence_gem.h"
#include "hw/cpu/a9mpcore.h"

#define NUM_SPI_FLASHES 4
#define NUM_QSPI_FLASHES 2
#define NUM_QSPI_BUSSES 2

#define FLASH_SIZE (64 * 1024 * 1024)
#define FLASH_SECTOR_SIZE (128 * 1024)

#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */

#define MPCORE_PERIPHBASE 0xF8F00000
#define ZYNQ_BOARD_MIDR 0x413FC090

static const int dma_irqs[8] = {
    46, 47, 48, 49, 72, 73, 74, 75
};

#define BOARD_SETUP_ADDR        0x100

#define SLCR_LOCK_OFFSET        0x004
#define SLCR_UNLOCK_OFFSET      0x008
#define SLCR_ARM_PLL_OFFSET     0x100

#define SLCR_XILINX_UNLOCK_KEY  0xdf0d
#define SLCR_XILINX_LOCK_KEY    0x767b

#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080  /* Datasheet: UG585 (v1.12.1) */

#define ARMV7_IMM16(x) (extract32((x),  0, 12) | \
                        extract32((x), 12,  4) << 16)

/* Write immediate val to address r0 + addr. r0 should contain base offset
 * of the SLCR block. Clobbers r1.
 */

#define SLCR_WRITE(addr, val) \
    0xe3001000 + ARMV7_IMM16(extract32((val),  0, 16)), /* movw r1 ... */ \
    0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
    0xe5801000 + (addr)

static void zynq_write_board_setup(ARMCPU *cpu,
                                   const struct arm_boot_info *info)
{
    int n;
    uint32_t board_setup_blob[] = {
        0xe3a004f8, /* mov r0, #0xf8000000 */
        SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
        SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
        SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
        0xe12fff1e, /* bx lr */
    };
    for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
        board_setup_blob[n] = tswap32(board_setup_blob[n]);
    }
    rom_add_blob_fixed("board-setup", board_setup_blob,
                       sizeof(board_setup_blob), BOARD_SETUP_ADDR);
}

static struct arm_boot_info zynq_binfo = {};

static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
{
    DeviceState *dev;
    SysBusDevice *s;

    dev = qdev_create(NULL, TYPE_CADENCE_GEM);
    if (nd->used) {
        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
        qdev_set_nic_properties(dev, nd);
    }
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, base);
    sysbus_connect_irq(s, 0, irq);
}

static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
                                         bool is_qspi)
{
    DeviceState *dev;
    SysBusDevice *busdev;
    SSIBus *spi;
    DeviceState *flash_dev;
    int i, j;
    int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;
    int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;

    dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
    qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
    qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
    qdev_prop_set_uint8(dev, "num-busses", num_busses);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, base_addr);
    if (is_qspi) {
        sysbus_mmio_map(busdev, 1, 0xFC000000);
    }
    sysbus_connect_irq(busdev, 0, irq);

    for (i = 0; i < num_busses; ++i) {
        char bus_name[16];
        qemu_irq cs_line;

        snprintf(bus_name, 16, "spi%d", i);
        spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);

        for (j = 0; j < num_ss; ++j) {
            DriveInfo *dinfo = drive_get_next(IF_MTD);
            flash_dev = ssi_create_slave_no_init(spi, "n25q128");
            if (dinfo) {
                qdev_prop_set_drive(flash_dev, "drive",
                                    blk_by_legacy_dinfo(dinfo), &error_fatal);
            }
            qdev_init_nofail(flash_dev);

            cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
            sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
        }
    }

}

static void zynq_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    ARMCPU *cpu;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
    MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
    DeviceState *dev;
    SysBusDevice *busdev;
    qemu_irq pic[64];
    int n;

    cpu = ARM_CPU(object_new(machine->cpu_type));

    /* By default A9 CPUs have EL3 enabled.  This board does not
     * currently support EL3 so the CPU EL3 property is disabled before
     * realization.
     */
    if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
        object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
    }

    object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
                            &error_fatal);
    object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
                            &error_fatal);
    object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);

    /* max 2GB ram */
    if (ram_size > 0x80000000) {
        ram_size = 0x80000000;
    }

    /* DDR remapped to address zero.  */
    memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
                                         ram_size);
    memory_region_add_subregion(address_space_mem, 0, ext_ram);

    /* 256K of on-chip memory */
    memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
                           &error_fatal);
    memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);

    DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);

    /* AMD */
    pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          FLASH_SECTOR_SIZE, 1,
                          1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
                          0);

    dev = qdev_create(NULL, "xilinx,zynq_slcr");
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);

    dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
    qdev_prop_set_uint32(dev, "num-cpu", 1);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
    sysbus_connect_irq(busdev, 0,
                       qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));

    for (n = 0; n < 64; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
    zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
    zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);

    sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
    sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);

    cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
    cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));

    sysbus_create_varargs("cadence_ttc", 0xF8001000,
            pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
    sysbus_create_varargs("cadence_ttc", 0xF8002000,
            pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);

    gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
    gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);

    for (n = 0; n < 2; n++) {
        int hci_irq = n ? 79 : 56;
        hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
        DriveInfo *di;
        BlockBackend *blk;
        DeviceState *carddev;

        /* Compatible with:
         * - SD Host Controller Specification Version 2.0 Part A2
         * - SDIO Specification Version 2.0
         * - MMC Specification Version 3.31
         */
        dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
        qdev_prop_set_uint8(dev, "sd-spec-version", 2);
        qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
        qdev_init_nofail(dev);
        sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);

        di = drive_get_next(IF_SD);
        blk = di ? blk_by_legacy_dinfo(di) : NULL;
        carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
        qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
        object_property_set_bool(OBJECT(carddev), true, "realized",
                                 &error_fatal);
    }

    dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);

    dev = qdev_create(NULL, "pl330");
    qdev_prop_set_uint8(dev, "num_chnls",  8);
    qdev_prop_set_uint8(dev, "num_periph_req",  4);
    qdev_prop_set_uint8(dev, "num_events",  16);

    qdev_prop_set_uint8(dev, "data_width",  64);
    qdev_prop_set_uint8(dev, "wr_cap",  8);
    qdev_prop_set_uint8(dev, "wr_q_dep",  16);
    qdev_prop_set_uint8(dev, "rd_cap",  8);
    qdev_prop_set_uint8(dev, "rd_q_dep",  16);
    qdev_prop_set_uint16(dev, "data_buffer_dep",  256);

    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, 0xF8003000);
    sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
    for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
        sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
    }

    dev = qdev_create(NULL, "xlnx.ps7-dev-cfg");
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
    sysbus_mmio_map(busdev, 0, 0xF8007000);

    zynq_binfo.ram_size = ram_size;
    zynq_binfo.nb_cpus = 1;
    zynq_binfo.board_id = 0xd32;
    zynq_binfo.loader_start = 0;
    zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
    zynq_binfo.write_board_setup = zynq_write_board_setup;

    arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
}

static void zynq_machine_init(MachineClass *mc)
{
    mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
    mc->init = zynq_init;
    mc->max_cpus = 1;
    mc->no_sdcard = 1;
    mc->ignore_memory_transaction_failures = true;
    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
}

DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
Commit	Line	Data
e3260506 PC	1	/*
	2	* Xilinx Zynq Baseboard System emulation.
	3	*
	4	* Copyright (c) 2010 Xilinx.
	5	* Copyright (c) 2012 Peter A.G. Crosthwaite ([email protected])
	6	* Copyright (c) 2012 Petalogix Pty Ltd.
	7	* Written by Haibing Ma
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*
	14	* You should have received a copy of the GNU General Public License along
	15	* with this program; if not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
12b16722	18	#include "qemu/osdep.h"
77a7cc61	19	#include "qemu/units.h"
da34e65c	20	#include "qapi/error.h"
4771d756	21	#include "cpu.h"
83c9f4ca	22	#include "hw/sysbus.h"
12ec8bd5	23	#include "hw/arm/boot.h"
1422e32d	24	#include "net/net.h"
022c62cb	25	#include "exec/address-spaces.h"
9c17d615	26	#include "sysemu/sysemu.h"
83c9f4ca	27	#include "hw/boards.h"
0d09e41a	28	#include "hw/block/flash.h"
83c9f4ca	29	#include "hw/loader.h"
74fcbd22	30	#include "hw/misc/zynq-xadc.h"
8fd06719	31	#include "hw/ssi/ssi.h"
d8bbdcf8	32	#include "qemu/error-report.h"
c2de81e2	33	#include "hw/sd/sdhci.h"
4be12ea0	34	#include "hw/char/cadence_uart.h"
c2de81e2 PMD	35	#include "hw/net/cadence_gem.h"
c2de81e2 PMD	36	#include "hw/cpu/a9mpcore.h"
559d489f PC	37
559d489f PC	38	#define NUM_SPI_FLASHES 4
7b482bcf PC	39	#define NUM_QSPI_FLASHES 2
7b482bcf PC	40	#define NUM_QSPI_BUSSES 2
e3260506 PC	41
	42	#define FLASH_SIZE (64 * 1024 * 1024)
	43	#define FLASH_SECTOR_SIZE (128 * 1024)
	44
	45	#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
	46
c2577128	47	#define MPCORE_PERIPHBASE 0xF8F00000
b48adc0d	48	#define ZYNQ_BOARD_MIDR 0x413FC090
c2577128	49
7451afb6 PC	50	static const int dma_irqs[8] = {
	51	46, 47, 48, 49, 72, 73, 74, 75
	52	};
	53
c3a9a689 PC	54	#define BOARD_SETUP_ADDR 0x100
	55
	56	#define SLCR_LOCK_OFFSET 0x004
	57	#define SLCR_UNLOCK_OFFSET 0x008
	58	#define SLCR_ARM_PLL_OFFSET 0x100
	59
	60	#define SLCR_XILINX_UNLOCK_KEY 0xdf0d
	61	#define SLCR_XILINX_LOCK_KEY 0x767b
	62
27a49d3b PMD	63	#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
27a49d3b PMD	64
c3a9a689 PC	65	#define ARMV7_IMM16(x) (extract32((x), 0, 12) \| \
	66	extract32((x), 12, 4) << 16)
	67
	68	/* Write immediate val to address r0 + addr. r0 should contain base offset
	69	* of the SLCR block. Clobbers r1.
	70	*/
	71
	72	#define SLCR_WRITE(addr, val) \
	73	0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \
	74	0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
	75	0xe5801000 + (addr)
	76
	77	static void zynq_write_board_setup(ARMCPU *cpu,
	78	const struct arm_boot_info *info)
	79	{
	80	int n;
	81	uint32_t board_setup_blob[] = {
	82	0xe3a004f8, /* mov r0, #0xf8000000 */
	83	SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
	84	SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
	85	SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
	86	0xe12fff1e, /* bx lr */
	87	};
	88	for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
	89	board_setup_blob[n] = tswap32(board_setup_blob[n]);
	90	}
	91	rom_add_blob_fixed("board-setup", board_setup_blob,
	92	sizeof(board_setup_blob), BOARD_SETUP_ADDR);
	93	}
	94
e3260506 PC	95	static struct arm_boot_info zynq_binfo = {};
	96
	97	static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
	98	{
	99	DeviceState *dev;
	100	SysBusDevice *s;
	101
c2de81e2	102	dev = qdev_create(NULL, TYPE_CADENCE_GEM);
7fcd57e8	103	if (nd->used) {
c2de81e2	104	qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
7fcd57e8 PC	105	qdev_set_nic_properties(dev, nd);
7fcd57e8 PC	106	}
e3260506	107	qdev_init_nofail(dev);
1356b98d	108	s = SYS_BUS_DEVICE(dev);
e3260506 PC	109	sysbus_mmio_map(s, 0, base);
	110	sysbus_connect_irq(s, 0, irq);
	111	}
	112
7b482bcf PC	113	static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
7b482bcf PC	114	bool is_qspi)
559d489f PC	115	{
	116	DeviceState *dev;
	117	SysBusDevice *busdev;
	118	SSIBus *spi;
79f5d67e	119	DeviceState *flash_dev;
7b482bcf PC	120	int i, j;
	121	int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
	122	int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
559d489f	123
6b91f015	124	dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
7b482bcf PC	125	qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
	126	qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
	127	qdev_prop_set_uint8(dev, "num-busses", num_busses);
559d489f	128	qdev_init_nofail(dev);
1356b98d	129	busdev = SYS_BUS_DEVICE(dev);
559d489f	130	sysbus_mmio_map(busdev, 0, base_addr);
7b482bcf PC	131	if (is_qspi) {
	132	sysbus_mmio_map(busdev, 1, 0xFC000000);
	133	}
559d489f PC	134	sysbus_connect_irq(busdev, 0, irq);
559d489f PC	135
7b482bcf PC	136	for (i = 0; i < num_busses; ++i) {
7b482bcf PC	137	char bus_name[16];
559d489f PC	138	qemu_irq cs_line;
559d489f PC	139
7b482bcf PC	140	snprintf(bus_name, 16, "spi%d", i);
	141	spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
	142
	143	for (j = 0; j < num_ss; ++j) {
73bce518 PB	144	DriveInfo *dinfo = drive_get_next(IF_MTD);
	145	flash_dev = ssi_create_slave_no_init(spi, "n25q128");
	146	if (dinfo) {
	147	qdev_prop_set_drive(flash_dev, "drive",
	148	blk_by_legacy_dinfo(dinfo), &error_fatal);
	149	}
	150	qdev_init_nofail(flash_dev);
559d489f	151
de77914e	152	cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
7b482bcf PC	153	sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
7b482bcf PC	154	}
559d489f PC	155	}
	156
	157	}
	158
3ef96221	159	static void zynq_init(MachineState *machine)
e3260506	160	{
3ef96221	161	ram_addr_t ram_size = machine->ram_size;
17c2f0bf	162	ARMCPU *cpu;
e3260506 PC	163	MemoryRegion *address_space_mem = get_system_memory();
	164	MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
	165	MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
27a49d3b	166	DeviceState *dev;
e3260506	167	SysBusDevice *busdev;
e3260506	168	qemu_irq pic[64];
e3260506	169	int n;
e3260506	170
ba1ba5cc	171	cpu = ARM_CPU(object_new(machine->cpu_type));
d8bbdcf8	172
61e2f352 GB	173	/* By default A9 CPUs have EL3 enabled. This board does not
	174	* currently support EL3 so the CPU EL3 property is disabled before
	175	* realization.
	176	*/
	177	if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
007b0657	178	object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
b48adc0d AF	179	}
b48adc0d AF	180
007b0657 MA	181	object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
	182	&error_fatal);
	183	object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
	184	&error_fatal);
	185	object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
e3260506 PC	186
	187	/* max 2GB ram */
	188	if (ram_size > 0x80000000) {
	189	ram_size = 0x80000000;
	190	}
	191
	192	/* DDR remapped to address zero. */
c8623c02 DM	193	memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
c8623c02 DM	194	ram_size);
e3260506 PC	195	memory_region_add_subregion(address_space_mem, 0, ext_ram);
	196
	197	/* 256K of on-chip memory */
77a7cc61	198	memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
f8ed85ac	199	&error_fatal);
e3260506 PC	200	memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
	201
	202	DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
	203
	204	/* AMD */
940d5b13	205	pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
4be74634	206	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
ce14710f	207	FLASH_SECTOR_SIZE, 1,
e3260506	208	1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
ce14710f	209	0);
e3260506 PC	210
	211	dev = qdev_create(NULL, "xilinx,zynq_slcr");
	212	qdev_init_nofail(dev);
1356b98d	213	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
e3260506	214
c2de81e2	215	dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
e3260506 PC	216	qdev_prop_set_uint32(dev, "num-cpu", 1);
e3260506 PC	217	qdev_init_nofail(dev);
1356b98d	218	busdev = SYS_BUS_DEVICE(dev);
c2577128	219	sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
e4a6540d PM	220	sysbus_connect_irq(busdev, 0,
e4a6540d PM	221	qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
e3260506 PC	222
	223	for (n = 0; n < 64; n++) {
	224	pic[n] = qdev_get_gpio_in(dev, n);
	225	}
	226
7b482bcf PC	227	zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
	228	zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
	229	zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
559d489f	230
892776ce	231	sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
70ef6a5b	232	sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
892776ce	233
9bca0edb PM	234	cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
9bca0edb PM	235	cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
e3260506 PC	236
	237	sysbus_create_varargs("cadence_ttc", 0xF8001000,
	238	pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
	239	sysbus_create_varargs("cadence_ttc", 0xF8002000,
	240	pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
	241
7fcd57e8 PC	242	gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
7fcd57e8 PC	243	gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
e3260506	244
27a49d3b PMD	245	for (n = 0; n < 2; n++) {
	246	int hci_irq = n ? 79 : 56;
	247	hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
	248	DriveInfo *di;
	249	BlockBackend *blk;
	250	DeviceState *carddev;
	251
	252	/* Compatible with:
	253	* - SD Host Controller Specification Version 2.0 Part A2
	254	* - SDIO Specification Version 2.0
	255	* - MMC Specification Version 3.31
	256	*/
	257	dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
	258	qdev_prop_set_uint8(dev, "sd-spec-version", 2);
	259	qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
	260	qdev_init_nofail(dev);
	261	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
	262	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
	263
	264	di = drive_get_next(IF_SD);
	265	blk = di ? blk_by_legacy_dinfo(di) : NULL;
	266	carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
	267	qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
	268	object_property_set_bool(OBJECT(carddev), true, "realized",
	269	&error_fatal);
	270	}
eb4f566b	271
74fcbd22 GR	272	dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
	273	qdev_init_nofail(dev);
	274	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
	275	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
	276
7451afb6 PC	277	dev = qdev_create(NULL, "pl330");
	278	qdev_prop_set_uint8(dev, "num_chnls", 8);
	279	qdev_prop_set_uint8(dev, "num_periph_req", 4);
	280	qdev_prop_set_uint8(dev, "num_events", 16);
	281
	282	qdev_prop_set_uint8(dev, "data_width", 64);
	283	qdev_prop_set_uint8(dev, "wr_cap", 8);
	284	qdev_prop_set_uint8(dev, "wr_q_dep", 16);
	285	qdev_prop_set_uint8(dev, "rd_cap", 8);
	286	qdev_prop_set_uint8(dev, "rd_q_dep", 16);
	287	qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
	288
	289	qdev_init_nofail(dev);
	290	busdev = SYS_BUS_DEVICE(dev);
	291	sysbus_mmio_map(busdev, 0, 0xF8003000);
	292	sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
5e9fcbd7	293	for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
7451afb6 PC	294	sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
	295	}
	296
f4b99537 PC	297	dev = qdev_create(NULL, "xlnx.ps7-dev-cfg");
	298	qdev_init_nofail(dev);
	299	busdev = SYS_BUS_DEVICE(dev);
	300	sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
	301	sysbus_mmio_map(busdev, 0, 0xF8007000);
	302
e3260506	303	zynq_binfo.ram_size = ram_size;
e3260506 PC	304	zynq_binfo.nb_cpus = 1;
	305	zynq_binfo.board_id = 0xd32;
	306	zynq_binfo.loader_start = 0;
c3a9a689 PC	307	zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
	308	zynq_binfo.write_board_setup = zynq_write_board_setup;
	309
2744ece8	310	arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
e3260506 PC	311	}
e3260506 PC	312
e264d29d	313	static void zynq_machine_init(MachineClass *mc)
e3260506	314	{
e264d29d EH	315	mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
e264d29d EH	316	mc->init = zynq_init;
e264d29d EH	317	mc->max_cpus = 1;
e264d29d EH	318	mc->no_sdcard = 1;
4672cbd7	319	mc->ignore_memory_transaction_failures = true;
ba1ba5cc	320	mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
e3260506 PC	321	}
e3260506 PC	322
e264d29d	323	DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)