[qemu.git] / hw / arm / realview.c

/*
 * ARM RealView Baseboard System emulation.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/arm/primecell.h"
#include "hw/net/lan9118.h"
#include "hw/net/smc91c111.h"
#include "hw/pci/pci.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/i2c/i2c.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
#include "hw/char/pl011.h"
#include "hw/cpu/a9mpcore.h"
#include "hw/intc/realview_gic.h"
#include "hw/irq.h"

#define SMP_BOOT_ADDR 0xe0000000
#define SMP_BOOTREG_ADDR 0x10000030

/* Board init.  */

static struct arm_boot_info realview_binfo = {
    .smp_loader_start = SMP_BOOT_ADDR,
    .smp_bootreg_addr = SMP_BOOTREG_ADDR,
};

/* The following two lists must be consistent.  */
enum realview_board_type {
    BOARD_EB,
    BOARD_EB_MPCORE,
    BOARD_PB_A8,
    BOARD_PBX_A9,
};

static const int realview_board_id[] = {
    0x33b,
    0x33b,
    0x769,
    0x76d
};

static void realview_init(MachineState *machine,
                          enum realview_board_type board_type)
{
    ARMCPU *cpu = NULL;
    CPUARMState *env;
    MemoryRegion *sysmem = get_system_memory();
    MemoryRegion *ram_lo;
    MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
    MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
    MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
    DeviceState *dev, *sysctl, *gpio2, *pl041;
    SysBusDevice *busdev;
    qemu_irq pic[64];
    qemu_irq mmc_irq[2];
    PCIBus *pci_bus = NULL;
    NICInfo *nd;
    I2CBus *i2c;
    int n;
    unsigned int smp_cpus = machine->smp.cpus;
    int done_nic = 0;
    qemu_irq cpu_irq[4];
    int is_mpcore = 0;
    int is_pb = 0;
    uint32_t proc_id = 0;
    uint32_t sys_id;
    ram_addr_t low_ram_size;
    ram_addr_t ram_size = machine->ram_size;
    hwaddr periphbase = 0;

    switch (board_type) {
    case BOARD_EB:
        break;
    case BOARD_EB_MPCORE:
        is_mpcore = 1;
        periphbase = 0x10100000;
        break;
    case BOARD_PB_A8:
        is_pb = 1;
        break;
    case BOARD_PBX_A9:
        is_mpcore = 1;
        is_pb = 1;
        periphbase = 0x1f000000;
        break;
    }

    for (n = 0; n < smp_cpus; n++) {
        Object *cpuobj = object_new(machine->cpu_type);

        /* By default A9,A15 and ARM1176 CPUs have EL3 enabled.  This board
         * does not currently support EL3 so the CPU EL3 property is disabled
         * before realization.
         */
        if (object_property_find(cpuobj, "has_el3", NULL)) {
            object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
        }

        if (is_pb && is_mpcore) {
            object_property_set_int(cpuobj, periphbase, "reset-cbar",
                                    &error_fatal);
        }

        object_property_set_bool(cpuobj, true, "realized", &error_fatal);

        cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
    }
    cpu = ARM_CPU(first_cpu);
    env = &cpu->env;
    if (arm_feature(env, ARM_FEATURE_V7)) {
        if (is_mpcore) {
            proc_id = 0x0c000000;
        } else {
            proc_id = 0x0e000000;
        }
    } else if (arm_feature(env, ARM_FEATURE_V6K)) {
        proc_id = 0x06000000;
    } else if (arm_feature(env, ARM_FEATURE_V6)) {
        proc_id = 0x04000000;
    } else {
        proc_id = 0x02000000;
    }

    if (is_pb && ram_size > 0x20000000) {
        /* Core tile RAM.  */
        ram_lo = g_new(MemoryRegion, 1);
        low_ram_size = ram_size - 0x20000000;
        ram_size = 0x20000000;
        memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size,
                               &error_fatal);
        memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
    }

    memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size,
                           &error_fatal);
    low_ram_size = ram_size;
    if (low_ram_size > 0x10000000)
      low_ram_size = 0x10000000;
    /* SDRAM at address zero.  */
    memory_region_init_alias(ram_alias, NULL, "realview.alias",
                             ram_hi, 0, low_ram_size);
    memory_region_add_subregion(sysmem, 0, ram_alias);
    if (is_pb) {
        /* And again at a high address.  */
        memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
    } else {
        ram_size = low_ram_size;
    }

    sys_id = is_pb ? 0x01780500 : 0xc1400400;
    sysctl = qdev_create(NULL, "realview_sysctl");
    qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
    qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
    qdev_init_nofail(sysctl);
    sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);

    if (is_mpcore) {
        dev = qdev_create(NULL, is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
        qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
        qdev_init_nofail(dev);
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, periphbase);
        for (n = 0; n < smp_cpus; n++) {
            sysbus_connect_irq(busdev, n, cpu_irq[n]);
        }
        sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL);
        /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */
        realview_binfo.gic_cpu_if_addr = periphbase + 0x100;
    } else {
        uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
        /* For now just create the nIRQ GIC, and ignore the others.  */
        dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]);
    }
    for (n = 0; n < 64; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    pl041 = qdev_create(NULL, "pl041");
    qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
    qdev_init_nofail(pl041);
    sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
    sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]);

    sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
    sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);

    pl011_create(0x10009000, pic[12], serial_hd(0));
    pl011_create(0x1000a000, pic[13], serial_hd(1));
    pl011_create(0x1000b000, pic[14], serial_hd(2));
    pl011_create(0x1000c000, pic[15], serial_hd(3));

    /* DMA controller is optional, apparently.  */
    dev = qdev_create(NULL, "pl081");
    object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",
                             &error_fatal);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, 0x10030000);
    sysbus_connect_irq(busdev, 0, pic[24]);

    sysbus_create_simple("sp804", 0x10011000, pic[4]);
    sysbus_create_simple("sp804", 0x10012000, pic[5]);

    sysbus_create_simple("pl061", 0x10013000, pic[6]);
    sysbus_create_simple("pl061", 0x10014000, pic[7]);
    gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);

    sysbus_create_simple("pl111", 0x10020000, pic[23]);

    dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
    /* Wire up MMC card detect and read-only signals. These have
     * to go to both the PL061 GPIO and the sysctl register.
     * Note that the PL181 orders these lines (readonly,inserted)
     * and the PL061 has them the other way about. Also the card
     * detect line is inverted.
     */
    mmc_irq[0] = qemu_irq_split(
        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
        qdev_get_gpio_in(gpio2, 1));
    mmc_irq[1] = qemu_irq_split(
        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
        qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
    qdev_connect_gpio_out(dev, 0, mmc_irq[0]);
    qdev_connect_gpio_out(dev, 1, mmc_irq[1]);

    sysbus_create_simple("pl031", 0x10017000, pic[10]);

    if (!is_pb) {
        dev = qdev_create(NULL, "realview_pci");
        busdev = SYS_BUS_DEVICE(dev);
        qdev_init_nofail(dev);
        sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */
        sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */
        sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */
        sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */
        sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */
        sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */
        sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */
        sysbus_connect_irq(busdev, 0, pic[48]);
        sysbus_connect_irq(busdev, 1, pic[49]);
        sysbus_connect_irq(busdev, 2, pic[50]);
        sysbus_connect_irq(busdev, 3, pic[51]);
        pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
        if (machine_usb(machine)) {
            pci_create_simple(pci_bus, -1, "pci-ohci");
        }
        n = drive_get_max_bus(IF_SCSI);
        while (n >= 0) {
            dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a"));
            lsi53c8xx_handle_legacy_cmdline(dev);
            n--;
        }
    }
    for(n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];

        if (!done_nic && (!nd->model ||
                    strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
            if (is_pb) {
                lan9118_init(nd, 0x4e000000, pic[28]);
            } else {
                smc91c111_init(nd, 0x4e000000, pic[28]);
            }
            done_nic = 1;
        } else {
            if (pci_bus) {
                pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
            }
        }
    }

    dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
    i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
    i2c_create_slave(i2c, "ds1338", 0x68);

    /* Memory map for RealView Emulation Baseboard:  */
    /* 0x10000000 System registers.  */
    /*  0x10001000 System controller.  */
    /* 0x10002000 Two-Wire Serial Bus.  */
    /* 0x10003000 Reserved.  */
    /*  0x10004000 AACI.  */
    /*  0x10005000 MCI.  */
    /* 0x10006000 KMI0.  */
    /* 0x10007000 KMI1.  */
    /*  0x10008000 Character LCD. (EB) */
    /* 0x10009000 UART0.  */
    /* 0x1000a000 UART1.  */
    /* 0x1000b000 UART2.  */
    /* 0x1000c000 UART3.  */
    /*  0x1000d000 SSPI.  */
    /*  0x1000e000 SCI.  */
    /* 0x1000f000 Reserved.  */
    /*  0x10010000 Watchdog.  */
    /* 0x10011000 Timer 0+1.  */
    /* 0x10012000 Timer 2+3.  */
    /*  0x10013000 GPIO 0.  */
    /*  0x10014000 GPIO 1.  */
    /*  0x10015000 GPIO 2.  */
    /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
    /* 0x10017000 RTC.  */
    /*  0x10018000 DMC.  */
    /*  0x10019000 PCI controller config.  */
    /*  0x10020000 CLCD.  */
    /* 0x10030000 DMA Controller.  */
    /* 0x10040000 GIC1. (EB) */
    /*  0x10050000 GIC2. (EB) */
    /*  0x10060000 GIC3. (EB) */
    /*  0x10070000 GIC4. (EB) */
    /*  0x10080000 SMC.  */
    /* 0x1e000000 GIC1. (PB) */
    /*  0x1e001000 GIC2. (PB) */
    /*  0x1e002000 GIC3. (PB) */
    /*  0x1e003000 GIC4. (PB) */
    /*  0x40000000 NOR flash.  */
    /*  0x44000000 DoC flash.  */
    /*  0x48000000 SRAM.  */
    /*  0x4c000000 Configuration flash.  */
    /* 0x4e000000 Ethernet.  */
    /*  0x4f000000 USB.  */
    /*  0x50000000 PISMO.  */
    /*  0x54000000 PISMO.  */
    /*  0x58000000 PISMO.  */
    /*  0x5c000000 PISMO.  */
    /* 0x60000000 PCI.  */
    /* 0x60000000 PCI Self Config.  */
    /* 0x61000000 PCI Config.  */
    /* 0x62000000 PCI IO.  */
    /* 0x63000000 PCI mem 0.  */
    /* 0x64000000 PCI mem 1.  */
    /* 0x68000000 PCI mem 2.  */

    /* ??? Hack to map an additional page of ram for the secondary CPU
       startup code.  I guess this works on real hardware because the
       BootROM happens to be in ROM/flash or in memory that isn't clobbered
       until after Linux boots the secondary CPUs.  */
    memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000,
                           &error_fatal);
    memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);

    realview_binfo.ram_size = ram_size;
    realview_binfo.nb_cpus = smp_cpus;
    realview_binfo.board_id = realview_board_id[board_type];
    realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
    arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo);
}

static void realview_eb_init(MachineState *machine)
{
    realview_init(machine, BOARD_EB);
}

static void realview_eb_mpcore_init(MachineState *machine)
{
    realview_init(machine, BOARD_EB_MPCORE);
}

static void realview_pb_a8_init(MachineState *machine)
{
    realview_init(machine, BOARD_PB_A8);
}

static void realview_pbx_a9_init(MachineState *machine)
{
    realview_init(machine, BOARD_PBX_A9);
}

static void realview_eb_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)";
    mc->init = realview_eb_init;
    mc->block_default_type = IF_SCSI;
    mc->ignore_memory_transaction_failures = true;
    mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
}

static const TypeInfo realview_eb_type = {
    .name = MACHINE_TYPE_NAME("realview-eb"),
    .parent = TYPE_MACHINE,
    .class_init = realview_eb_class_init,
};

static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)";
    mc->init = realview_eb_mpcore_init;
    mc->block_default_type = IF_SCSI;
    mc->max_cpus = 4;
    mc->ignore_memory_transaction_failures = true;
    mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore");
}

static const TypeInfo realview_eb_mpcore_type = {
    .name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
    .parent = TYPE_MACHINE,
    .class_init = realview_eb_mpcore_class_init,
};

static void realview_pb_a8_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "ARM RealView Platform Baseboard for Cortex-A8";
    mc->init = realview_pb_a8_init;
    mc->ignore_memory_transaction_failures = true;
    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8");
}

static const TypeInfo realview_pb_a8_type = {
    .name = MACHINE_TYPE_NAME("realview-pb-a8"),
    .parent = TYPE_MACHINE,
    .class_init = realview_pb_a8_class_init,
};

static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9";
    mc->init = realview_pbx_a9_init;
    mc->max_cpus = 4;
    mc->ignore_memory_transaction_failures = true;
    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
}

static const TypeInfo realview_pbx_a9_type = {
    .name = MACHINE_TYPE_NAME("realview-pbx-a9"),
    .parent = TYPE_MACHINE,
    .class_init = realview_pbx_a9_class_init,
};

static void realview_machine_init(void)
{
    type_register_static(&realview_eb_type);
    type_register_static(&realview_eb_mpcore_type);
    type_register_static(&realview_pb_a8_type);
    type_register_static(&realview_pbx_a9_type);
}

type_init(realview_machine_init)
Commit	Line	Data
5fafdf24	1	/*
e69954b9 PB	2	* ARM RealView Baseboard System emulation.
e69954b9 PB	3	*
a1bb27b1	4	* Copyright (c) 2006-2007 CodeSourcery.
e69954b9 PB	5	* Written by Paul Brook
e69954b9 PB	6	*
8e31bf38	7	* This code is licensed under the GPL.
e69954b9 PB	8	*/
e69954b9 PB	9
12b16722	10	#include "qemu/osdep.h"
da34e65c	11	#include "qapi/error.h"
4771d756	12	#include "cpu.h"
83c9f4ca	13	#include "hw/sysbus.h"
12ec8bd5	14	#include "hw/arm/boot.h"
0d09e41a	15	#include "hw/arm/primecell.h"
66b03dce	16	#include "hw/net/lan9118.h"
437cc27d	17	#include "hw/net/smc91c111.h"
83c9f4ca	18	#include "hw/pci/pci.h"
1422e32d	19	#include "net/net.h"
9c17d615	20	#include "sysemu/sysemu.h"
83c9f4ca	21	#include "hw/boards.h"
0d09e41a	22	#include "hw/i2c/i2c.h"
022c62cb	23	#include "exec/address-spaces.h"
b5a3ca3e	24	#include "qemu/error-report.h"
f0d1d2c1	25	#include "hw/char/pl011.h"
c2de81e2 PMD	26	#include "hw/cpu/a9mpcore.h"
c2de81e2 PMD	27	#include "hw/intc/realview_gic.h"
64552b6b	28	#include "hw/irq.h"
e69954b9	29
0ef849d7	30	#define SMP_BOOT_ADDR 0xe0000000
078758d0	31	#define SMP_BOOTREG_ADDR 0x10000030
eee48504	32
e69954b9 PB	33	/* Board init. */
e69954b9 PB	34
f93eb9ff	35	static struct arm_boot_info realview_binfo = {
0ef849d7	36	.smp_loader_start = SMP_BOOT_ADDR,
078758d0	37	.smp_bootreg_addr = SMP_BOOTREG_ADDR,
f93eb9ff AZ	38	};
f93eb9ff AZ	39
f7c70325	40	/* The following two lists must be consistent. */
c988bfad PB	41	enum realview_board_type {
c988bfad PB	42	BOARD_EB,
0ef849d7	43	BOARD_EB_MPCORE,
f7c70325 PB	44	BOARD_PB_A8,
	45	BOARD_PBX_A9,
	46	};
	47
d05ac8fa	48	static const int realview_board_id[] = {
f7c70325 PB	49	0x33b,
	50	0x33b,
	51	0x769,
	52	0x76d
c988bfad PB	53	};
c988bfad PB	54
3ef96221	55	static void realview_init(MachineState *machine,
db4ff6f1	56	enum realview_board_type board_type)
e69954b9	57	{
9077f01b AF	58	ARMCPU *cpu = NULL;
9077f01b AF	59	CPUARMState *env;
35e87820	60	MemoryRegion *sysmem = get_system_memory();
b1ab03af	61	MemoryRegion *ram_lo;
35e87820 AK	62	MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
	63	MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
	64	MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
03a0e944	65	DeviceState dev, sysctl, gpio2, pl041;
c988bfad	66	SysBusDevice *busdev;
fe7e8758	67	qemu_irq pic[64];
26883c69	68	qemu_irq mmc_irq[2];
29b358f9	69	PCIBus *pci_bus = NULL;
e69954b9	70	NICInfo *nd;
a5c82852	71	I2CBus *i2c;
e69954b9	72	int n;
cc7d44c2	73	unsigned int smp_cpus = machine->smp.cpus;
0ef849d7	74	int done_nic = 0;
9ee6e8bb	75	qemu_irq cpu_irq[4];
f7c70325 PB	76	int is_mpcore = 0;
f7c70325 PB	77	int is_pb = 0;
26e92f65	78	uint32_t proc_id = 0;
0ef849d7 PB	79	uint32_t sys_id;
0ef849d7 PB	80	ram_addr_t low_ram_size;
3ef96221	81	ram_addr_t ram_size = machine->ram_size;
b5a3ca3e	82	hwaddr periphbase = 0;
e69954b9	83
f7c70325 PB	84	switch (board_type) {
	85	case BOARD_EB:
	86	break;
	87	case BOARD_EB_MPCORE:
	88	is_mpcore = 1;
b5a3ca3e	89	periphbase = 0x10100000;
f7c70325 PB	90	break;
	91	case BOARD_PB_A8:
	92	is_pb = 1;
	93	break;
	94	case BOARD_PBX_A9:
	95	is_mpcore = 1;
	96	is_pb = 1;
b5a3ca3e	97	periphbase = 0x1f000000;
f7c70325 PB	98	break;
f7c70325 PB	99	}
b5a3ca3e	100
c988bfad	101	for (n = 0; n < smp_cpus; n++) {
ba1ba5cc	102	Object *cpuobj = object_new(machine->cpu_type);
b5a3ca3e	103
61e2f352 GB	104	/* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board
	105	* does not currently support EL3 so the CPU EL3 property is disabled
	106	* before realization.
	107	*/
	108	if (object_property_find(cpuobj, "has_el3", NULL)) {
007b0657	109	object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
61e2f352 GB	110	}
61e2f352 GB	111
b5a3ca3e	112	if (is_pb && is_mpcore) {
007b0657 MA	113	object_property_set_int(cpuobj, periphbase, "reset-cbar",
007b0657 MA	114	&error_fatal);
b5a3ca3e PM	115	}
b5a3ca3e PM	116
007b0657	117	object_property_set_bool(cpuobj, true, "realized", &error_fatal);
b5a3ca3e PM	118
b5a3ca3e PM	119	cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
aaed909a	120	}
b5a3ca3e	121	cpu = ARM_CPU(first_cpu);
9077f01b	122	env = &cpu->env;
26e92f65	123	if (arm_feature(env, ARM_FEATURE_V7)) {
f7c70325 PB	124	if (is_mpcore) {
	125	proc_id = 0x0c000000;
	126	} else {
	127	proc_id = 0x0e000000;
	128	}
26e92f65 PB	129	} else if (arm_feature(env, ARM_FEATURE_V6K)) {
	130	proc_id = 0x06000000;
	131	} else if (arm_feature(env, ARM_FEATURE_V6)) {
	132	proc_id = 0x04000000;
	133	} else {
	134	proc_id = 0x02000000;
	135	}
aaed909a	136
21a88941 PB	137	if (is_pb && ram_size > 0x20000000) {
21a88941 PB	138	/* Core tile RAM. */
b1ab03af	139	ram_lo = g_new(MemoryRegion, 1);
21a88941 PB	140	low_ram_size = ram_size - 0x20000000;
21a88941 PB	141	ram_size = 0x20000000;
98a99ce0	142	memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size,
f8ed85ac	143	&error_fatal);
35e87820	144	memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
21a88941 PB	145	}
21a88941 PB	146
98a99ce0	147	memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size,
f8ed85ac	148	&error_fatal);
0ef849d7 PB	149	low_ram_size = ram_size;
	150	if (low_ram_size > 0x10000000)
	151	low_ram_size = 0x10000000;
e69954b9	152	/* SDRAM at address zero. */
2c9b15ca	153	memory_region_init_alias(ram_alias, NULL, "realview.alias",
35e87820 AK	154	ram_hi, 0, low_ram_size);
35e87820 AK	155	memory_region_add_subregion(sysmem, 0, ram_alias);
0ef849d7 PB	156	if (is_pb) {
0ef849d7 PB	157	/* And again at a high address. */
35e87820	158	memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
0ef849d7 PB	159	} else {
	160	ram_size = low_ram_size;
	161	}
e69954b9	162
0ef849d7	163	sys_id = is_pb ? 0x01780500 : 0xc1400400;
26883c69 PM	164	sysctl = qdev_create(NULL, "realview_sysctl");
26883c69 PM	165	qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
26883c69	166	qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
7a65c8cc	167	qdev_init_nofail(sysctl);
1356b98d	168	sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
9ee6e8bb	169
c988bfad	170	if (is_mpcore) {
c2de81e2	171	dev = qdev_create(NULL, is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
c988bfad PB	172	qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
c988bfad PB	173	qdev_init_nofail(dev);
1356b98d	174	busdev = SYS_BUS_DEVICE(dev);
96eacf64	175	sysbus_mmio_map(busdev, 0, periphbase);
c988bfad PB	176	for (n = 0; n < smp_cpus; n++) {
	177	sysbus_connect_irq(busdev, n, cpu_irq[n]);
	178	}
96eacf64 PM	179	sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL);
	180	/* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */
	181	realview_binfo.gic_cpu_if_addr = periphbase + 0x100;
9ee6e8bb	182	} else {
0ef849d7 PB	183	uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
0ef849d7 PB	184	/* For now just create the nIRQ GIC, and ignore the others. */
c2de81e2	185	dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]);
fe7e8758 PB	186	}
fe7e8758 PB	187	for (n = 0; n < 64; n++) {
067a3ddc	188	pic[n] = qdev_get_gpio_in(dev, n);
9ee6e8bb PB	189	}
9ee6e8bb PB	190
03a0e944 PM	191	pl041 = qdev_create(NULL, "pl041");
	192	qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
	193	qdev_init_nofail(pl041);
1356b98d AF	194	sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
1356b98d AF	195	sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]);
03a0e944	196
86394e96 PB	197	sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
86394e96 PB	198	sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
e69954b9	199
9bca0edb PM	200	pl011_create(0x10009000, pic[12], serial_hd(0));
	201	pl011_create(0x1000a000, pic[13], serial_hd(1));
	202	pl011_create(0x1000b000, pic[14], serial_hd(2));
	203	pl011_create(0x1000c000, pic[15], serial_hd(3));
e69954b9 PB	204
e69954b9 PB	205	/* DMA controller is optional, apparently. */
112a829f PM	206	dev = qdev_create(NULL, "pl081");
	207	object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",
	208	&error_fatal);
	209	qdev_init_nofail(dev);
	210	busdev = SYS_BUS_DEVICE(dev);
	211	sysbus_mmio_map(busdev, 0, 0x10030000);
	212	sysbus_connect_irq(busdev, 0, pic[24]);
e69954b9	213
6a824ec3 PB	214	sysbus_create_simple("sp804", 0x10011000, pic[4]);
6a824ec3 PB	215	sysbus_create_simple("sp804", 0x10012000, pic[5]);
e69954b9	216
26883c69 PM	217	sysbus_create_simple("pl061", 0x10013000, pic[6]);
	218	sysbus_create_simple("pl061", 0x10014000, pic[7]);
	219	gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);
	220
acb9b722	221	sysbus_create_simple("pl111", 0x10020000, pic[23]);
e69954b9	222
26883c69 PM	223	dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
	224	/* Wire up MMC card detect and read-only signals. These have
	225	* to go to both the PL061 GPIO and the sysctl register.
	226	* Note that the PL181 orders these lines (readonly,inserted)
	227	* and the PL061 has them the other way about. Also the card
	228	* detect line is inverted.
	229	*/
	230	mmc_irq[0] = qemu_irq_split(
	231	qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
	232	qdev_get_gpio_in(gpio2, 1));
	233	mmc_irq[1] = qemu_irq_split(
	234	qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
	235	qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
	236	qdev_connect_gpio_out(dev, 0, mmc_irq[0]);
	237	qdev_connect_gpio_out(dev, 1, mmc_irq[1]);
a1bb27b1	238
a63bdb31	239	sysbus_create_simple("pl031", 0x10017000, pic[10]);
7e1543c2	240
0ef849d7	241	if (!is_pb) {
7d6e771f	242	dev = qdev_create(NULL, "realview_pci");
1356b98d	243	busdev = SYS_BUS_DEVICE(dev);
7d6e771f	244	qdev_init_nofail(dev);
7468d73a	245	sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */
a2bff788 PM	246	sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */
	247	sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */
	248	sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */
89a32d32 PM	249	sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */
	250	sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */
	251	sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */
7d6e771f PM	252	sysbus_connect_irq(busdev, 0, pic[48]);
	253	sysbus_connect_irq(busdev, 1, pic[49]);
	254	sysbus_connect_irq(busdev, 2, pic[50]);
	255	sysbus_connect_irq(busdev, 3, pic[51]);
0ef849d7	256	pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
4bcbe0b6	257	if (machine_usb(machine)) {
afb9a60e	258	pci_create_simple(pci_bus, -1, "pci-ohci");
0ef849d7 PB	259	}
	260	n = drive_get_max_bus(IF_SCSI);
	261	while (n >= 0) {
877eb21d MCA	262	dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a"));
877eb21d MCA	263	lsi53c8xx_handle_legacy_cmdline(dev);
0ef849d7 PB	264	n--;
0ef849d7 PB	265	}
e69954b9 PB	266	}
	267	for(n = 0; n < nb_nics; n++) {
	268	nd = &nd_table[n];
0ae18cee	269
e6b3c8ca PM	270	if (!done_nic && (!nd->model \|\|
e6b3c8ca PM	271	strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
0ef849d7 PB	272	if (is_pb) {
	273	lan9118_init(nd, 0x4e000000, pic[28]);
	274	} else {
	275	smc91c111_init(nd, 0x4e000000, pic[28]);
	276	}
	277	done_nic = 1;
e69954b9	278	} else {
29b358f9 DG	279	if (pci_bus) {
	280	pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
	281	}
e69954b9 PB	282	}
	283	}
	284
d1157ca4	285	dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
a5c82852	286	i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
eee48504 PB	287	i2c_create_slave(i2c, "ds1338", 0x68);
eee48504 PB	288
e69954b9 PB	289	/* Memory map for RealView Emulation Baseboard: */
	290	/* 0x10000000 System registers. */
	291	/* 0x10001000 System controller. */
eee48504	292	/* 0x10002000 Two-Wire Serial Bus. */
e69954b9 PB	293	/* 0x10003000 Reserved. */
	294	/* 0x10004000 AACI. */
	295	/* 0x10005000 MCI. */
	296	/* 0x10006000 KMI0. */
	297	/* 0x10007000 KMI1. */
0ef849d7	298	/* 0x10008000 Character LCD. (EB) */
e69954b9 PB	299	/* 0x10009000 UART0. */
	300	/* 0x1000a000 UART1. */
	301	/* 0x1000b000 UART2. */
	302	/* 0x1000c000 UART3. */
	303	/* 0x1000d000 SSPI. */
	304	/* 0x1000e000 SCI. */
	305	/* 0x1000f000 Reserved. */
	306	/* 0x10010000 Watchdog. */
	307	/* 0x10011000 Timer 0+1. */
	308	/* 0x10012000 Timer 2+3. */
	309	/* 0x10013000 GPIO 0. */
	310	/* 0x10014000 GPIO 1. */
	311	/* 0x10015000 GPIO 2. */
0ef849d7	312	/* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */
7e1543c2	313	/* 0x10017000 RTC. */
e69954b9 PB	314	/* 0x10018000 DMC. */
	315	/* 0x10019000 PCI controller config. */
	316	/* 0x10020000 CLCD. */
	317	/* 0x10030000 DMA Controller. */
0ef849d7 PB	318	/* 0x10040000 GIC1. (EB) */
	319	/* 0x10050000 GIC2. (EB) */
	320	/* 0x10060000 GIC3. (EB) */
	321	/* 0x10070000 GIC4. (EB) */
e69954b9	322	/* 0x10080000 SMC. */
0ef849d7 PB	323	/* 0x1e000000 GIC1. (PB) */
	324	/* 0x1e001000 GIC2. (PB) */
	325	/* 0x1e002000 GIC3. (PB) */
	326	/* 0x1e003000 GIC4. (PB) */
e69954b9 PB	327	/* 0x40000000 NOR flash. */
	328	/* 0x44000000 DoC flash. */
	329	/* 0x48000000 SRAM. */
	330	/* 0x4c000000 Configuration flash. */
	331	/* 0x4e000000 Ethernet. */
	332	/* 0x4f000000 USB. */
	333	/* 0x50000000 PISMO. */
	334	/* 0x54000000 PISMO. */
	335	/* 0x58000000 PISMO. */
	336	/* 0x5c000000 PISMO. */
	337	/* 0x60000000 PCI. */
a2bff788 PM	338	/* 0x60000000 PCI Self Config. */
	339	/* 0x61000000 PCI Config. */
	340	/* 0x62000000 PCI IO. */
	341	/* 0x63000000 PCI mem 0. */
	342	/* 0x64000000 PCI mem 1. */
	343	/* 0x68000000 PCI mem 2. */
e69954b9	344
7ffab4d7 PB	345	/* ??? Hack to map an additional page of ram for the secondary CPU
	346	startup code. I guess this works on real hardware because the
	347	BootROM happens to be in ROM/flash or in memory that isn't clobbered
	348	until after Linux boots the secondary CPUs. */
98a99ce0	349	memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000,
f8ed85ac	350	&error_fatal);
35e87820	351	memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
7ffab4d7	352
f93eb9ff	353	realview_binfo.ram_size = ram_size;
c988bfad	354	realview_binfo.nb_cpus = smp_cpus;
f7c70325	355	realview_binfo.board_id = realview_board_id[board_type];
21a88941	356	realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
2744ece8	357	arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo);
e69954b9 PB	358	}
e69954b9 PB	359
3ef96221	360	static void realview_eb_init(MachineState *machine)
c988bfad	361	{
3ef96221	362	realview_init(machine, BOARD_EB);
c988bfad PB	363	}
c988bfad PB	364
3ef96221	365	static void realview_eb_mpcore_init(MachineState *machine)
c988bfad	366	{
3ef96221	367	realview_init(machine, BOARD_EB_MPCORE);
c988bfad PB	368	}
c988bfad PB	369
3ef96221	370	static void realview_pb_a8_init(MachineState *machine)
0ef849d7	371	{
3ef96221	372	realview_init(machine, BOARD_PB_A8);
0ef849d7 PB	373	}
0ef849d7 PB	374
3ef96221	375	static void realview_pbx_a9_init(MachineState *machine)
f7c70325	376	{
3ef96221	377	realview_init(machine, BOARD_PBX_A9);
f7c70325 PB	378	}
f7c70325 PB	379
8a661aea	380	static void realview_eb_class_init(ObjectClass oc, void data)
e264d29d	381	{
8a661aea AF	382	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	383
e264d29d EH	384	mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)";
	385	mc->init = realview_eb_init;
	386	mc->block_default_type = IF_SCSI;
4672cbd7	387	mc->ignore_memory_transaction_failures = true;
ba1ba5cc	388	mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
e264d29d	389	}
c988bfad	390
8a661aea AF	391	static const TypeInfo realview_eb_type = {
	392	.name = MACHINE_TYPE_NAME("realview-eb"),
	393	.parent = TYPE_MACHINE,
	394	.class_init = realview_eb_class_init,
	395	};
f80f9ec9	396
8a661aea	397	static void realview_eb_mpcore_class_init(ObjectClass oc, void data)
e264d29d	398	{
8a661aea AF	399	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	400
e264d29d EH	401	mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)";
	402	mc->init = realview_eb_mpcore_init;
	403	mc->block_default_type = IF_SCSI;
	404	mc->max_cpus = 4;
4672cbd7	405	mc->ignore_memory_transaction_failures = true;
ba1ba5cc	406	mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore");
e264d29d	407	}
f7c70325	408
8a661aea AF	409	static const TypeInfo realview_eb_mpcore_type = {
	410	.name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
	411	.parent = TYPE_MACHINE,
	412	.class_init = realview_eb_mpcore_class_init,
	413	};
e264d29d	414
8a661aea	415	static void realview_pb_a8_class_init(ObjectClass oc, void data)
e264d29d	416	{
8a661aea AF	417	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	418
e264d29d EH	419	mc->desc = "ARM RealView Platform Baseboard for Cortex-A8";
e264d29d EH	420	mc->init = realview_pb_a8_init;
4672cbd7	421	mc->ignore_memory_transaction_failures = true;
ba1ba5cc	422	mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8");
e264d29d EH	423	}
e264d29d EH	424
8a661aea AF	425	static const TypeInfo realview_pb_a8_type = {
	426	.name = MACHINE_TYPE_NAME("realview-pb-a8"),
	427	.parent = TYPE_MACHINE,
	428	.class_init = realview_pb_a8_class_init,
	429	};
0ef849d7	430
8a661aea	431	static void realview_pbx_a9_class_init(ObjectClass oc, void data)
f80f9ec9	432	{
8a661aea AF	433	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	434
e264d29d EH	435	mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9";
e264d29d EH	436	mc->init = realview_pbx_a9_init;
e264d29d	437	mc->max_cpus = 4;
4672cbd7	438	mc->ignore_memory_transaction_failures = true;
ba1ba5cc	439	mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
f80f9ec9 AL	440	}
f80f9ec9 AL	441
8a661aea AF	442	static const TypeInfo realview_pbx_a9_type = {
	443	.name = MACHINE_TYPE_NAME("realview-pbx-a9"),
	444	.parent = TYPE_MACHINE,
	445	.class_init = realview_pbx_a9_class_init,
	446	};
	447
	448	static void realview_machine_init(void)
	449	{
	450	type_register_static(&realview_eb_type);
	451	type_register_static(&realview_eb_mpcore_type);
	452	type_register_static(&realview_pb_a8_type);
	453	type_register_static(&realview_pbx_a9_type);
	454	}
	455
0e6aac87	456	type_init(realview_machine_init)