[qemu.git] / hw / etraxfs_timer.c

/*
 * QEMU ETRAX Timers
 *
 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "sysbus.h"
#include "sysemu.h"
#include "qemu-timer.h"

#define D(x)

#define RW_TMR0_DIV   0x00
#define R_TMR0_DATA   0x04
#define RW_TMR0_CTRL  0x08
#define RW_TMR1_DIV   0x10
#define R_TMR1_DATA   0x14
#define RW_TMR1_CTRL  0x18
#define R_TIME        0x38
#define RW_WD_CTRL    0x40
#define R_WD_STAT     0x44
#define RW_INTR_MASK  0x48
#define RW_ACK_INTR   0x4c
#define R_INTR        0x50
#define R_MASKED_INTR 0x54

struct etrax_timer {
    SysBusDevice busdev;
    qemu_irq irq;
    qemu_irq nmi;

    QEMUBH *bh_t0;
    QEMUBH *bh_t1;
    QEMUBH *bh_wd;
    ptimer_state *ptimer_t0;
    ptimer_state *ptimer_t1;
    ptimer_state *ptimer_wd;

    int wd_hits;

    /* Control registers.  */
    uint32_t rw_tmr0_div;
    uint32_t r_tmr0_data;
    uint32_t rw_tmr0_ctrl;

    uint32_t rw_tmr1_div;
    uint32_t r_tmr1_data;
    uint32_t rw_tmr1_ctrl;

    uint32_t rw_wd_ctrl;

    uint32_t rw_intr_mask;
    uint32_t rw_ack_intr;
    uint32_t r_intr;
    uint32_t r_masked_intr;
};

static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
{
    struct etrax_timer *t = opaque;
    uint32_t r = 0;

    switch (addr) {
    case R_TMR0_DATA:
        r = ptimer_get_count(t->ptimer_t0);
        break;
    case R_TMR1_DATA:
        r = ptimer_get_count(t->ptimer_t1);
        break;
    case R_TIME:
        r = qemu_get_clock_ns(vm_clock) / 10;
        break;
    case RW_INTR_MASK:
        r = t->rw_intr_mask;
        break;
    case R_MASKED_INTR:
        r = t->r_intr & t->rw_intr_mask;
        break;
    default:
        D(printf ("%s %x\n", __func__, addr));
        break;
    }
    return r;
}

static void update_ctrl(struct etrax_timer *t, int tnum)
{
    unsigned int op;
    unsigned int freq;
    unsigned int freq_hz;
    unsigned int div;
    uint32_t ctrl;

    ptimer_state *timer;

    if (tnum == 0) {
        ctrl = t->rw_tmr0_ctrl;
        div = t->rw_tmr0_div;
        timer = t->ptimer_t0;
    } else {
        ctrl = t->rw_tmr1_ctrl;
        div = t->rw_tmr1_div;
        timer = t->ptimer_t1;
    }


    op = ctrl & 3;
    freq = ctrl >> 2;
    freq_hz = 32000000;

    switch (freq)
    {
    case 0:
    case 1:
        D(printf ("extern or disabled timer clock?\n"));
        break;
    case 4: freq_hz =  29493000; break;
    case 5: freq_hz =  32000000; break;
    case 6: freq_hz =  32768000; break;
    case 7: freq_hz = 100000000; break;
    default:
        abort();
        break;
    }

    D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
    ptimer_set_freq(timer, freq_hz);
    ptimer_set_limit(timer, div, 0);

    switch (op)
    {
        case 0:
            /* Load.  */
            ptimer_set_limit(timer, div, 1);
            break;
        case 1:
            /* Hold.  */
            ptimer_stop(timer);
            break;
        case 2:
            /* Run.  */
            ptimer_run(timer, 0);
            break;
        default:
            abort();
            break;
    }
}

static void timer_update_irq(struct etrax_timer *t)
{
    t->r_intr &= ~(t->rw_ack_intr);
    t->r_masked_intr = t->r_intr & t->rw_intr_mask;

    D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
    qemu_set_irq(t->irq, !!t->r_masked_intr);
}

static void timer0_hit(void *opaque)
{
    struct etrax_timer *t = opaque;
    t->r_intr |= 1;
    timer_update_irq(t);
}

static void timer1_hit(void *opaque)
{
    struct etrax_timer *t = opaque;
    t->r_intr |= 2;
    timer_update_irq(t);
}

static void watchdog_hit(void *opaque)
{
    struct etrax_timer *t = opaque;
    if (t->wd_hits == 0) {
        /* real hw gives a single tick before reseting but we are
           a bit friendlier to compensate for our slower execution.  */
        ptimer_set_count(t->ptimer_wd, 10);
        ptimer_run(t->ptimer_wd, 1);
        qemu_irq_raise(t->nmi);
    }
    else
        qemu_system_reset_request();

    t->wd_hits++;
}

static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
{
    unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
    unsigned int wd_key = t->rw_wd_ctrl >> 9;
    unsigned int wd_cnt = t->rw_wd_ctrl & 511;
    unsigned int new_key = value >> 9 & ((1 << 7) - 1);
    unsigned int new_cmd = (value >> 8) & 1;

    /* If the watchdog is enabled, they written key must match the
       complement of the previous.  */
    wd_key = ~wd_key & ((1 << 7) - 1);

    if (wd_en && wd_key != new_key)
        return;

    D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", 
         wd_en, new_key, wd_key, new_cmd, wd_cnt));

    if (t->wd_hits)
        qemu_irq_lower(t->nmi);

    t->wd_hits = 0;

    ptimer_set_freq(t->ptimer_wd, 760);
    if (wd_cnt == 0)
        wd_cnt = 256;
    ptimer_set_count(t->ptimer_wd, wd_cnt);
    if (new_cmd)
        ptimer_run(t->ptimer_wd, 1);
    else
        ptimer_stop(t->ptimer_wd);

    t->rw_wd_ctrl = value;
}

static void
timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    struct etrax_timer *t = opaque;

    switch (addr)
    {
        case RW_TMR0_DIV:
            t->rw_tmr0_div = value;
            break;
        case RW_TMR0_CTRL:
            D(printf ("RW_TMR0_CTRL=%x\n", value));
            t->rw_tmr0_ctrl = value;
            update_ctrl(t, 0);
            break;
        case RW_TMR1_DIV:
            t->rw_tmr1_div = value;
            break;
        case RW_TMR1_CTRL:
            D(printf ("RW_TMR1_CTRL=%x\n", value));
            t->rw_tmr1_ctrl = value;
            update_ctrl(t, 1);
            break;
        case RW_INTR_MASK:
            D(printf ("RW_INTR_MASK=%x\n", value));
            t->rw_intr_mask = value;
            timer_update_irq(t);
            break;
        case RW_WD_CTRL:
            timer_watchdog_update(t, value);
            break;
        case RW_ACK_INTR:
            t->rw_ack_intr = value;
            timer_update_irq(t);
            t->rw_ack_intr = 0;
            break;
        default:
            printf ("%s " TARGET_FMT_plx " %x\n",
                __func__, addr, value);
            break;
    }
}

static CPUReadMemoryFunc * const timer_read[] = {
    NULL, NULL,
    &timer_readl,
};

static CPUWriteMemoryFunc * const timer_write[] = {
    NULL, NULL,
    &timer_writel,
};

static void etraxfs_timer_reset(void *opaque)
{
    struct etrax_timer *t = opaque;

    ptimer_stop(t->ptimer_t0);
    ptimer_stop(t->ptimer_t1);
    ptimer_stop(t->ptimer_wd);
    t->rw_wd_ctrl = 0;
    t->r_intr = 0;
    t->rw_intr_mask = 0;
    qemu_irq_lower(t->irq);
}

static int etraxfs_timer_init(SysBusDevice *dev)
{
    struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev);
    int timer_regs;

    t->bh_t0 = qemu_bh_new(timer0_hit, t);
    t->bh_t1 = qemu_bh_new(timer1_hit, t);
    t->bh_wd = qemu_bh_new(watchdog_hit, t);
    t->ptimer_t0 = ptimer_init(t->bh_t0);
    t->ptimer_t1 = ptimer_init(t->bh_t1);
    t->ptimer_wd = ptimer_init(t->bh_wd);

    sysbus_init_irq(dev, &t->irq);
    sysbus_init_irq(dev, &t->nmi);

    timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
                                        DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x5c, timer_regs);

    qemu_register_reset(etraxfs_timer_reset, t);
    return 0;
}

static void etraxfs_timer_register(void)
{
    sysbus_register_dev("etraxfs,timer", sizeof (struct etrax_timer),
                        etraxfs_timer_init);
}

device_init(etraxfs_timer_register)
Commit	Line	Data
83fa1010	1	/*
e62b5b13	2	* QEMU ETRAX Timers
83fa1010 TS	3	*
	4	* Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
3b1fd90e	24	#include "sysbus.h"
5439779e	25	#include "sysemu.h"
87ecb68b	26	#include "qemu-timer.h"
83fa1010	27
bbaf29c7 EI	28	#define D(x)
bbaf29c7 EI	29
ca87d03b EI	30	#define RW_TMR0_DIV 0x00
	31	#define R_TMR0_DATA 0x04
	32	#define RW_TMR0_CTRL 0x08
	33	#define RW_TMR1_DIV 0x10
	34	#define R_TMR1_DATA 0x14
	35	#define RW_TMR1_CTRL 0x18
	36	#define R_TIME 0x38
	37	#define RW_WD_CTRL 0x40
5439779e	38	#define R_WD_STAT 0x44
ca87d03b EI	39	#define RW_INTR_MASK 0x48
	40	#define RW_ACK_INTR 0x4c
	41	#define R_INTR 0x50
	42	#define R_MASKED_INTR 0x54
83fa1010	43
3b1fd90e EI	44	struct etrax_timer {
	45	SysBusDevice busdev;
	46	qemu_irq irq;
	47	qemu_irq nmi;
84ceea57 EI	48
	49	QEMUBH *bh_t0;
	50	QEMUBH *bh_t1;
	51	QEMUBH *bh_wd;
	52	ptimer_state *ptimer_t0;
	53	ptimer_state *ptimer_t1;
	54	ptimer_state *ptimer_wd;
84ceea57 EI	55
	56	int wd_hits;
	57
	58	/* Control registers. */
	59	uint32_t rw_tmr0_div;
	60	uint32_t r_tmr0_data;
	61	uint32_t rw_tmr0_ctrl;
	62
	63	uint32_t rw_tmr1_div;
	64	uint32_t r_tmr1_data;
	65	uint32_t rw_tmr1_ctrl;
	66
	67	uint32_t rw_wd_ctrl;
	68
	69	uint32_t rw_intr_mask;
	70	uint32_t rw_ack_intr;
	71	uint32_t r_intr;
	72	uint32_t r_masked_intr;
83fa1010 TS	73	};
83fa1010 TS	74
c227f099	75	static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
83fa1010	76	{
3b1fd90e	77	struct etrax_timer *t = opaque;
84ceea57 EI	78	uint32_t r = 0;
	79
	80	switch (addr) {
	81	case R_TMR0_DATA:
	82	r = ptimer_get_count(t->ptimer_t0);
	83	break;
	84	case R_TMR1_DATA:
	85	r = ptimer_get_count(t->ptimer_t1);
	86	break;
	87	case R_TIME:
74475455	88	r = qemu_get_clock_ns(vm_clock) / 10;
84ceea57 EI	89	break;
	90	case RW_INTR_MASK:
	91	r = t->rw_intr_mask;
	92	break;
	93	case R_MASKED_INTR:
	94	r = t->r_intr & t->rw_intr_mask;
	95	break;
	96	default:
	97	D(printf ("%s %x\n", __func__, addr));
	98	break;
	99	}
	100	return r;
83fa1010 TS	101	}
83fa1010 TS	102
3b1fd90e	103	static void update_ctrl(struct etrax_timer *t, int tnum)
83fa1010	104	{
84ceea57 EI	105	unsigned int op;
	106	unsigned int freq;
	107	unsigned int freq_hz;
	108	unsigned int div;
	109	uint32_t ctrl;
	110
	111	ptimer_state *timer;
	112
	113	if (tnum == 0) {
	114	ctrl = t->rw_tmr0_ctrl;
	115	div = t->rw_tmr0_div;
	116	timer = t->ptimer_t0;
	117	} else {
	118	ctrl = t->rw_tmr1_ctrl;
	119	div = t->rw_tmr1_div;
	120	timer = t->ptimer_t1;
	121	}
	122
	123
	124	op = ctrl & 3;
	125	freq = ctrl >> 2;
	126	freq_hz = 32000000;
	127
	128	switch (freq)
	129	{
	130	case 0:
	131	case 1:
	132	D(printf ("extern or disabled timer clock?\n"));
	133	break;
	134	case 4: freq_hz = 29493000; break;
	135	case 5: freq_hz = 32000000; break;
	136	case 6: freq_hz = 32768000; break;
	137	case 7: freq_hz = 100000000; break;
	138	default:
	139	abort();
	140	break;
	141	}
	142
	143	D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
84ceea57 EI	144	ptimer_set_freq(timer, freq_hz);
	145	ptimer_set_limit(timer, div, 0);
	146
	147	switch (op)
	148	{
	149	case 0:
	150	/* Load. */
	151	ptimer_set_limit(timer, div, 1);
	152	break;
	153	case 1:
	154	/* Hold. */
	155	ptimer_stop(timer);
	156	break;
	157	case 2:
	158	/* Run. */
	159	ptimer_run(timer, 0);
	160	break;
	161	default:
	162	abort();
	163	break;
	164	}
83fa1010 TS	165	}
83fa1010 TS	166
3b1fd90e	167	static void timer_update_irq(struct etrax_timer *t)
83fa1010	168	{
84ceea57 EI	169	t->r_intr &= ~(t->rw_ack_intr);
84ceea57 EI	170	t->r_masked_intr = t->r_intr & t->rw_intr_mask;
60237223	171
84ceea57	172	D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
3b1fd90e	173	qemu_set_irq(t->irq, !!t->r_masked_intr);
83fa1010 TS	174	}
83fa1010 TS	175
5439779e	176	static void timer0_hit(void *opaque)
60237223	177	{
3b1fd90e	178	struct etrax_timer *t = opaque;
84ceea57 EI	179	t->r_intr \|= 1;
84ceea57 EI	180	timer_update_irq(t);
60237223 EI	181	}
60237223 EI	182
5439779e EI	183	static void timer1_hit(void *opaque)
5439779e EI	184	{
3b1fd90e	185	struct etrax_timer *t = opaque;
84ceea57 EI	186	t->r_intr \|= 2;
84ceea57 EI	187	timer_update_irq(t);
5439779e EI	188	}
	189
	190	static void watchdog_hit(void *opaque)
	191	{
3b1fd90e	192	struct etrax_timer *t = opaque;
84ceea57 EI	193	if (t->wd_hits == 0) {
	194	/* real hw gives a single tick before reseting but we are
	195	a bit friendlier to compensate for our slower execution. */
	196	ptimer_set_count(t->ptimer_wd, 10);
	197	ptimer_run(t->ptimer_wd, 1);
3b1fd90e	198	qemu_irq_raise(t->nmi);
84ceea57 EI	199	}
	200	else
	201	qemu_system_reset_request();
	202
	203	t->wd_hits++;
5439779e EI	204	}
5439779e EI	205
3b1fd90e	206	static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
5439779e	207	{
84ceea57 EI	208	unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
	209	unsigned int wd_key = t->rw_wd_ctrl >> 9;
	210	unsigned int wd_cnt = t->rw_wd_ctrl & 511;
	211	unsigned int new_key = value >> 9 & ((1 << 7) - 1);
	212	unsigned int new_cmd = (value >> 8) & 1;
5439779e	213
84ceea57 EI	214	/* If the watchdog is enabled, they written key must match the
	215	complement of the previous. */
	216	wd_key = ~wd_key & ((1 << 7) - 1);
5439779e	217
84ceea57 EI	218	if (wd_en && wd_key != new_key)
84ceea57 EI	219	return;
5439779e	220
84ceea57 EI	221	D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
84ceea57 EI	222	wd_en, new_key, wd_key, new_cmd, wd_cnt));
5439779e	223
84ceea57	224	if (t->wd_hits)
3b1fd90e	225	qemu_irq_lower(t->nmi);
5ef98b47	226
84ceea57	227	t->wd_hits = 0;
5ef98b47	228
84ceea57 EI	229	ptimer_set_freq(t->ptimer_wd, 760);
	230	if (wd_cnt == 0)
	231	wd_cnt = 256;
	232	ptimer_set_count(t->ptimer_wd, wd_cnt);
	233	if (new_cmd)
	234	ptimer_run(t->ptimer_wd, 1);
	235	else
	236	ptimer_stop(t->ptimer_wd);
5439779e	237
84ceea57	238	t->rw_wd_ctrl = value;
5439779e EI	239	}
5439779e EI	240
83fa1010	241	static void
c227f099	242	timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
83fa1010	243	{
3b1fd90e	244	struct etrax_timer *t = opaque;
84ceea57 EI	245
	246	switch (addr)
	247	{
	248	case RW_TMR0_DIV:
	249	t->rw_tmr0_div = value;
	250	break;
	251	case RW_TMR0_CTRL:
	252	D(printf ("RW_TMR0_CTRL=%x\n", value));
	253	t->rw_tmr0_ctrl = value;
	254	update_ctrl(t, 0);
	255	break;
	256	case RW_TMR1_DIV:
	257	t->rw_tmr1_div = value;
	258	break;
	259	case RW_TMR1_CTRL:
	260	D(printf ("RW_TMR1_CTRL=%x\n", value));
	261	t->rw_tmr1_ctrl = value;
	262	update_ctrl(t, 1);
	263	break;
	264	case RW_INTR_MASK:
	265	D(printf ("RW_INTR_MASK=%x\n", value));
	266	t->rw_intr_mask = value;
	267	timer_update_irq(t);
	268	break;
	269	case RW_WD_CTRL:
	270	timer_watchdog_update(t, value);
	271	break;
	272	case RW_ACK_INTR:
	273	t->rw_ack_intr = value;
	274	timer_update_irq(t);
	275	t->rw_ack_intr = 0;
	276	break;
	277	default:
	278	printf ("%s " TARGET_FMT_plx " %x\n",
	279	__func__, addr, value);
	280	break;
	281	}
83fa1010 TS	282	}
83fa1010 TS	283
d60efc6b	284	static CPUReadMemoryFunc * const timer_read[] = {
84ceea57 EI	285	NULL, NULL,
84ceea57 EI	286	&timer_readl,
83fa1010 TS	287	};
83fa1010 TS	288
d60efc6b	289	static CPUWriteMemoryFunc * const timer_write[] = {
84ceea57 EI	290	NULL, NULL,
84ceea57 EI	291	&timer_writel,
83fa1010 TS	292	};
83fa1010 TS	293
5439779e EI	294	static void etraxfs_timer_reset(void *opaque)
5439779e EI	295	{
3b1fd90e	296	struct etrax_timer *t = opaque;
84ceea57 EI	297
	298	ptimer_stop(t->ptimer_t0);
	299	ptimer_stop(t->ptimer_t1);
	300	ptimer_stop(t->ptimer_wd);
	301	t->rw_wd_ctrl = 0;
	302	t->r_intr = 0;
	303	t->rw_intr_mask = 0;
3b1fd90e	304	qemu_irq_lower(t->irq);
5439779e EI	305	}
5439779e EI	306
81a322d4	307	static int etraxfs_timer_init(SysBusDevice *dev)
83fa1010	308	{
3b1fd90e	309	struct etrax_timer t = FROM_SYSBUS(typeof (t), dev);
84ceea57	310	int timer_regs;
83fa1010	311
84ceea57 EI	312	t->bh_t0 = qemu_bh_new(timer0_hit, t);
	313	t->bh_t1 = qemu_bh_new(timer1_hit, t);
	314	t->bh_wd = qemu_bh_new(watchdog_hit, t);
	315	t->ptimer_t0 = ptimer_init(t->bh_t0);
	316	t->ptimer_t1 = ptimer_init(t->bh_t1);
	317	t->ptimer_wd = ptimer_init(t->bh_wd);
3b1fd90e EI	318
	319	sysbus_init_irq(dev, &t->irq);
	320	sysbus_init_irq(dev, &t->nmi);
83fa1010	321
2507c12a AG	322	timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
2507c12a AG	323	DEVICE_NATIVE_ENDIAN);
3b1fd90e	324	sysbus_init_mmio(dev, 0x5c, timer_regs);
5439779e	325
a08d4367	326	qemu_register_reset(etraxfs_timer_reset, t);
81a322d4	327	return 0;
83fa1010	328	}
3b1fd90e EI	329
	330	static void etraxfs_timer_register(void)
	331	{
	332	sysbus_register_dev("etraxfs,timer", sizeof (struct etrax_timer),
	333	etraxfs_timer_init);
	334	}
	335
	336	device_init(etraxfs_timer_register)