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Commit | Line | Data |
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94e1a912 GH |
1 | #define PCNET_IOPORT_SIZE 0x20 |
2 | #define PCNET_PNPMMIO_SIZE 0x20 | |
3 | ||
4 | #define PCNET_LOOPTEST_CRC 1 | |
5 | #define PCNET_LOOPTEST_NOCRC 2 | |
6 | ||
bd8d6f7c | 7 | #include "memory.h" |
94e1a912 GH |
8 | |
9 | typedef struct PCNetState_st PCNetState; | |
10 | ||
11 | struct PCNetState_st { | |
1fa51482 | 12 | NICState *nic; |
94e1a912 GH |
13 | NICConf conf; |
14 | QEMUTimer *poll_timer; | |
15 | int rap, isr, lnkst; | |
16 | uint32_t rdra, tdra; | |
17 | uint8_t prom[16]; | |
18 | uint16_t csr[128]; | |
19 | uint16_t bcr[32]; | |
fe87aa83 | 20 | int xmit_pos; |
94e1a912 | 21 | uint64_t timer; |
bd8d6f7c | 22 | MemoryRegion mmio; |
94e1a912 | 23 | uint8_t buffer[4096]; |
94e1a912 GH |
24 | qemu_irq irq; |
25 | void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr, | |
26 | uint8_t *buf, int len, int do_bswap); | |
27 | void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr, | |
28 | uint8_t *buf, int len, int do_bswap); | |
29 | void *dma_opaque; | |
fe87aa83 | 30 | int tx_busy; |
94e1a912 GH |
31 | int looptest; |
32 | }; | |
33 | ||
34 | void pcnet_h_reset(void *opaque); | |
35 | void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val); | |
36 | uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr); | |
a4c75a21 PB |
37 | void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val); |
38 | uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr); | |
39 | uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap); | |
1fa51482 MM |
40 | int pcnet_can_receive(VLANClientState *nc); |
41 | ssize_t pcnet_receive(VLANClientState *nc, const uint8_t *buf, size_t size_); | |
94e1a912 | 42 | void pcnet_common_cleanup(PCNetState *d); |
1fa51482 | 43 | int pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info); |
3d865059 | 44 | extern const VMStateDescription vmstate_pcnet; |