[qemu.git] / hw / mipsnet.c

#include "hw.h"
#include "mips.h"
#include "net.h"
#include "isa.h"

//#define DEBUG_MIPSNET_SEND
//#define DEBUG_MIPSNET_RECEIVE
//#define DEBUG_MIPSNET_DATA
//#define DEBUG_MIPSNET_IRQ

/* MIPSnet register offsets */

#define MIPSNET_DEV_ID		0x00
#define MIPSNET_BUSY		0x08
#define MIPSNET_RX_DATA_COUNT	0x0c
#define MIPSNET_TX_DATA_COUNT	0x10
#define MIPSNET_INT_CTL		0x14
# define MIPSNET_INTCTL_TXDONE		0x00000001
# define MIPSNET_INTCTL_RXDONE		0x00000002
# define MIPSNET_INTCTL_TESTBIT		0x80000000
#define MIPSNET_INTERRUPT_INFO	0x18
#define MIPSNET_RX_DATA_BUFFER	0x1c
#define MIPSNET_TX_DATA_BUFFER	0x20

#define MAX_ETH_FRAME_SIZE	1514

typedef struct MIPSnetState {
    uint32_t busy;
    uint32_t rx_count;
    uint32_t rx_read;
    uint32_t tx_count;
    uint32_t tx_written;
    uint32_t intctl;
    uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
    uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
    int io_base;
    qemu_irq irq;
    VLANClientState *vc;
} MIPSnetState;

static void mipsnet_reset(MIPSnetState *s)
{
    s->busy = 1;
    s->rx_count = 0;
    s->rx_read = 0;
    s->tx_count = 0;
    s->tx_written = 0;
    s->intctl = 0;
    memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
    memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
}

static void mipsnet_update_irq(MIPSnetState *s)
{
    int isr = !!s->intctl;
#ifdef DEBUG_MIPSNET_IRQ
    printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
#endif
    qemu_set_irq(s->irq, isr);
}

static int mipsnet_buffer_full(MIPSnetState *s)
{
    if (s->rx_count >= MAX_ETH_FRAME_SIZE)
        return 1;
    return 0;
}

static int mipsnet_can_receive(VLANClientState *vc)
{
    MIPSnetState *s = vc->opaque;

    if (s->busy)
        return 0;
    return !mipsnet_buffer_full(s);
}

static ssize_t mipsnet_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
{
    MIPSnetState *s = vc->opaque;

#ifdef DEBUG_MIPSNET_RECEIVE
    printf("mipsnet: receiving len=%d\n", size);
#endif
    if (!mipsnet_can_receive(vc))
        return -1;

    s->busy = 1;

    /* Just accept everything. */

    /* Write packet data. */
    memcpy(s->rx_buffer, buf, size);

    s->rx_count = size;
    s->rx_read = 0;

    /* Now we can signal we have received something. */
    s->intctl |= MIPSNET_INTCTL_RXDONE;
    mipsnet_update_irq(s);

    return size;
}

static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr)
{
    MIPSnetState *s = opaque;
    int ret = 0;

    addr &= 0x3f;
    switch (addr) {
    case MIPSNET_DEV_ID:
	ret = be32_to_cpu(0x4d495053);		/* MIPS */
        break;
    case MIPSNET_DEV_ID + 4:
	ret = be32_to_cpu(0x4e455430);		/* NET0 */
        break;
    case MIPSNET_BUSY:
	ret = s->busy;
        break;
    case MIPSNET_RX_DATA_COUNT:
	ret = s->rx_count;
        break;
    case MIPSNET_TX_DATA_COUNT:
	ret = s->tx_count;
        break;
    case MIPSNET_INT_CTL:
	ret = s->intctl;
        s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
        break;
    case MIPSNET_INTERRUPT_INFO:
        /* XXX: This seems to be a per-VPE interrupt number. */
	ret = 0;
        break;
    case MIPSNET_RX_DATA_BUFFER:
        if (s->rx_count) {
            s->rx_count--;
            ret = s->rx_buffer[s->rx_read++];
        }
        break;
    /* Reads as zero. */
    case MIPSNET_TX_DATA_BUFFER:
    default:
        break;
    }
#ifdef DEBUG_MIPSNET_DATA
    printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
    return ret;
}

static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    MIPSnetState *s = opaque;

    addr &= 0x3f;
#ifdef DEBUG_MIPSNET_DATA
    printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
    switch (addr) {
    case MIPSNET_TX_DATA_COUNT:
	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
        s->tx_written = 0;
        break;
    case MIPSNET_INT_CTL:
        if (val & MIPSNET_INTCTL_TXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_TXDONE;
        } else if (val & MIPSNET_INTCTL_RXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_RXDONE;
        } else if (val & MIPSNET_INTCTL_TESTBIT) {
            mipsnet_reset(s);
            s->intctl |= MIPSNET_INTCTL_TESTBIT;
        } else if (!val) {
            /* ACK testbit interrupt, flag was cleared on read. */
        }
        s->busy = !!s->intctl;
        mipsnet_update_irq(s);
        break;
    case MIPSNET_TX_DATA_BUFFER:
        s->tx_buffer[s->tx_written++] = val;
        if (s->tx_written == s->tx_count) {
            /* Send buffer. */
#ifdef DEBUG_MIPSNET_SEND
            printf("mipsnet: sending len=%d\n", s->tx_count);
#endif
            qemu_send_packet(s->vc, s->tx_buffer, s->tx_count);
            s->tx_count = s->tx_written = 0;
            s->intctl |= MIPSNET_INTCTL_TXDONE;
            s->busy = 1;
            mipsnet_update_irq(s);
        }
        break;
    /* Read-only registers */
    case MIPSNET_DEV_ID:
    case MIPSNET_BUSY:
    case MIPSNET_RX_DATA_COUNT:
    case MIPSNET_INTERRUPT_INFO:
    case MIPSNET_RX_DATA_BUFFER:
    default:
        break;
    }
}

static void mipsnet_save(QEMUFile *f, void *opaque)
{
    MIPSnetState *s = opaque;

    qemu_put_be32s(f, &s->busy);
    qemu_put_be32s(f, &s->rx_count);
    qemu_put_be32s(f, &s->rx_read);
    qemu_put_be32s(f, &s->tx_count);
    qemu_put_be32s(f, &s->tx_written);
    qemu_put_be32s(f, &s->intctl);
    qemu_put_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
    qemu_put_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
}

static int mipsnet_load(QEMUFile *f, void *opaque, int version_id)
{
    MIPSnetState *s = opaque;

    if (version_id > 0)
        return -EINVAL;

    qemu_get_be32s(f, &s->busy);
    qemu_get_be32s(f, &s->rx_count);
    qemu_get_be32s(f, &s->rx_read);
    qemu_get_be32s(f, &s->tx_count);
    qemu_get_be32s(f, &s->tx_written);
    qemu_get_be32s(f, &s->intctl);
    qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
    qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);

    return 0;
}

static void mipsnet_cleanup(VLANClientState *vc)
{
    MIPSnetState *s = vc->opaque;

    unregister_savevm("mipsnet", s);

    isa_unassign_ioport(s->io_base, 36);

    qemu_free(s);
}

void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
{
    MIPSnetState *s;

    qemu_check_nic_model(nd, "mipsnet");

    s = qemu_mallocz(sizeof(MIPSnetState));

    register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
    register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
    register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
    register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
    register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
    register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);

    s->io_base = base;
    s->irq = irq;
    if (nd && nd->vlan) {
        s->vc = nd->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
                                              mipsnet_can_receive, mipsnet_receive,
                                              NULL, mipsnet_cleanup, s);
    } else {
        s->vc = NULL;
    }

    qemu_format_nic_info_str(s->vc, nd->macaddr);

    mipsnet_reset(s);
    register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
}
Commit	Line	Data
87ecb68b PB	1	#include "hw.h"
	2	#include "mips.h"
	3	#include "net.h"
	4	#include "isa.h"
f0fc6f8f	5
57ba97de TS	6	//#define DEBUG_MIPSNET_SEND
57ba97de TS	7	//#define DEBUG_MIPSNET_RECEIVE
f0fc6f8f	8	//#define DEBUG_MIPSNET_DATA
57ba97de	9	//#define DEBUG_MIPSNET_IRQ
f0fc6f8f TS	10
	11	/* MIPSnet register offsets */
	12
	13	#define MIPSNET_DEV_ID 0x00
f0fc6f8f TS	14	#define MIPSNET_BUSY 0x08
	15	#define MIPSNET_RX_DATA_COUNT 0x0c
	16	#define MIPSNET_TX_DATA_COUNT 0x10
	17	#define MIPSNET_INT_CTL 0x14
	18	# define MIPSNET_INTCTL_TXDONE 0x00000001
	19	# define MIPSNET_INTCTL_RXDONE 0x00000002
	20	# define MIPSNET_INTCTL_TESTBIT 0x80000000
	21	#define MIPSNET_INTERRUPT_INFO 0x18
	22	#define MIPSNET_RX_DATA_BUFFER 0x1c
	23	#define MIPSNET_TX_DATA_BUFFER 0x20
	24
	25	#define MAX_ETH_FRAME_SIZE 1514
	26
	27	typedef struct MIPSnetState {
	28	uint32_t busy;
	29	uint32_t rx_count;
	30	uint32_t rx_read;
	31	uint32_t tx_count;
	32	uint32_t tx_written;
	33	uint32_t intctl;
	34	uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
	35	uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
b946a153	36	int io_base;
f0fc6f8f TS	37	qemu_irq irq;
f0fc6f8f TS	38	VLANClientState *vc;
f0fc6f8f TS	39	} MIPSnetState;
	40
	41	static void mipsnet_reset(MIPSnetState *s)
	42	{
	43	s->busy = 1;
	44	s->rx_count = 0;
	45	s->rx_read = 0;
	46	s->tx_count = 0;
	47	s->tx_written = 0;
	48	s->intctl = 0;
	49	memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
	50	memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
	51	}
	52
	53	static void mipsnet_update_irq(MIPSnetState *s)
	54	{
	55	int isr = !!s->intctl;
	56	#ifdef DEBUG_MIPSNET_IRQ
	57	printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
	58	#endif
	59	qemu_set_irq(s->irq, isr);
	60	}
	61
	62	static int mipsnet_buffer_full(MIPSnetState *s)
	63	{
	64	if (s->rx_count >= MAX_ETH_FRAME_SIZE)
	65	return 1;
	66	return 0;
	67	}
	68
e3f5ec2b	69	static int mipsnet_can_receive(VLANClientState *vc)
f0fc6f8f	70	{
e3f5ec2b	71	MIPSnetState *s = vc->opaque;
f0fc6f8f TS	72
	73	if (s->busy)
	74	return 0;
	75	return !mipsnet_buffer_full(s);
	76	}
	77
4f1c942b	78	static ssize_t mipsnet_receive(VLANClientState vc, const uint8_t buf, size_t size)
f0fc6f8f	79	{
e3f5ec2b	80	MIPSnetState *s = vc->opaque;
f0fc6f8f TS	81
	82	#ifdef DEBUG_MIPSNET_RECEIVE
	83	printf("mipsnet: receiving len=%d\n", size);
	84	#endif
e3f5ec2b	85	if (!mipsnet_can_receive(vc))
4f1c942b	86	return -1;
f0fc6f8f TS	87
	88	s->busy = 1;
	89
	90	/* Just accept everything. */
	91
	92	/* Write packet data. */
	93	memcpy(s->rx_buffer, buf, size);
	94
	95	s->rx_count = size;
	96	s->rx_read = 0;
	97
	98	/* Now we can signal we have received something. */
	99	s->intctl \|= MIPSNET_INTCTL_RXDONE;
	100	mipsnet_update_irq(s);
4f1c942b MM	101
4f1c942b MM	102	return size;
f0fc6f8f TS	103	}
	104
	105	static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr)
	106	{
	107	MIPSnetState *s = opaque;
	108	int ret = 0;
f0fc6f8f TS	109
	110	addr &= 0x3f;
	111	switch (addr) {
	112	case MIPSNET_DEV_ID:
9b595395	113	ret = be32_to_cpu(0x4d495053); /* MIPS */
f0fc6f8f TS	114	break;
f0fc6f8f TS	115	case MIPSNET_DEV_ID + 4:
9b595395	116	ret = be32_to_cpu(0x4e455430); /* NET0 */
f0fc6f8f TS	117	break;
	118	case MIPSNET_BUSY:
	119	ret = s->busy;
	120	break;
	121	case MIPSNET_RX_DATA_COUNT:
	122	ret = s->rx_count;
	123	break;
	124	case MIPSNET_TX_DATA_COUNT:
	125	ret = s->tx_count;
	126	break;
	127	case MIPSNET_INT_CTL:
	128	ret = s->intctl;
	129	s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
	130	break;
	131	case MIPSNET_INTERRUPT_INFO:
	132	/* XXX: This seems to be a per-VPE interrupt number. */
	133	ret = 0;
	134	break;
	135	case MIPSNET_RX_DATA_BUFFER:
	136	if (s->rx_count) {
	137	s->rx_count--;
	138	ret = s->rx_buffer[s->rx_read++];
	139	}
	140	break;
	141	/* Reads as zero. */
	142	case MIPSNET_TX_DATA_BUFFER:
	143	default:
	144	break;
	145	}
	146	#ifdef DEBUG_MIPSNET_DATA
	147	printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
	148	#endif
	149	return ret;
	150	}
	151
	152	static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val)
	153	{
	154	MIPSnetState *s = opaque;
	155
	156	addr &= 0x3f;
	157	#ifdef DEBUG_MIPSNET_DATA
	158	printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
	159	#endif
	160	switch (addr) {
	161	case MIPSNET_TX_DATA_COUNT:
	162	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
	163	s->tx_written = 0;
	164	break;
	165	case MIPSNET_INT_CTL:
	166	if (val & MIPSNET_INTCTL_TXDONE) {
	167	s->intctl &= ~MIPSNET_INTCTL_TXDONE;
	168	} else if (val & MIPSNET_INTCTL_RXDONE) {
	169	s->intctl &= ~MIPSNET_INTCTL_RXDONE;
	170	} else if (val & MIPSNET_INTCTL_TESTBIT) {
	171	mipsnet_reset(s);
	172	s->intctl \|= MIPSNET_INTCTL_TESTBIT;
	173	} else if (!val) {
	174	/* ACK testbit interrupt, flag was cleared on read. */
	175	}
	176	s->busy = !!s->intctl;
	177	mipsnet_update_irq(s);
	178	break;
	179	case MIPSNET_TX_DATA_BUFFER:
	180	s->tx_buffer[s->tx_written++] = val;
181	if (s->tx_written == s->tx_count) {
182	/* Send buffer. */
183	#ifdef DEBUG_MIPSNET_SEND
184	printf("mipsnet: sending len=%d\n", s->tx_count);
185	#endif
186	qemu_send_packet(s->vc, s->tx_buffer, s->tx_count);
187	s->tx_count = s->tx_written = 0;
188	s->intctl \|= MIPSNET_INTCTL_TXDONE;
189	s->busy = 1;
190	mipsnet_update_irq(s);
191	}
192	break;
193	/* Read-only registers */
194	case MIPSNET_DEV_ID:
195	case MIPSNET_BUSY:
196	case MIPSNET_RX_DATA_COUNT:
197	case MIPSNET_INTERRUPT_INFO:
198	case MIPSNET_RX_DATA_BUFFER:
199	default:
200	break;
201	}
202	}
203
204	static void mipsnet_save(QEMUFile f, void opaque)
205	{
206	MIPSnetState *s = opaque;
207
208	qemu_put_be32s(f, &s->busy);
209	qemu_put_be32s(f, &s->rx_count);
210	qemu_put_be32s(f, &s->rx_read);
211	qemu_put_be32s(f, &s->tx_count);
212	qemu_put_be32s(f, &s->tx_written);
213	qemu_put_be32s(f, &s->intctl);
214	qemu_put_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
215	qemu_put_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
216	}
217
218	static int mipsnet_load(QEMUFile f, void opaque, int version_id)
219	{
220	MIPSnetState *s = opaque;
221
222	if (version_id > 0)
223	return -EINVAL;
224
225	qemu_get_be32s(f, &s->busy);
226	qemu_get_be32s(f, &s->rx_count);
227	qemu_get_be32s(f, &s->rx_read);
228	qemu_get_be32s(f, &s->tx_count);
229	qemu_get_be32s(f, &s->tx_written);
230	qemu_get_be32s(f, &s->intctl);
231	qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
232	qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
233
234	return 0;
235	}
236
b946a153 AL	237	static void mipsnet_cleanup(VLANClientState *vc)
	238	{
	239	MIPSnetState *s = vc->opaque;
	240
	241	unregister_savevm("mipsnet", s);
	242
	243	isa_unassign_ioport(s->io_base, 36);
	244
	245	qemu_free(s);
	246	}
	247
f0fc6f8f TS	248	void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
	249	{
	250	MIPSnetState *s;
	251
0ae18cee AL	252	qemu_check_nic_model(nd, "mipsnet");
0ae18cee AL	253
f0fc6f8f	254	s = qemu_mallocz(sizeof(MIPSnetState));
f0fc6f8f TS	255
	256	register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
	257	register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
	258	register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
	259	register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
	260	register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
	261	register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
	262
b946a153	263	s->io_base = base;
f0fc6f8f	264	s->irq = irq;
f0fc6f8f	265	if (nd && nd->vlan) {
ae50b274 MM	266	s->vc = nd->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
	267	mipsnet_can_receive, mipsnet_receive,
	268	NULL, mipsnet_cleanup, s);
f0fc6f8f TS	269	} else {
	270	s->vc = NULL;
	271	}
	272
ad067148	273	qemu_format_nic_info_str(s->vc, nd->macaddr);
f0fc6f8f TS	274
	275	mipsnet_reset(s);
	276	register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
	277	}