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pci: rename pci_register_bar_region() to pci_register_bar()
[qemu.git] / hw / e1000.c
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7c23b892
AZ		 1/*
2 * QEMU e1000 emulation
3 *
2758aa52
MT		 4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7c23b892
AZ		 7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
8167ee88 24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7c23b892
AZ		 25 */
26
27
28#include "hw.h"
29#include "pci.h"
30#include "net.h"
7200ac3c 31#include "net/checksum.h"
fbdaa002 32#include "loader.h"
1ca4d09a 33#include "sysemu.h"
7c23b892 34
7c23b892
AZ		 35#include "e1000_hw.h"
36
27124888 37#define E1000_DEBUG
7c23b892 38
27124888 39#ifdef E1000_DEBUG
7c23b892
AZ		 40enum {
41 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
42 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
43 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
44 DEBUG_RXFILTER, DEBUG_NOTYET,
45};
46#define DBGBIT(x) (1<<DEBUG_##x)
47static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
48
6c7f4b47 49#define DBGOUT(what, fmt, ...) do { \
7c23b892 50 if (debugflags & DBGBIT(what)) \
6c7f4b47 51 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
7c23b892
AZ		 52 } while (0)
53#else
6c7f4b47 54#define DBGOUT(what, fmt, ...) do {} while (0)
7c23b892
AZ		 55#endif
56
57#define IOPORT_SIZE 0x40
e94bbefe 58#define PNPMMIO_SIZE 0x20000
78aeb23e 59#define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
7c23b892
AZ		 60
61/*
62 * HW models:
63 * E1000_DEV_ID_82540EM works with Windows and Linux
64 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
65 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
66 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
67 * Others never tested
68 */
69enum { E1000_DEVID = E1000_DEV_ID_82540EM };
70
71/*
72 * May need to specify additional MAC-to-PHY entries --
73 * Intel's Windows driver refuses to initialize unless they match
74 */
75enum {
76 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
77 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
78 /* default to E1000_DEV_ID_82540EM */ 0xc20
79};
80
81typedef struct E1000State_st {
82 PCIDevice dev;
a03e2aec 83 NICState *nic;
fbdaa002 84 NICConf conf;
ad00a9b9
AK		 85 MemoryRegion mmio;
86 MemoryRegion io;
7c23b892
AZ		 87
88 uint32_t mac_reg[0x8000];
89 uint16_t phy_reg[0x20];
90 uint16_t eeprom_data[64];
91
92 uint32_t rxbuf_size;
93 uint32_t rxbuf_min_shift;
94 int check_rxov;
95 struct e1000_tx {
96 unsigned char header[256];
8f2e8d1f 97 unsigned char vlan_header[4];
b10fec9b 98 /* Fields vlan and data must not be reordered or separated. */
8f2e8d1f 99 unsigned char vlan[4];
7c23b892
AZ		 100 unsigned char data[0x10000];
101 uint16_t size;
102 unsigned char sum_needed;
8f2e8d1f 103 unsigned char vlan_needed;
7c23b892
AZ		 104 uint8_t ipcss;
105 uint8_t ipcso;
106 uint16_t ipcse;
107 uint8_t tucss;
108 uint8_t tucso;
109 uint16_t tucse;
110 uint8_t hdr_len;
111 uint16_t mss;
112 uint32_t paylen;
113 uint16_t tso_frames;
114 char tse;
b6c4f71f
BS		 115 int8_t ip;
116 int8_t tcp;
1b0009db 117 char cptse; // current packet tse bit
7c23b892
AZ		 118 } tx;
119
120 struct {
121 uint32_t val_in; // shifted in from guest driver
122 uint16_t bitnum_in;
123 uint16_t bitnum_out;
124 uint16_t reading;
125 uint32_t old_eecd;
126 } eecd_state;
127} E1000State;
128
129#define defreg(x) x = (E1000_##x>>2)
130enum {
131 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
132 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
133 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
134 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
135 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
136 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
137 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
138 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
139 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
8f2e8d1f
AL		 140 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
141 defreg(VET),
7c23b892
AZ		 142};
143
144enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
88b4e9db 145static const char phy_regcap[0x20] = {
7c23b892
AZ		 146 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
147 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
148 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
149 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
150 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
700f6e2c 151 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
7c23b892
AZ		 152};
153
7c23b892
AZ		 154static void
155set_interrupt_cause(E1000State *s, int index, uint32_t val)
156{
157 if (val)
158 val |= E1000_ICR_INT_ASSERTED;
159 s->mac_reg[ICR] = val;
b1332393 160 s->mac_reg[ICS] = val;
bc26e55a 161 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
7c23b892
AZ		 162}
163
164static void
165set_ics(E1000State *s, int index, uint32_t val)
166{
167 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
168 s->mac_reg[IMS]);
169 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
170}
171
172static int
173rxbufsize(uint32_t v)
174{
175 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
176 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
177 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
178 switch (v) {
179 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
180 return 16384;
181 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
182 return 8192;
183 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
184 return 4096;
185 case E1000_RCTL_SZ_1024:
186 return 1024;
187 case E1000_RCTL_SZ_512:
188 return 512;
189 case E1000_RCTL_SZ_256:
190 return 256;
191 }
192 return 2048;
193}
194
cab3c825
KW		 195static void
196set_ctrl(E1000State *s, int index, uint32_t val)
197{
198 /* RST is self clearing */
199 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
200}
201
7c23b892
AZ		 202static void
203set_rx_control(E1000State *s, int index, uint32_t val)
204{
205 s->mac_reg[RCTL] = val;
206 s->rxbuf_size = rxbufsize(val);
207 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
208 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
209 s->mac_reg[RCTL]);
210}
211
212static void
213set_mdic(E1000State *s, int index, uint32_t val)
214{
215 uint32_t data = val & E1000_MDIC_DATA_MASK;
216 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
217
218 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
219 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
220 else if (val & E1000_MDIC_OP_READ) {
221 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
222 if (!(phy_regcap[addr] & PHY_R)) {
223 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
224 val |= E1000_MDIC_ERROR;
225 } else
226 val = (val ^ data) | s->phy_reg[addr];
227 } else if (val & E1000_MDIC_OP_WRITE) {
228 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
229 if (!(phy_regcap[addr] & PHY_W)) {
230 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
231 val |= E1000_MDIC_ERROR;
232 } else
233 s->phy_reg[addr] = data;
234 }
235 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
236 set_ics(s, 0, E1000_ICR_MDAC);
237}
238
239static uint32_t
240get_eecd(E1000State *s, int index)
241{
242 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
243
244 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
245 s->eecd_state.bitnum_out, s->eecd_state.reading);
246 if (!s->eecd_state.reading ||
247 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
248 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
249 ret |= E1000_EECD_DO;
250 return ret;
251}
252
253static void
254set_eecd(E1000State *s, int index, uint32_t val)
255{
256 uint32_t oldval = s->eecd_state.old_eecd;
257
258 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
259 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
9651ac55
IT		 260 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
261 return;
262 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
263 s->eecd_state.val_in = 0;
264 s->eecd_state.bitnum_in = 0;
265 s->eecd_state.bitnum_out = 0;
266 s->eecd_state.reading = 0;
267 }
7c23b892
AZ		 268 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
269 return;
270 if (!(E1000_EECD_SK & val)) { // falling edge
271 s->eecd_state.bitnum_out++;
272 return;
273 }
7c23b892
AZ		 274 s->eecd_state.val_in <<= 1;
275 if (val & E1000_EECD_DI)
276 s->eecd_state.val_in |= 1;
277 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
278 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
279 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
280 EEPROM_READ_OPCODE_MICROWIRE);
281 }
282 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
283 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
284 s->eecd_state.reading);
285}
286
287static uint32_t
288flash_eerd_read(E1000State *s, int x)
289{
290 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
291
b1332393
BP		 292 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
293 return (s->mac_reg[EERD]);
294
7c23b892 295 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
b1332393
BP		 296 return (E1000_EEPROM_RW_REG_DONE | r);
297
298 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
299 E1000_EEPROM_RW_REG_DONE | r);
7c23b892
AZ		 300}
301
7c23b892
AZ		 302static void
303putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
304{
c6a6a5e3
AL		 305 uint32_t sum;
306
7c23b892
AZ		 307 if (cse && cse < n)
308 n = cse + 1;
c6a6a5e3
AL		 309 if (sloc < n-1) {
310 sum = net_checksum_add(n-css, data+css);
7c23b892 311 cpu_to_be16wu((uint16_t *)(data + sloc),
c6a6a5e3
AL		 312 net_checksum_finish(sum));
313 }
7c23b892
AZ		 314}
315
8f2e8d1f
AL		 316static inline int
317vlan_enabled(E1000State *s)
318{
319 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
320}
321
322static inline int
323vlan_rx_filter_enabled(E1000State *s)
324{
325 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
326}
327
328static inline int
329is_vlan_packet(E1000State *s, const uint8_t *buf)
330{
331 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
332 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
333}
334
335static inline int
336is_vlan_txd(uint32_t txd_lower)
337{
338 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
339}
340
55e8d1ce
MT		 341/* FCS aka Ethernet CRC-32. We don't get it from backends and can't
342 * fill it in, just pad descriptor length by 4 bytes unless guest
a05e8a6e 343 * told us to strip it off the packet. */
55e8d1ce
MT		 344static inline int
345fcs_len(E1000State *s)
346{
347 return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
348}
349
7c23b892
AZ		 350static void
351xmit_seg(E1000State *s)
352{
353 uint16_t len, *sp;
354 unsigned int frames = s->tx.tso_frames, css, sofar, n;
355 struct e1000_tx *tp = &s->tx;
356
1b0009db 357 if (tp->tse && tp->cptse) {
7c23b892
AZ		 358 css = tp->ipcss;
359 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
360 frames, tp->size, css);
361 if (tp->ip) { // IPv4
362 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
363 tp->size - css);
364 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
365 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
366 } else // IPv6
367 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
368 tp->size - css);
369 css = tp->tucss;
370 len = tp->size - css;
371 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
372 if (tp->tcp) {
373 sofar = frames * tp->mss;
374 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
88738c09 375 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
7c23b892
AZ		 376 if (tp->paylen - sofar > tp->mss)
377 tp->data[css + 13] &= ~9; // PSH, FIN
378 } else // UDP
379 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
380 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
e685b4eb 381 unsigned int phsum;
7c23b892
AZ		 382 // add pseudo-header length before checksum calculation
383 sp = (uint16_t *)(tp->data + tp->tucso);
e685b4eb
AW		 384 phsum = be16_to_cpup(sp) + len;
385 phsum = (phsum >> 16) + (phsum & 0xffff);
386 cpu_to_be16wu(sp, phsum);
7c23b892
AZ		 387 }
388 tp->tso_frames++;
389 }
390
391 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
392 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
393 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
394 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
8f2e8d1f 395 if (tp->vlan_needed) {
b10fec9b
SW		 396 memmove(tp->vlan, tp->data, 4);
397 memmove(tp->data, tp->data + 4, 8);
8f2e8d1f 398 memcpy(tp->data + 8, tp->vlan_header, 4);
a03e2aec 399 qemu_send_packet(&s->nic->nc, tp->vlan, tp->size + 4);
8f2e8d1f 400 } else
a03e2aec 401 qemu_send_packet(&s->nic->nc, tp->data, tp->size);
7c23b892
AZ		 402 s->mac_reg[TPT]++;
403 s->mac_reg[GPTC]++;
404 n = s->mac_reg[TOTL];
405 if ((s->mac_reg[TOTL] += s->tx.size) < n)
406 s->mac_reg[TOTH]++;
407}
408
409static void
410process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
411{
412 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
413 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
414 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
415 unsigned int msh = 0xfffff, hdr = 0;
416 uint64_t addr;
417 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
418 struct e1000_tx *tp = &s->tx;
419
420 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
421 op = le32_to_cpu(xp->cmd_and_length);
422 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
423 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
424 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
425 tp->tucss = xp->upper_setup.tcp_fields.tucss;
426 tp->tucso = xp->upper_setup.tcp_fields.tucso;
427 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
428 tp->paylen = op & 0xfffff;
429 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
430 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
431 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
432 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
433 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
434 tp->tso_frames = 0;
435 if (tp->tucso == 0) { // this is probably wrong
436 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
437 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
438 }
439 return;
1b0009db
AZ		 440 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
441 // data descriptor
735e77ec
SH		 442 if (tp->size == 0) {
443 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
444 }
1b0009db 445 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
43ad7e3e 446 } else {
1b0009db
AZ		 447 // legacy descriptor
448 tp->cptse = 0;
43ad7e3e 449 }
7c23b892 450
8f2e8d1f
AL		 451 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
452 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
453 tp->vlan_needed = 1;
454 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
455 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
456 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
457 le16_to_cpu(dp->upper.fields.special));
458 }
459
7c23b892 460 addr = le64_to_cpu(dp->buffer_addr);
1b0009db 461 if (tp->tse && tp->cptse) {
7c23b892
AZ		 462 hdr = tp->hdr_len;
463 msh = hdr + tp->mss;
1b0009db
AZ		 464 do {
465 bytes = split_size;
466 if (tp->size + bytes > msh)
467 bytes = msh - tp->size;
468 cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
469 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
470 memmove(tp->header, tp->data, hdr);
471 tp->size = sz;
472 addr += bytes;
473 if (sz == msh) {
474 xmit_seg(s);
475 memmove(tp->data, tp->header, hdr);
476 tp->size = hdr;
477 }
478 } while (split_size -= bytes);
479 } else if (!tp->tse && tp->cptse) {
480 // context descriptor TSE is not set, while data descriptor TSE is set
481 DBGOUT(TXERR, "TCP segmentaion Error\n");
482 } else {
483 cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
484 tp->size += split_size;
7c23b892 485 }
7c23b892
AZ		 486
487 if (!(txd_lower & E1000_TXD_CMD_EOP))
488 return;
1b0009db 489 if (!(tp->tse && tp->cptse && tp->size < hdr))
7c23b892
AZ		 490 xmit_seg(s);
491 tp->tso_frames = 0;
492 tp->sum_needed = 0;
8f2e8d1f 493 tp->vlan_needed = 0;
7c23b892 494 tp->size = 0;
1b0009db 495 tp->cptse = 0;
7c23b892
AZ		 496}
497
498static uint32_t
c227f099 499txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
7c23b892
AZ		 500{
501 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
502
503 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
504 return 0;
505 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
506 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
507 dp->upper.data = cpu_to_le32(txd_upper);
508 cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp),
509 (void *)&dp->upper, sizeof(dp->upper));
510 return E1000_ICR_TXDW;
511}
512
d17161f6
KW		 513static uint64_t tx_desc_base(E1000State *s)
514{
515 uint64_t bah = s->mac_reg[TDBAH];
516 uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
517
518 return (bah << 32) + bal;
519}
520
7c23b892
AZ		 521static void
522start_xmit(E1000State *s)
523{
c227f099 524 target_phys_addr_t base;
7c23b892
AZ		 525 struct e1000_tx_desc desc;
526 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
527
528 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
529 DBGOUT(TX, "tx disabled\n");
530 return;
531 }
532
533 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
d17161f6 534 base = tx_desc_base(s) +
7c23b892
AZ		 535 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
536 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
537
538 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
6106075b 539 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
7c23b892
AZ		 540 desc.upper.data);
541
542 process_tx_desc(s, &desc);
543 cause |= txdesc_writeback(base, &desc);
544
545 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
546 s->mac_reg[TDH] = 0;
547 /*
548 * the following could happen only if guest sw assigns
549 * bogus values to TDT/TDLEN.
550 * there's nothing too intelligent we could do about this.
551 */
552 if (s->mac_reg[TDH] == tdh_start) {
553 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
554 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
555 break;
556 }
557 }
558 set_ics(s, 0, cause);
559}
560
561static int
562receive_filter(E1000State *s, const uint8_t *buf, int size)
563{
af2960f9
BS		 564 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
565 static const int mta_shift[] = {4, 3, 2, 0};
7c23b892
AZ		 566 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
567
8f2e8d1f
AL		 568 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
569 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
570 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
571 ((vid >> 5) & 0x7f));
572 if ((vfta & (1 << (vid & 0x1f))) == 0)
573 return 0;
574 }
575
7c23b892
AZ		 576 if (rctl & E1000_RCTL_UPE) // promiscuous
577 return 1;
578
579 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
580 return 1;
581
582 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
583 return 1;
584
585 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
586 if (!(rp[1] & E1000_RAH_AV))
587 continue;
588 ra[0] = cpu_to_le32(rp[0]);
589 ra[1] = cpu_to_le32(rp[1]);
590 if (!memcmp(buf, (uint8_t *)ra, 6)) {
591 DBGOUT(RXFILTER,
592 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
593 (int)(rp - s->mac_reg - RA)/2,
594 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
595 return 1;
596 }
597 }
598 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
599 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
600
601 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
602 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
603 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
604 return 1;
605 DBGOUT(RXFILTER,
606 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
607 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
608 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
609 s->mac_reg[MTA + (f >> 5)]);
610
611 return 0;
612}
613
99ed7e30 614static void
a03e2aec 615e1000_set_link_status(VLANClientState *nc)
99ed7e30 616{
a03e2aec 617 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
99ed7e30
AL		 618 uint32_t old_status = s->mac_reg[STATUS];
619
a03e2aec 620 if (nc->link_down)
99ed7e30
AL		 621 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
622 else
623 s->mac_reg[STATUS] |= E1000_STATUS_LU;
624
625 if (s->mac_reg[STATUS] != old_status)
626 set_ics(s, 0, E1000_ICR_LSC);
627}
628
322fd48a
MT		 629static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
630{
631 int bufs;
632 /* Fast-path short packets */
633 if (total_size <= s->rxbuf_size) {
634 return s->mac_reg[RDH] != s->mac_reg[RDT] || !s->check_rxov;
635 }
636 if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
637 bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
638 } else if (s->mac_reg[RDH] > s->mac_reg[RDT] || !s->check_rxov) {
639 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
640 s->mac_reg[RDT] - s->mac_reg[RDH];
641 } else {
642 return false;
643 }
644 return total_size <= bufs * s->rxbuf_size;
645}
646
6cdfab28
MT		 647static int
648e1000_can_receive(VLANClientState *nc)
649{
650 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
651
652 return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1);
653}
654
d17161f6
KW		 655static uint64_t rx_desc_base(E1000State *s)
656{
657 uint64_t bah = s->mac_reg[RDBAH];
658 uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
659
660 return (bah << 32) + bal;
661}
662
4f1c942b 663static ssize_t
a03e2aec 664e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
7c23b892 665{
a03e2aec 666 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
7c23b892 667 struct e1000_rx_desc desc;
c227f099 668 target_phys_addr_t base;
7c23b892
AZ		 669 unsigned int n, rdt;
670 uint32_t rdh_start;
8f2e8d1f
AL		 671 uint16_t vlan_special = 0;
672 uint8_t vlan_status = 0, vlan_offset = 0;
78aeb23e 673 uint8_t min_buf[MIN_BUF_SIZE];
b19487e2
MT		 674 size_t desc_offset;
675 size_t desc_size;
676 size_t total_size;
7c23b892
AZ		 677
678 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
4f1c942b 679 return -1;
7c23b892 680
78aeb23e
SH		 681 /* Pad to minimum Ethernet frame length */
682 if (size < sizeof(min_buf)) {
683 memcpy(min_buf, buf, size);
684 memset(&min_buf[size], 0, sizeof(min_buf) - size);
685 buf = min_buf;
686 size = sizeof(min_buf);
687 }
688
7c23b892 689 if (!receive_filter(s, buf, size))
4f1c942b 690 return size;
7c23b892 691
8f2e8d1f
AL		 692 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
693 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
98835fe3 694 memmove((uint8_t *)buf + 4, buf, 12);
8f2e8d1f
AL		 695 vlan_status = E1000_RXD_STAT_VP;
696 vlan_offset = 4;
697 size -= 4;
698 }
699
7c23b892 700 rdh_start = s->mac_reg[RDH];
b19487e2
MT		 701 desc_offset = 0;
702 total_size = size + fcs_len(s);
322fd48a
MT		 703 if (!e1000_has_rxbufs(s, total_size)) {
704 set_ics(s, 0, E1000_ICS_RXO);
705 return -1;
706 }
7c23b892 707 do {
b19487e2
MT		 708 desc_size = total_size - desc_offset;
709 if (desc_size > s->rxbuf_size) {
710 desc_size = s->rxbuf_size;
711 }
d17161f6 712 base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
7c23b892 713 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
8f2e8d1f
AL		 714 desc.special = vlan_special;
715 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
7c23b892 716 if (desc.buffer_addr) {
b19487e2
MT		 717 if (desc_offset < size) {
718 size_t copy_size = size - desc_offset;
719 if (copy_size > s->rxbuf_size) {
720 copy_size = s->rxbuf_size;
721 }
722 cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr),
723 (void *)(buf + desc_offset + vlan_offset),
724 copy_size);
725 }
726 desc_offset += desc_size;
ee912ccf 727 desc.length = cpu_to_le16(desc_size);
b19487e2 728 if (desc_offset >= total_size) {
b19487e2
MT		 729 desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
730 } else {
ee912ccf
MT		 731 /* Guest zeroing out status is not a hardware requirement.
732 Clear EOP in case guest didn't do it. */
733 desc.status &= ~E1000_RXD_STAT_EOP;
b19487e2 734 }
43ad7e3e 735 } else { // as per intel docs; skip descriptors with null buf addr
7c23b892 736 DBGOUT(RX, "Null RX descriptor!!\n");
43ad7e3e 737 }
7c23b892
AZ		 738 cpu_physical_memory_write(base, (void *)&desc, sizeof(desc));
739
740 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
741 s->mac_reg[RDH] = 0;
742 s->check_rxov = 1;
743 /* see comment in start_xmit; same here */
744 if (s->mac_reg[RDH] == rdh_start) {
745 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
746 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
747 set_ics(s, 0, E1000_ICS_RXO);
4f1c942b 748 return -1;
7c23b892 749 }
b19487e2 750 } while (desc_offset < total_size);
7c23b892
AZ		 751
752 s->mac_reg[GPRC]++;
753 s->mac_reg[TPR]++;
a05e8a6e
MT		 754 /* TOR - Total Octets Received:
755 * This register includes bytes received in a packet from the <Destination
756 * Address> field through the <CRC> field, inclusively.
757 */
758 n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
759 if (n < s->mac_reg[TORL])
7c23b892 760 s->mac_reg[TORH]++;
a05e8a6e 761 s->mac_reg[TORL] = n;
7c23b892
AZ		 762
763 n = E1000_ICS_RXT0;
764 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
765 rdt += s->mac_reg[RDLEN] / sizeof(desc);
bf16cc8f
AL		 766 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
767 s->rxbuf_min_shift)
7c23b892
AZ		 768 n |= E1000_ICS_RXDMT0;
769
770 set_ics(s, 0, n);
4f1c942b
MM		 771
772 return size;
7c23b892
AZ		 773}
774
775static uint32_t
776mac_readreg(E1000State *s, int index)
777{
778 return s->mac_reg[index];
779}
780
781static uint32_t
782mac_icr_read(E1000State *s, int index)
783{
784 uint32_t ret = s->mac_reg[ICR];
785
786 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
787 set_interrupt_cause(s, 0, 0);
788 return ret;
789}
790
791static uint32_t
792mac_read_clr4(E1000State *s, int index)
793{
794 uint32_t ret = s->mac_reg[index];
795
796 s->mac_reg[index] = 0;
797 return ret;
798}
799
800static uint32_t
801mac_read_clr8(E1000State *s, int index)
802{
803 uint32_t ret = s->mac_reg[index];
804
805 s->mac_reg[index] = 0;
806 s->mac_reg[index-1] = 0;
807 return ret;
808}
809
810static void
811mac_writereg(E1000State *s, int index, uint32_t val)
812{
813 s->mac_reg[index] = val;
814}
815
816static void
817set_rdt(E1000State *s, int index, uint32_t val)
818{
819 s->check_rxov = 0;
820 s->mac_reg[index] = val & 0xffff;
821}
822
823static void
824set_16bit(E1000State *s, int index, uint32_t val)
825{
826 s->mac_reg[index] = val & 0xffff;
827}
828
829static void
830set_dlen(E1000State *s, int index, uint32_t val)
831{
832 s->mac_reg[index] = val & 0xfff80;
833}
834
835static void
836set_tctl(E1000State *s, int index, uint32_t val)
837{
838 s->mac_reg[index] = val;
839 s->mac_reg[TDT] &= 0xffff;
840 start_xmit(s);
841}
842
843static void
844set_icr(E1000State *s, int index, uint32_t val)
845{
846 DBGOUT(INTERRUPT, "set_icr %x\n", val);
847 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
848}
849
850static void
851set_imc(E1000State *s, int index, uint32_t val)
852{
853 s->mac_reg[IMS] &= ~val;
854 set_ics(s, 0, 0);
855}
856
857static void
858set_ims(E1000State *s, int index, uint32_t val)
859{
860 s->mac_reg[IMS] |= val;
861 set_ics(s, 0, 0);
862}
863
864#define getreg(x) [x] = mac_readreg
865static uint32_t (*macreg_readops[])(E1000State *, int) = {
866 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
867 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
868 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
869 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
b1332393 870 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
a00b2335
KA		 871 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
872 getreg(TDLEN), getreg(RDLEN),
7c23b892
AZ		 873
874 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
875 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
876 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
877 [CRCERRS ... MPC] = &mac_readreg,
878 [RA ... RA+31] = &mac_readreg,
879 [MTA ... MTA+127] = &mac_readreg,
8f2e8d1f 880 [VFTA ... VFTA+127] = &mac_readreg,
7c23b892 881};
b1503cda 882enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
7c23b892
AZ		 883
884#define putreg(x) [x] = mac_writereg
885static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
886 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
887 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
cab3c825 888 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
7c23b892
AZ		 889 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
890 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
891 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
892 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
cab3c825 893 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
7c23b892
AZ		 894 [RA ... RA+31] = &mac_writereg,
895 [MTA ... MTA+127] = &mac_writereg,
8f2e8d1f 896 [VFTA ... VFTA+127] = &mac_writereg,
7c23b892 897};
b1503cda 898enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
7c23b892
AZ		 899
900static void
ad00a9b9
AK		 901e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
902 unsigned size)
7c23b892
AZ		 903{
904 E1000State *s = opaque;
8da3ff18 905 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892 906
43ad7e3e 907 if (index < NWRITEOPS && macreg_writeops[index]) {
6b59fc74 908 macreg_writeops[index](s, index, val);
43ad7e3e 909 } else if (index < NREADOPS && macreg_readops[index]) {
ad00a9b9 910 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val);
43ad7e3e 911 } else {
ad00a9b9 912 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
7c23b892 913 index<<2, val);
43ad7e3e 914 }
7c23b892
AZ		 915}
916
ad00a9b9
AK		 917static uint64_t
918e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
7c23b892
AZ		 919{
920 E1000State *s = opaque;
8da3ff18 921 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892
AZ		 922
923 if (index < NREADOPS && macreg_readops[index])
6b59fc74 924 {
32600a30 925 return macreg_readops[index](s, index);
6b59fc74 926 }
7c23b892
AZ		 927 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
928 return 0;
929}
930
ad00a9b9
AK		 931static const MemoryRegionOps e1000_mmio_ops = {
932 .read = e1000_mmio_read,
933 .write = e1000_mmio_write,
934 .endianness = DEVICE_LITTLE_ENDIAN,
935 .impl = {
936 .min_access_size = 4,
937 .max_access_size = 4,
938 },
939};
940
941static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
942 unsigned size)
7c23b892 943{
ad00a9b9
AK		 944 E1000State *s = opaque;
945
946 (void)s;
947 return 0;
7c23b892
AZ		 948}
949
ad00a9b9
AK		 950static void e1000_io_write(void *opaque, target_phys_addr_t addr,
951 uint64_t val, unsigned size)
7c23b892 952{
ad00a9b9
AK		 953 E1000State *s = opaque;
954
955 (void)s;
7c23b892
AZ		 956}
957
ad00a9b9
AK		 958static const MemoryRegionOps e1000_io_ops = {
959 .read = e1000_io_read,
960 .write = e1000_io_write,
961 .endianness = DEVICE_LITTLE_ENDIAN,
962};
963
e482dc3e 964static bool is_version_1(void *opaque, int version_id)
7c23b892 965{
e482dc3e 966 return version_id == 1;
7c23b892
AZ		 967}
968
e482dc3e
JQ		 969static const VMStateDescription vmstate_e1000 = {
970 .name = "e1000",
971 .version_id = 2,
972 .minimum_version_id = 1,
973 .minimum_version_id_old = 1,
974 .fields = (VMStateField []) {
975 VMSTATE_PCI_DEVICE(dev, E1000State),
976 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
977 VMSTATE_UNUSED(4), /* Was mmio_base. */
978 VMSTATE_UINT32(rxbuf_size, E1000State),
979 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
980 VMSTATE_UINT32(eecd_state.val_in, E1000State),
981 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
982 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
983 VMSTATE_UINT16(eecd_state.reading, E1000State),
984 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
985 VMSTATE_UINT8(tx.ipcss, E1000State),
986 VMSTATE_UINT8(tx.ipcso, E1000State),
987 VMSTATE_UINT16(tx.ipcse, E1000State),
988 VMSTATE_UINT8(tx.tucss, E1000State),
989 VMSTATE_UINT8(tx.tucso, E1000State),
990 VMSTATE_UINT16(tx.tucse, E1000State),
991 VMSTATE_UINT32(tx.paylen, E1000State),
992 VMSTATE_UINT8(tx.hdr_len, E1000State),
993 VMSTATE_UINT16(tx.mss, E1000State),
994 VMSTATE_UINT16(tx.size, E1000State),
995 VMSTATE_UINT16(tx.tso_frames, E1000State),
996 VMSTATE_UINT8(tx.sum_needed, E1000State),
997 VMSTATE_INT8(tx.ip, E1000State),
998 VMSTATE_INT8(tx.tcp, E1000State),
999 VMSTATE_BUFFER(tx.header, E1000State),
1000 VMSTATE_BUFFER(tx.data, E1000State),
1001 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
1002 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
1003 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
1004 VMSTATE_UINT32(mac_reg[EECD], E1000State),
1005 VMSTATE_UINT32(mac_reg[EERD], E1000State),
1006 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
1007 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
1008 VMSTATE_UINT32(mac_reg[ICR], E1000State),
1009 VMSTATE_UINT32(mac_reg[ICS], E1000State),
1010 VMSTATE_UINT32(mac_reg[IMC], E1000State),
1011 VMSTATE_UINT32(mac_reg[IMS], E1000State),
1012 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
1013 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1014 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1015 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1016 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1017 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1018 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1019 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1020 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1021 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1022 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1023 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1024 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1025 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1026 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1027 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1028 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1029 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1030 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1031 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1032 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1033 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1034 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1035 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1036 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1037 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1038 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1039 VMSTATE_UINT32(mac_reg[VET], E1000State),
1040 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1041 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
1042 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
1043 VMSTATE_END_OF_LIST()
1044 }
1045};
7c23b892 1046
88b4e9db 1047static const uint16_t e1000_eeprom_template[64] = {
7c23b892
AZ		 1048 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1049 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
1050 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1051 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1052 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1053 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1054 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1055 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1056};
1057
88b4e9db 1058static const uint16_t phy_reg_init[] = {
7c23b892
AZ		 1059 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
1060 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
1061 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
1062 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
1063 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
700f6e2c 1064 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
7c23b892
AZ		 1065};
1066
88b4e9db 1067static const uint32_t mac_reg_init[] = {
7c23b892
AZ		 1068 [PBA] = 0x00100030,
1069 [LEDCTL] = 0x602,
1070 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
1071 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
1072 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
1073 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
1074 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
1075 E1000_STATUS_LU,
1076 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
1077 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
1078 E1000_MANC_RMCP_EN,
1079};
1080
1081/* PCI interface */
1082
7c23b892 1083static void
ad00a9b9 1084e1000_mmio_setup(E1000State *d)
7c23b892 1085{
f65ed4c1
AL		 1086 int i;
1087 const uint32_t excluded_regs[] = {
1088 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1089 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1090 };
1091
ad00a9b9
AK		 1092 memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
1093 PNPMMIO_SIZE);
1094 memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);
f65ed4c1 1095 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
ad00a9b9
AK		 1096 memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
1097 excluded_regs[i+1] - excluded_regs[i] - 4);
1098 memory_region_init_io(&d->io, &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
7c23b892
AZ		 1099}
1100
b946a153 1101static void
a03e2aec 1102e1000_cleanup(VLANClientState *nc)
b946a153 1103{
a03e2aec 1104 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 1105
a03e2aec 1106 s->nic = NULL;
b946a153
AL		 1107}
1108
4b09be85
AL		 1109static int
1110pci_e1000_uninit(PCIDevice *dev)
1111{
7d9e52bd 1112 E1000State *d = DO_UPCAST(E1000State, dev, dev);
4b09be85 1113
ad00a9b9
AK		 1114 memory_region_destroy(&d->mmio);
1115 memory_region_destroy(&d->io);
a03e2aec 1116 qemu_del_vlan_client(&d->nic->nc);
4b09be85
AL		 1117 return 0;
1118}
1119
32c86e95
BS		 1120static void e1000_reset(void *opaque)
1121{
1122 E1000State *d = opaque;
1123
1124 memset(d->phy_reg, 0, sizeof d->phy_reg);
1125 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1126 memset(d->mac_reg, 0, sizeof d->mac_reg);
1127 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1128 d->rxbuf_min_shift = 1;
1129 memset(&d->tx, 0, sizeof d->tx);
1130}
1131
a03e2aec
MM		 1132static NetClientInfo net_e1000_info = {
1133 .type = NET_CLIENT_TYPE_NIC,
1134 .size = sizeof(NICState),
1135 .can_receive = e1000_can_receive,
1136 .receive = e1000_receive,
1137 .cleanup = e1000_cleanup,
1138 .link_status_changed = e1000_set_link_status,
1139};
1140
81a322d4 1141static int pci_e1000_init(PCIDevice *pci_dev)
7c23b892 1142{
7d9e52bd 1143 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
7c23b892 1144 uint8_t *pci_conf;
7c23b892 1145 uint16_t checksum = 0;
7c23b892 1146 int i;
fbdaa002 1147 uint8_t *macaddr;
aff427a1 1148
7c23b892 1149 pci_conf = d->dev.config;
7c23b892 1150
a9cbacb0
MT		 1151 /* TODO: we have no capabilities, so why is this bit set? */
1152 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST);
a9cbacb0
MT		 1153 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1154 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
7c23b892 1155
a9cbacb0
MT		 1156 /* TODO: RST# value should be 0 if programmable, PCI spec 6.2.4 */
1157 pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
7c23b892 1158
ad00a9b9 1159 e1000_mmio_setup(d);
7c23b892 1160
e824b2cc 1161 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
7c23b892 1162
e824b2cc 1163 pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
7c23b892 1164
7c23b892
AZ		 1165 memmove(d->eeprom_data, e1000_eeprom_template,
1166 sizeof e1000_eeprom_template);
fbdaa002
GH		 1167 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1168 macaddr = d->conf.macaddr.a;
7c23b892 1169 for (i = 0; i < 3; i++)
9d07d757 1170 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
7c23b892
AZ		 1171 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1172 checksum += d->eeprom_data[i];
1173 checksum = (uint16_t) EEPROM_SUM - checksum;
1174 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1175
a03e2aec
MM		 1176 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
1177 d->dev.qdev.info->name, d->dev.qdev.id, d);
7c23b892 1178
a03e2aec 1179 qemu_format_nic_info_str(&d->nic->nc, macaddr);
1ca4d09a
GN		 1180
1181 add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1182
81a322d4 1183 return 0;
9d07d757 1184}
72da4208 1185
fbdaa002
GH		 1186static void qdev_e1000_reset(DeviceState *dev)
1187{
1188 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1189 e1000_reset(d);
1190}
1191
0aab0d3a 1192static PCIDeviceInfo e1000_info = {
fbdaa002
GH		 1193 .qdev.name = "e1000",
1194 .qdev.desc = "Intel Gigabit Ethernet",
1195 .qdev.size = sizeof(E1000State),
1196 .qdev.reset = qdev_e1000_reset,
be73cfe2 1197 .qdev.vmsd = &vmstate_e1000,
fbdaa002
GH		 1198 .init = pci_e1000_init,
1199 .exit = pci_e1000_uninit,
5ee8ad71 1200 .romfile = "pxe-e1000.rom",
e72d5c9d
IY		 1201 .vendor_id = PCI_VENDOR_ID_INTEL,
1202 .device_id = E1000_DEVID,
1203 .revision = 0x03,
1204 .class_id = PCI_CLASS_NETWORK_ETHERNET,
fbdaa002
GH		 1205 .qdev.props = (Property[]) {
1206 DEFINE_NIC_PROPERTIES(E1000State, conf),
1207 DEFINE_PROP_END_OF_LIST(),
1208 }
0aab0d3a
GH		 1209};
1210
9d07d757
PB		 1211static void e1000_register_devices(void)
1212{
0aab0d3a 1213 pci_qdev_register(&e1000_info);
7c23b892 1214}
9d07d757
PB		 1215
1216device_init(e1000_register_devices)
Empty description
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