[qemu.git] / hw / arm / stm32f205_soc.c

/*
 * STM32F205 SoC
 *
 * Copyright (c) 2014 Alistair Francis <[email protected]>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/arm/boot.h"
#include "exec/address-spaces.h"
#include "hw/arm/stm32f205_soc.h"

/* At the moment only Timer 2 to 5 are modelled */
static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
    0x40000800, 0x40000C00 };
static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
    0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
    0x40012200 };
static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
    0x40003C00 };

static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
#define ADC_IRQ 18
static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};

static void stm32f205_soc_initfn(Object *obj)
{
    STM32F205State *s = STM32F205_SOC(obj);
    int i;

    sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
                          TYPE_ARMV7M);

    sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
                          TYPE_STM32F2XX_SYSCFG);

    for (i = 0; i < STM_NUM_USARTS; i++) {
        sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
                              sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
    }

    for (i = 0; i < STM_NUM_TIMERS; i++) {
        sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
                              sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
    }

    s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));

    for (i = 0; i < STM_NUM_ADCS; i++) {
        sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
                              TYPE_STM32F2XX_ADC);
    }

    for (i = 0; i < STM_NUM_SPIS; i++) {
        sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
                              TYPE_STM32F2XX_SPI);
    }
}

static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
{
    STM32F205State *s = STM32F205_SOC(dev_soc);
    DeviceState *dev, *armv7m;
    SysBusDevice *busdev;
    Error *err = NULL;
    int i;

    MemoryRegion *system_memory = get_system_memory();
    MemoryRegion *sram = g_new(MemoryRegion, 1);
    MemoryRegion *flash = g_new(MemoryRegion, 1);
    MemoryRegion *flash_alias = g_new(MemoryRegion, 1);

    memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
                           &error_fatal);
    memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
                             flash, 0, FLASH_SIZE);

    memory_region_set_readonly(flash, true);
    memory_region_set_readonly(flash_alias, true);

    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
    memory_region_add_subregion(system_memory, 0, flash_alias);

    memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
                           &error_fatal);
    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);

    armv7m = DEVICE(&s->armv7m);
    qdev_prop_set_uint32(armv7m, "num-irq", 96);
    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
    qdev_prop_set_bit(armv7m, "enable-bitband", true);
    object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
                                     "memory", &error_abort);
    object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }

    /* System configuration controller */
    dev = DEVICE(&s->syscfg);
    object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, 0x40013800);
    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));

    /* Attach UART (uses USART registers) and USART controllers */
    for (i = 0; i < STM_NUM_USARTS; i++) {
        dev = DEVICE(&(s->usart[i]));
        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
        object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, usart_addr[i]);
        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
    }

    /* Timer 2 to 5 */
    for (i = 0; i < STM_NUM_TIMERS; i++) {
        dev = DEVICE(&(s->timer[i]));
        qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
        object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, timer_addr[i]);
        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
    }

    /* ADC 1 to 3 */
    object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
                            "num-lines", &err);
    object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }
    qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
                          qdev_get_gpio_in(armv7m, ADC_IRQ));

    for (i = 0; i < STM_NUM_ADCS; i++) {
        dev = DEVICE(&(s->adc[i]));
        object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, adc_addr[i]);
        sysbus_connect_irq(busdev, 0,
                           qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
    }

    /* SPI 1 and 2 */
    for (i = 0; i < STM_NUM_SPIS; i++) {
        dev = DEVICE(&(s->spi[i]));
        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, spi_addr[i]);
        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
    }
}

static Property stm32f205_soc_properties[] = {
    DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
    DEFINE_PROP_END_OF_LIST(),
};

static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = stm32f205_soc_realize;
    dc->props = stm32f205_soc_properties;
}

static const TypeInfo stm32f205_soc_info = {
    .name          = TYPE_STM32F205_SOC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(STM32F205State),
    .instance_init = stm32f205_soc_initfn,
    .class_init    = stm32f205_soc_class_init,
};

static void stm32f205_soc_types(void)
{
    type_register_static(&stm32f205_soc_info);
}

type_init(stm32f205_soc_types)
Commit	Line	Data
db635521 AF	1	/*
	2	* STM32F205 SoC
	3	*
	4	* Copyright (c) 2014 Alistair Francis <[email protected]>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
12b16722	25	#include "qemu/osdep.h"
da34e65c	26	#include "qapi/error.h"
0b8fa32f	27	#include "qemu/module.h"
12ec8bd5	28	#include "hw/arm/boot.h"
db635521 AF	29	#include "exec/address-spaces.h"
	30	#include "hw/arm/stm32f205_soc.h"
	31
	32	/* At the moment only Timer 2 to 5 are modelled */
	33	static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
	34	0x40000800, 0x40000C00 };
	35	static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
	36	0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
b63041c8 AF	37	static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
b63041c8 AF	38	0x40012200 };
540a8f34 AF	39	static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
540a8f34 AF	40	0x40003C00 };
db635521 AF	41
	42	static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
	43	static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
b63041c8	44	#define ADC_IRQ 18
540a8f34	45	static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
db635521 AF	46
	47	static void stm32f205_soc_initfn(Object *obj)
	48	{
	49	STM32F205State *s = STM32F205_SOC(obj);
	50	int i;
	51
a39ae816 TH	52	sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
a39ae816 TH	53	TYPE_ARMV7M);
b72e2f68	54
a39ae816 TH	55	sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
a39ae816 TH	56	TYPE_STM32F2XX_SYSCFG);
db635521 AF	57
db635521 AF	58	for (i = 0; i < STM_NUM_USARTS; i++) {
a39ae816 TH	59	sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
a39ae816 TH	60	sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
db635521 AF	61	}
	62
	63	for (i = 0; i < STM_NUM_TIMERS; i++) {
a39ae816 TH	64	sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
a39ae816 TH	65	sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
db635521	66	}
b63041c8 AF	67
	68	s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
	69
	70	for (i = 0; i < STM_NUM_ADCS; i++) {
a39ae816 TH	71	sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
a39ae816 TH	72	TYPE_STM32F2XX_ADC);
b63041c8	73	}
540a8f34 AF	74
540a8f34 AF	75	for (i = 0; i < STM_NUM_SPIS; i++) {
a39ae816 TH	76	sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
a39ae816 TH	77	TYPE_STM32F2XX_SPI);
540a8f34	78	}
db635521 AF	79	}
	80
	81	static void stm32f205_soc_realize(DeviceState dev_soc, Error *errp)
	82	{
	83	STM32F205State *s = STM32F205_SOC(dev_soc);
8a85e065	84	DeviceState dev, armv7m;
81fed1d0	85	SysBusDevice *busdev;
db635521 AF	86	Error *err = NULL;
	87	int i;
	88
	89	MemoryRegion *system_memory = get_system_memory();
	90	MemoryRegion *sram = g_new(MemoryRegion, 1);
	91	MemoryRegion *flash = g_new(MemoryRegion, 1);
	92	MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
	93
98a99ce0	94	memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
f8ed85ac	95	&error_fatal);
db635521 AF	96	memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
	97	flash, 0, FLASH_SIZE);
	98
db635521 AF	99	memory_region_set_readonly(flash, true);
	100	memory_region_set_readonly(flash_alias, true);
	101
	102	memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
	103	memory_region_add_subregion(system_memory, 0, flash_alias);
	104
98a99ce0	105	memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
f8ed85ac	106	&error_fatal);
db635521 AF	107	memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
db635521 AF	108
8a85e065 PM	109	armv7m = DEVICE(&s->armv7m);
8a85e065 PM	110	qdev_prop_set_uint32(armv7m, "num-irq", 96);
ba1ba5cc	111	qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
a1c5a062	112	qdev_prop_set_bit(armv7m, "enable-bitband", true);
b72e2f68 PM	113	object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
	114	"memory", &error_abort);
	115	object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
	116	if (err != NULL) {
	117	error_propagate(errp, err);
	118	return;
	119	}
db635521 AF	120
db635521 AF	121	/* System configuration controller */
81fed1d0	122	dev = DEVICE(&s->syscfg);
db635521 AF	123	object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
	124	if (err != NULL) {
	125	error_propagate(errp, err);
	126	return;
	127	}
81fed1d0 AF	128	busdev = SYS_BUS_DEVICE(dev);
81fed1d0 AF	129	sysbus_mmio_map(busdev, 0, 0x40013800);
8a85e065	130	sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
db635521 AF	131
	132	/* Attach UART (uses USART registers) and USART controllers */
	133	for (i = 0; i < STM_NUM_USARTS; i++) {
81fed1d0	134	dev = DEVICE(&(s->usart[i]));
fc38a112	135	qdev_prop_set_chr(dev, "chardev", serial_hd(i));
db635521 AF	136	object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
	137	if (err != NULL) {
	138	error_propagate(errp, err);
	139	return;
	140	}
81fed1d0 AF	141	busdev = SYS_BUS_DEVICE(dev);
81fed1d0 AF	142	sysbus_mmio_map(busdev, 0, usart_addr[i]);
8a85e065	143	sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
db635521 AF	144	}
	145
	146	/* Timer 2 to 5 */
	147	for (i = 0; i < STM_NUM_TIMERS; i++) {
81fed1d0 AF	148	dev = DEVICE(&(s->timer[i]));
81fed1d0 AF	149	qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
db635521 AF	150	object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
	151	if (err != NULL) {
	152	error_propagate(errp, err);
	153	return;
	154	}
81fed1d0 AF	155	busdev = SYS_BUS_DEVICE(dev);
81fed1d0 AF	156	sysbus_mmio_map(busdev, 0, timer_addr[i]);
8a85e065	157	sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
db635521	158	}
b63041c8 AF	159
	160	/* ADC 1 to 3 */
	161	object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
	162	"num-lines", &err);
	163	object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
	164	if (err != NULL) {
	165	error_propagate(errp, err);
	166	return;
	167	}
	168	qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
8a85e065	169	qdev_get_gpio_in(armv7m, ADC_IRQ));
b63041c8 AF	170
	171	for (i = 0; i < STM_NUM_ADCS; i++) {
	172	dev = DEVICE(&(s->adc[i]));
	173	object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
	174	if (err != NULL) {
	175	error_propagate(errp, err);
	176	return;
	177	}
	178	busdev = SYS_BUS_DEVICE(dev);
	179	sysbus_mmio_map(busdev, 0, adc_addr[i]);
	180	sysbus_connect_irq(busdev, 0,
	181	qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
	182	}
540a8f34 AF	183
	184	/* SPI 1 and 2 */
	185	for (i = 0; i < STM_NUM_SPIS; i++) {
	186	dev = DEVICE(&(s->spi[i]));
	187	object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
	188	if (err != NULL) {
	189	error_propagate(errp, err);
	190	return;
	191	}
	192	busdev = SYS_BUS_DEVICE(dev);
	193	sysbus_mmio_map(busdev, 0, spi_addr[i]);
8a85e065	194	sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
540a8f34	195	}
db635521 AF	196	}
	197
	198	static Property stm32f205_soc_properties[] = {
ba1ba5cc	199	DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
db635521 AF	200	DEFINE_PROP_END_OF_LIST(),
	201	};
	202
	203	static void stm32f205_soc_class_init(ObjectClass klass, void data)
	204	{
	205	DeviceClass *dc = DEVICE_CLASS(klass);
	206
	207	dc->realize = stm32f205_soc_realize;
	208	dc->props = stm32f205_soc_properties;
	209	}
	210
	211	static const TypeInfo stm32f205_soc_info = {
	212	.name = TYPE_STM32F205_SOC,
	213	.parent = TYPE_SYS_BUS_DEVICE,
	214	.instance_size = sizeof(STM32F205State),
	215	.instance_init = stm32f205_soc_initfn,
	216	.class_init = stm32f205_soc_class_init,
	217	};
	218
	219	static void stm32f205_soc_types(void)
	220	{
	221	type_register_static(&stm32f205_soc_info);
	222	}
	223
	224	type_init(stm32f205_soc_types)