[qemu.git] / hw / arm / fsl-imx31.c

/*
 * Copyright (c) 2013 Jean-Christophe Dubois <[email protected]>
 *
 * i.MX31 SOC emulation.
 *
 * Based on hw/arm/fsl-imx31.c
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/arm/fsl-imx31.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "chardev/char.h"

static void fsl_imx31_init(Object *obj)
{
    FslIMX31State *s = FSL_IMX31(obj);
    int i;

    object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);

    sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
                          TYPE_IMX_AVIC);

    sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);

    for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
        sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
                              TYPE_IMX_SERIAL);
    }

    sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);

    for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
        sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
                              TYPE_IMX_EPIT);
    }

    for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
        sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
                              TYPE_IMX_I2C);
    }

    for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
        sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
                              TYPE_IMX_GPIO);
    }
}

static void fsl_imx31_realize(DeviceState *dev, Error **errp)
{
    FslIMX31State *s = FSL_IMX31(dev);
    uint16_t i;
    Error *err = NULL;

    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));

    object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);

    /* Initialize all UARTS */
    for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } serial_table[FSL_IMX31_NUM_UARTS] = {
            { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
            { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
        };

        qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));

        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            serial_table[i].irq));
    }

    s->gpt.ccm = IMX_CCM(&s->ccm);

    object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
                       qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));

    /* Initialize all EPIT timers */
    for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } epit_table[FSL_IMX31_NUM_EPITS] = {
            { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
            { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
        };

        s->epit[i].ccm = IMX_CCM(&s->ccm);

        object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            epit_table[i].irq));
    }

    /* Initialize all I2C */
    for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } i2c_table[FSL_IMX31_NUM_I2CS] = {
            { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
            { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
            { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
        };

        /* Initialize the I2C */
        object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        /* Map I2C memory */
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
        /* Connect I2C IRQ to PIC */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            i2c_table[i].irq));
    }

    /* Initialize all GPIOs */
    for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } gpio_table[FSL_IMX31_NUM_GPIOS] = {
            { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
            { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
            { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
        };

        object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
                                 &error_abort);
        object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
        /* Connect GPIO IRQ to PIC */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            gpio_table[i].irq));
    }

    /* On a real system, the first 16k is a `secure boot rom' */
    memory_region_init_rom(&s->secure_rom, NULL, "imx31.secure_rom",
                           FSL_IMX31_SECURE_ROM_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
                                &s->secure_rom);

    /* There is also a 16k ROM */
    memory_region_init_rom(&s->rom, NULL, "imx31.rom",
                           FSL_IMX31_ROM_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
                                &s->rom);

    /* initialize internal RAM (16 KB) */
    memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
                           &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
                                &s->iram);

    /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
    memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",
                             &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
    memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
                                &s->iram_alias);
}

static void fsl_imx31_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = fsl_imx31_realize;
    dc->desc = "i.MX31 SOC";
    /*
     * Reason: uses serial_hds in realize and the kzm board does not
     * support multiple CPUs
     */
    dc->user_creatable = false;
}

static const TypeInfo fsl_imx31_type_info = {
    .name = TYPE_FSL_IMX31,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(FslIMX31State),
    .instance_init = fsl_imx31_init,
    .class_init = fsl_imx31_class_init,
};

static void fsl_imx31_register_types(void)
{
    type_register_static(&fsl_imx31_type_info);
}

type_init(fsl_imx31_register_types)
Commit	Line	Data
558df83d JCD	1	/*
	2	* Copyright (c) 2013 Jean-Christophe Dubois <[email protected]>
	3	*
	4	* i.MX31 SOC emulation.
	5	*
	6	* Based on hw/arm/fsl-imx31.c
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful, but WITHOUT
	14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
12b16722	22	#include "qemu/osdep.h"
da34e65c	23	#include "qapi/error.h"
4771d756	24	#include "cpu.h"
558df83d JCD	25	#include "hw/arm/fsl-imx31.h"
	26	#include "sysemu/sysemu.h"
	27	#include "exec/address-spaces.h"
	28	#include "hw/boards.h"
8228e353	29	#include "chardev/char.h"
558df83d JCD	30
	31	static void fsl_imx31_init(Object *obj)
	32	{
	33	FslIMX31State *s = FSL_IMX31(obj);
	34	int i;
	35
	36	object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);
	37
aac409c9 TH	38	sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
aac409c9 TH	39	TYPE_IMX_AVIC);
558df83d	40
aac409c9	41	sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);
558df83d JCD	42
558df83d JCD	43	for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
aac409c9 TH	44	sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
aac409c9 TH	45	TYPE_IMX_SERIAL);
558df83d JCD	46	}
558df83d JCD	47
aac409c9	48	sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);
558df83d JCD	49
558df83d JCD	50	for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
aac409c9 TH	51	sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
aac409c9 TH	52	TYPE_IMX_EPIT);
558df83d	53	}
d4e26d10 JCD	54
d4e26d10 JCD	55	for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
aac409c9 TH	56	sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
aac409c9 TH	57	TYPE_IMX_I2C);
d4e26d10	58	}
dde0c4ca JCD	59
dde0c4ca JCD	60	for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
aac409c9 TH	61	sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
aac409c9 TH	62	TYPE_IMX_GPIO);
dde0c4ca	63	}
558df83d JCD	64	}
	65
	66	static void fsl_imx31_realize(DeviceState dev, Error *errp)
	67	{
	68	FslIMX31State *s = FSL_IMX31(dev);
	69	uint16_t i;
	70	Error *err = NULL;
	71
	72	object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
	73	if (err) {
	74	error_propagate(errp, err);
	75	return;
	76	}
	77
	78	object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
	79	if (err) {
	80	error_propagate(errp, err);
	81	return;
	82	}
	83	sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
	84	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
	85	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
	86	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
	87	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
	88
	89	object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
	90	if (err) {
	91	error_propagate(errp, err);
	92	return;
	93	}
	94	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
	95
	96	/* Initialize all UARTS */
	97	for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
	98	static const struct {
	99	hwaddr addr;
	100	unsigned int irq;
	101	} serial_table[FSL_IMX31_NUM_UARTS] = {
	102	{ FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
	103	{ FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
	104	};
	105
fc38a112	106	qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
558df83d JCD	107
	108	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
	109	if (err) {
	110	error_propagate(errp, err);
	111	return;
	112	}
	113
	114	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
	115	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	116	qdev_get_gpio_in(DEVICE(&s->avic),
	117	serial_table[i].irq));
	118	}
	119
cb54d868	120	s->gpt.ccm = IMX_CCM(&s->ccm);
558df83d JCD	121
	122	object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
	123	if (err) {
	124	error_propagate(errp, err);
	125	return;
	126	}
	127
	128	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
	129	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
	130	qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));
	131
	132	/* Initialize all EPIT timers */
	133	for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
	134	static const struct {
	135	hwaddr addr;
	136	unsigned int irq;
	137	} epit_table[FSL_IMX31_NUM_EPITS] = {
	138	{ FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
	139	{ FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
	140	};
	141
cb54d868	142	s->epit[i].ccm = IMX_CCM(&s->ccm);
558df83d JCD	143
	144	object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
	145	if (err) {
	146	error_propagate(errp, err);
	147	return;
	148	}
	149
	150	sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
	151	sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
	152	qdev_get_gpio_in(DEVICE(&s->avic),
	153	epit_table[i].irq));
	154	}
d4e26d10 JCD	155
	156	/* Initialize all I2C */
	157	for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
	158	static const struct {
	159	hwaddr addr;
	160	unsigned int irq;
	161	} i2c_table[FSL_IMX31_NUM_I2CS] = {
	162	{ FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
	163	{ FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
	164	{ FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
	165	};
	166
	167	/* Initialize the I2C */
	168	object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
	169	if (err) {
	170	error_propagate(errp, err);
	171	return;
	172	}
	173	/* Map I2C memory */
	174	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
	175	/* Connect I2C IRQ to PIC */
	176	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
	177	qdev_get_gpio_in(DEVICE(&s->avic),
	178	i2c_table[i].irq));
	179	}
dde0c4ca JCD	180
	181	/* Initialize all GPIOs */
	182	for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
	183	static const struct {
	184	hwaddr addr;
	185	unsigned int irq;
	186	} gpio_table[FSL_IMX31_NUM_GPIOS] = {
	187	{ FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
	188	{ FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
	189	{ FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
	190	};
	191
	192	object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
	193	&error_abort);
	194	object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
	195	if (err) {
	196	error_propagate(errp, err);
	197	return;
	198	}
	199	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
	200	/* Connect GPIO IRQ to PIC */
	201	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
	202	qdev_get_gpio_in(DEVICE(&s->avic),
	203	gpio_table[i].irq));
	204	}
558df83d JCD	205
558df83d JCD	206	/* On a real system, the first 16k is a `secure boot rom' */
eda40cc1	207	memory_region_init_rom(&s->secure_rom, NULL, "imx31.secure_rom",
a7aeb5f7	208	FSL_IMX31_SECURE_ROM_SIZE, &err);
558df83d JCD	209	if (err) {
	210	error_propagate(errp, err);
	211	return;
	212	}
	213	memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
	214	&s->secure_rom);
	215
	216	/* There is also a 16k ROM */
eda40cc1	217	memory_region_init_rom(&s->rom, NULL, "imx31.rom",
a7aeb5f7	218	FSL_IMX31_ROM_SIZE, &err);
558df83d JCD	219	if (err) {
	220	error_propagate(errp, err);
	221	return;
	222	}
	223	memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
	224	&s->rom);
	225
	226	/* initialize internal RAM (16 KB) */
98a99ce0	227	memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
558df83d JCD	228	&err);
	229	if (err) {
	230	error_propagate(errp, err);
	231	return;
	232	}
	233	memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
	234	&s->iram);
558df83d JCD	235
	236	/* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
	237	memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",
	238	&s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
	239	memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
	240	&s->iram_alias);
	241	}
	242
	243	static void fsl_imx31_class_init(ObjectClass oc, void data)
	244	{
	245	DeviceClass *dc = DEVICE_CLASS(oc);
	246
	247	dc->realize = fsl_imx31_realize;
eccfa35e	248	dc->desc = "i.MX31 SOC";
e4e05b7b TH	249	/*
	250	* Reason: uses serial_hds in realize and the kzm board does not
	251	* support multiple CPUs
	252	*/
	253	dc->user_creatable = false;
558df83d JCD	254	}
	255
	256	static const TypeInfo fsl_imx31_type_info = {
	257	.name = TYPE_FSL_IMX31,
	258	.parent = TYPE_DEVICE,
	259	.instance_size = sizeof(FslIMX31State),
	260	.instance_init = fsl_imx31_init,
	261	.class_init = fsl_imx31_class_init,
	262	};
	263
	264	static void fsl_imx31_register_types(void)
	265	{
	266	type_register_static(&fsl_imx31_type_info);
	267	}
	268
	269	type_init(fsl_imx31_register_types)