[qemu.git] / hw / acpi.c

/*
 * ACPI implementation
 * 
 * Copyright (c) 2006 Fabrice Bellard
 * 
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "vl.h"

//#define DEBUG

/* i82731AB (PIIX4) compatible power management function */
#define PM_FREQ 3579545

#define ACPI_DBG_IO_ADDR  0xb044

typedef struct PIIX4PMState {
    PCIDevice dev;
    uint16_t pmsts;
    uint16_t pmen;
    uint16_t pmcntrl;
    uint8_t apmc;
    uint8_t apms;
    QEMUTimer *tmr_timer;
    int64_t tmr_overflow_time;
} PIIX4PMState;

#define RTC_EN (1 << 10)
#define PWRBTN_EN (1 << 8)
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)

#define SCI_EN (1 << 0)

#define SUS_EN (1 << 13)

static uint32_t get_pmtmr(PIIX4PMState *s)
{
    uint32_t d;
    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
    return d & 0xffffff;
}

static int get_pmsts(PIIX4PMState *s)
{
    int64_t d;
    int pmsts;
    pmsts = s->pmsts;
    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
    if (d >= s->tmr_overflow_time)
        s->pmsts |= TMROF_EN;
    return pmsts;
}

static void pm_update_sci(PIIX4PMState *s)
{
    int sci_level, pmsts;
    int64_t expire_time;
    
    pmsts = get_pmsts(s);
    sci_level = (((pmsts & s->pmen) & 
                  (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
    pci_set_irq(&s->dev, 0, sci_level);
    /* schedule a timer interruption if needed */
    if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
        expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
        qemu_mod_timer(s->tmr_timer, expire_time);
    } else {
        qemu_del_timer(s->tmr_timer);
    }
}

static void pm_tmr_timer(void *opaque)
{
    PIIX4PMState *s = opaque;
    pm_update_sci(s);
}

static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4PMState *s = opaque;
    addr &= 0x3f;
    switch(addr) {
    case 0x00:
        {
            int64_t d;
            int pmsts;
            pmsts = get_pmsts(s);
            if (pmsts & val & TMROF_EN) {
                /* if TMRSTS is reset, then compute the new overflow time */
                d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
            }
            s->pmsts &= ~val;
            pm_update_sci(s);
        }
        break;
    case 0x02:
        s->pmen = val;
        pm_update_sci(s);
        break;
    case 0x04:
        {
            int sus_typ;
            s->pmcntrl = val & ~(SUS_EN);
            if (val & SUS_EN) {
                /* change suspend type */
                sus_typ = (val >> 10) & 3;
                switch(sus_typ) {
                case 0: /* soft power off */
                    qemu_system_shutdown_request();
                    break;
                default:
                    break;
                }
            }
        }
        break;
    default:
        break;
    }
#ifdef DEBUG
    printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
#endif
}

static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;

    addr &= 0x3f;
    switch(addr) {
    case 0x00:
        val = get_pmsts(s);
        break;
    case 0x02:
        val = s->pmen;
        break;
    case 0x04:
        val = s->pmcntrl;
        break;
    default:
        val = 0;
        break;
    }
#ifdef DEBUG
    printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
#endif
    return val;
}

static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
{
    //    PIIX4PMState *s = opaque;
    addr &= 0x3f;
#ifdef DEBUG
    printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
#endif
}

static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;

    addr &= 0x3f;
    switch(addr) {
    case 0x08:
        val = get_pmtmr(s);
        break;
    default:
        val = 0;
        break;
    }
#ifdef DEBUG
    printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
#endif
    return val;
}

static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4PMState *s = opaque;
    addr &= 1;
#ifdef DEBUG
    printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
#endif
    if (addr == 0) {
        s->apmc = val;
        if (s->dev.config[0x5b] & (1 << 1)) {
            cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
        }
    } else {
        s->apms = val;
    }
}

static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;
    
    addr &= 1;
    if (addr == 0) {
        val = s->apmc;
    } else {
        val = s->apms;
    }
#ifdef DEBUG
    printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
#endif
    return val;
}

static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
{
#if defined(DEBUG)
    printf("ACPI: DBG: 0x%08x\n", val);
#endif
}

static void pm_io_space_update(PIIX4PMState *s)
{
    uint32_t pm_io_base;

    if (s->dev.config[0x80] & 1) {
        pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
        pm_io_base &= 0xfffe;

        /* XXX: need to improve memory and ioport allocation */
#if defined(DEBUG)
        printf("PM: mapping to 0x%x\n", pm_io_base);
#endif
        register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
        register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
        register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
        register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
    }
}

static void pm_write_config(PCIDevice *d, 
                            uint32_t address, uint32_t val, int len)
{
    pci_default_write_config(d, address, val, len);
    if (address == 0x80)
        pm_io_space_update((PIIX4PMState *)d);
}

static void pm_save(QEMUFile* f,void *opaque)
{
    PIIX4PMState *s = opaque;

    pci_device_save(&s->dev, f);

    qemu_put_be16s(f, &s->pmsts);
    qemu_put_be16s(f, &s->pmen);
    qemu_put_be16s(f, &s->pmcntrl);
    qemu_put_8s(f, &s->apmc);
    qemu_put_8s(f, &s->apms);
    qemu_put_timer(f, s->tmr_timer);
    qemu_put_be64s(f, &s->tmr_overflow_time);
}

static int pm_load(QEMUFile* f,void* opaque,int version_id)
{
    PIIX4PMState *s = opaque;
    int ret;

    if (version_id > 1)
        return -EINVAL;

    ret = pci_device_load(&s->dev, f);
    if (ret < 0)
        return ret;

    qemu_get_be16s(f, &s->pmsts);
    qemu_get_be16s(f, &s->pmen);
    qemu_get_be16s(f, &s->pmcntrl);
    qemu_get_8s(f, &s->apmc);
    qemu_get_8s(f, &s->apms);
    qemu_get_timer(f, s->tmr_timer);
    qemu_get_be64s(f, &s->tmr_overflow_time);

    pm_io_space_update(s);

    return 0;
}

void piix4_pm_init(PCIBus *bus, int devfn)
{
    PIIX4PMState *s;
    uint8_t *pci_conf;

    s = (PIIX4PMState *)pci_register_device(bus,
                                         "PM", sizeof(PIIX4PMState),
                                         devfn, NULL, pm_write_config);
    pci_conf = s->dev.config;
    pci_conf[0x00] = 0x86;
    pci_conf[0x01] = 0x80;
    pci_conf[0x02] = 0x13;
    pci_conf[0x03] = 0x71;
    pci_conf[0x08] = 0x00; // revision number
    pci_conf[0x09] = 0x00;
    pci_conf[0x0a] = 0x80; // other bridge device
    pci_conf[0x0b] = 0x06; // bridge device
    pci_conf[0x0e] = 0x00; // header_type
    pci_conf[0x3d] = 0x01; // interrupt pin 1
    
    pci_conf[0x40] = 0x01; /* PM io base read only bit */
    
    register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
    register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);

    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);

    /* XXX: which specification is used ? The i82731AB has different
       mappings */
    pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
    pci_conf[0x63] = 0x60;
    pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
	(serial_hds[1] != NULL ? 0x90 : 0);

    s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);

    register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
}
Commit	Line	Data
6515b203 FB	1	/*
	2	* ACPI implementation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License version 2 as published by the Free Software Foundation.
	9	*
	10	* This library is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* Lesser General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU Lesser General Public
	16	* License along with this library; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19	#include "vl.h"
	20
	21	//#define DEBUG
	22
	23	/* i82731AB (PIIX4) compatible power management function */
	24	#define PM_FREQ 3579545
	25
6515b203 FB	26	#define ACPI_DBG_IO_ADDR 0xb044
	27
	28	typedef struct PIIX4PMState {
	29	PCIDevice dev;
	30	uint16_t pmsts;
	31	uint16_t pmen;
	32	uint16_t pmcntrl;
ab1e34ad FB	33	uint8_t apmc;
ab1e34ad FB	34	uint8_t apms;
6515b203 FB	35	QEMUTimer *tmr_timer;
	36	int64_t tmr_overflow_time;
	37	} PIIX4PMState;
	38
	39	#define RTC_EN (1 << 10)
	40	#define PWRBTN_EN (1 << 8)
	41	#define GBL_EN (1 << 5)
	42	#define TMROF_EN (1 << 0)
	43
	44	#define SCI_EN (1 << 0)
	45
	46	#define SUS_EN (1 << 13)
	47
6515b203 FB	48	static uint32_t get_pmtmr(PIIX4PMState *s)
	49	{
	50	uint32_t d;
	51	d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
	52	return d & 0xffffff;
	53	}
	54
	55	static int get_pmsts(PIIX4PMState *s)
	56	{
	57	int64_t d;
	58	int pmsts;
	59	pmsts = s->pmsts;
	60	d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
	61	if (d >= s->tmr_overflow_time)
	62	s->pmsts \|= TMROF_EN;
	63	return pmsts;
	64	}
	65
	66	static void pm_update_sci(PIIX4PMState *s)
	67	{
	68	int sci_level, pmsts;
	69	int64_t expire_time;
	70
	71	pmsts = get_pmsts(s);
	72	sci_level = (((pmsts & s->pmen) &
	73	(RTC_EN \| PWRBTN_EN \| GBL_EN \| TMROF_EN)) != 0);
	74	pci_set_irq(&s->dev, 0, sci_level);
	75	/* schedule a timer interruption if needed */
	76	if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
	77	expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
	78	qemu_mod_timer(s->tmr_timer, expire_time);
	79	} else {
	80	qemu_del_timer(s->tmr_timer);
	81	}
	82	}
	83
	84	static void pm_tmr_timer(void *opaque)
	85	{
	86	PIIX4PMState *s = opaque;
	87	pm_update_sci(s);
	88	}
	89
	90	static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
	91	{
	92	PIIX4PMState *s = opaque;
	93	addr &= 0x3f;
	94	switch(addr) {
	95	case 0x00:
	96	{
	97	int64_t d;
	98	int pmsts;
	99	pmsts = get_pmsts(s);
	100	if (pmsts & val & TMROF_EN) {
	101	/* if TMRSTS is reset, then compute the new overflow time */
	102	d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
	103	s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
	104	}
	105	s->pmsts &= ~val;
	106	pm_update_sci(s);
	107	}
	108	break;
	109	case 0x02:
	110	s->pmen = val;
	111	pm_update_sci(s);
112	break;
113	case 0x04:
114	{
115	int sus_typ;
116	s->pmcntrl = val & ~(SUS_EN);
117	if (val & SUS_EN) {
118	/* change suspend type */
119	sus_typ = (val >> 10) & 3;
120	switch(sus_typ) {
121	case 0: /* soft power off */
122	qemu_system_shutdown_request();
123	break;
124	default:
125	break;
126	}
127	}
128	}
129	break;
130	default:
131	break;
132	}
133	#ifdef DEBUG
134	printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
135	#endif
136	}
137
138	static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
139	{
140	PIIX4PMState *s = opaque;
141	uint32_t val;
142
143	addr &= 0x3f;
144	switch(addr) {
145	case 0x00:
146	val = get_pmsts(s);
147	break;
148	case 0x02:
149	val = s->pmen;
150	break;
151	case 0x04:
152	val = s->pmcntrl;
153	break;
154	default:
155	val = 0;
156	break;
157	}
158	#ifdef DEBUG
159	printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
160	#endif
161	return val;
162	}
163
164	static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
165	{
166	// PIIX4PMState *s = opaque;
167	addr &= 0x3f;
168	#ifdef DEBUG
169	printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
170	#endif
171	}
172
173	static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
174	{
175	PIIX4PMState *s = opaque;
176	uint32_t val;
177
178	addr &= 0x3f;
179	switch(addr) {
180	case 0x08:
181	val = get_pmtmr(s);
182	break;
183	default:
184	val = 0;
185	break;
186	}
187	#ifdef DEBUG
188	printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
189	#endif
190	return val;
191	}
192
ab1e34ad	193	static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
6515b203 FB	194	{
6515b203 FB	195	PIIX4PMState *s = opaque;
ab1e34ad	196	addr &= 1;
6515b203	197	#ifdef DEBUG
ab1e34ad	198	printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
6515b203	199	#endif
ab1e34ad FB	200	if (addr == 0) {
ab1e34ad FB	201	s->apmc = val;
47d02f6d FB	202	if (s->dev.config[0x5b] & (1 << 1)) {
47d02f6d FB	203	cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
ab1e34ad	204	}
ab1e34ad FB	205	} else {
ab1e34ad FB	206	s->apms = val;
6515b203 FB	207	}
	208	}
	209
ab1e34ad FB	210	static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
	211	{
	212	PIIX4PMState *s = opaque;
	213	uint32_t val;
	214
	215	addr &= 1;
	216	if (addr == 0) {
	217	val = s->apmc;
	218	} else {
	219	val = s->apms;
	220	}
	221	#ifdef DEBUG
	222	printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
	223	#endif
	224	return val;
	225	}
	226
6515b203 FB	227	static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
	228	{
	229	#if defined(DEBUG)
	230	printf("ACPI: DBG: 0x%08x\n", val);
	231	#endif
	232	}
	233
ab1e34ad FB	234	static void pm_io_space_update(PIIX4PMState *s)
	235	{
	236	uint32_t pm_io_base;
	237
	238	if (s->dev.config[0x80] & 1) {
	239	pm_io_base = le32_to_cpu((uint32_t )(s->dev.config + 0x40));
	240	pm_io_base &= 0xfffe;
	241
	242	/* XXX: need to improve memory and ioport allocation */
	243	#if defined(DEBUG)
	244	printf("PM: mapping to 0x%x\n", pm_io_base);
	245	#endif
	246	register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
	247	register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
	248	register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
	249	register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
	250	}
	251	}
	252
	253	static void pm_write_config(PCIDevice *d,
	254	uint32_t address, uint32_t val, int len)
	255	{
	256	pci_default_write_config(d, address, val, len);
	257	if (address == 0x80)
	258	pm_io_space_update((PIIX4PMState *)d);
	259	}
	260
	261	static void pm_save(QEMUFile* f,void *opaque)
	262	{
	263	PIIX4PMState *s = opaque;
	264
	265	pci_device_save(&s->dev, f);
	266
	267	qemu_put_be16s(f, &s->pmsts);
	268	qemu_put_be16s(f, &s->pmen);
	269	qemu_put_be16s(f, &s->pmcntrl);
	270	qemu_put_8s(f, &s->apmc);
	271	qemu_put_8s(f, &s->apms);
	272	qemu_put_timer(f, s->tmr_timer);
	273	qemu_put_be64s(f, &s->tmr_overflow_time);
	274	}
	275
	276	static int pm_load(QEMUFile* f,void* opaque,int version_id)
	277	{
	278	PIIX4PMState *s = opaque;
	279	int ret;
	280
	281	if (version_id > 1)
	282	return -EINVAL;
	283
	284	ret = pci_device_load(&s->dev, f);
	285	if (ret < 0)
	286	return ret;
	287
	288	qemu_get_be16s(f, &s->pmsts);
	289	qemu_get_be16s(f, &s->pmen);
	290	qemu_get_be16s(f, &s->pmcntrl);
	291	qemu_get_8s(f, &s->apmc);
	292	qemu_get_8s(f, &s->apms);
	293	qemu_get_timer(f, s->tmr_timer);
	294	qemu_get_be64s(f, &s->tmr_overflow_time);
	295
	296	pm_io_space_update(s);
	297
298	return 0;
299	}
300
502a5395	301	void piix4_pm_init(PCIBus *bus, int devfn)
6515b203 FB	302	{
	303	PIIX4PMState *s;
	304	uint8_t *pci_conf;
6515b203 FB	305
	306	s = (PIIX4PMState *)pci_register_device(bus,
	307	"PM", sizeof(PIIX4PMState),
ab1e34ad	308	devfn, NULL, pm_write_config);
6515b203 FB	309	pci_conf = s->dev.config;
	310	pci_conf[0x00] = 0x86;
	311	pci_conf[0x01] = 0x80;
	312	pci_conf[0x02] = 0x13;
7ef4da1c	313	pci_conf[0x03] = 0x71;
6515b203 FB	314	pci_conf[0x08] = 0x00; // revision number
	315	pci_conf[0x09] = 0x00;
	316	pci_conf[0x0a] = 0x80; // other bridge device
	317	pci_conf[0x0b] = 0x06; // bridge device
	318	pci_conf[0x0e] = 0x00; // header_type
	319	pci_conf[0x3d] = 0x01; // interrupt pin 1
6515b203	320
ab1e34ad	321	pci_conf[0x40] = 0x01; /* PM io base read only bit */
6515b203	322
ab1e34ad FB	323	register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
	324	register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
	325
6515b203 FB	326	register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
6515b203 FB	327
1ce549ab FB	328	/* XXX: which specification is used ? The i82731AB has different
	329	mappings */
	330	pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) \| 0x10;
	331	pci_conf[0x63] = 0x60;
	332	pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) \|
	333	(serial_hds[1] != NULL ? 0x90 : 0);
	334
6515b203	335	s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
6515b203	336
ab1e34ad	337	register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
6515b203	338	}