[qemu.git] / hw / cris / axis_dev88.c

/*
 * QEMU model for the AXIS devboard 88.
 *
 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw/sysbus.h"
#include "net/net.h"
#include "hw/block/flash.h"
#include "hw/boards.h"
#include "hw/cris/etraxfs.h"
#include "hw/loader.h"
#include "elf.h"
#include "boot.h"
#include "sysemu/blockdev.h"
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"

#define D(x)
#define DNAND(x)

struct nand_state_t
{
    DeviceState *nand;
    MemoryRegion iomem;
    unsigned int rdy:1;
    unsigned int ale:1;
    unsigned int cle:1;
    unsigned int ce:1;
};

static struct nand_state_t nand_state;
static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
{
    struct nand_state_t *s = opaque;
    uint32_t r;
    int rdy;

    r = nand_getio(s->nand);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;

    DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
    return r;
}

static void
nand_write(void *opaque, hwaddr addr, uint64_t value,
           unsigned size)
{
    struct nand_state_t *s = opaque;
    int rdy;

    DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
    nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
    nand_setio(s->nand, value);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;
}

static const MemoryRegionOps nand_ops = {
    .read = nand_read,
    .write = nand_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

struct tempsensor_t
{
    unsigned int shiftreg;
    unsigned int count;
    enum {
        ST_OUT, ST_IN, ST_Z
    } state;

    uint16_t regs[3];
};

static void tempsensor_clkedge(struct tempsensor_t *s,
                               unsigned int clk, unsigned int data_in)
{
    D(printf("%s clk=%d state=%d sr=%x\n", __func__,
             clk, s->state, s->shiftreg));
    if (s->count == 0) {
        s->count = 16;
        s->state = ST_OUT;
    }
    switch (s->state) {
        case ST_OUT:
            /* Output reg is clocked at negedge.  */
            if (!clk) {
                s->count--;
                s->shiftreg <<= 1;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_IN;
                    s->count = 16;
                }
            }
            break;
        case ST_Z:
            if (clk) {
                s->count--;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_OUT;
                    s->count = 16;
                }
            }
            break;
        case ST_IN:
            /* Indata is sampled at posedge.  */
            if (clk) {
                s->count--;
                s->shiftreg <<= 1;
                s->shiftreg |= data_in & 1;
                if (s->count == 0) {
                    D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
                    s->regs[0] = s->shiftreg;
                    s->state = ST_OUT;
                    s->count = 16;

                    if ((s->regs[0] & 0xff) == 0) {
                        /* 25 degrees celcius.  */
                        s->shiftreg = 0x0b9f;
                    } else if ((s->regs[0] & 0xff) == 0xff) {
                        /* Sensor ID, 0x8100 LM70.  */
                        s->shiftreg = 0x8100;
                    } else
                        printf("Invalid tempsens state %x\n", s->regs[0]);
                }
            }
            break;
    }
}


#define RW_PA_DOUT    0x00
#define R_PA_DIN      0x01
#define RW_PA_OE      0x02
#define RW_PD_DOUT    0x10
#define R_PD_DIN      0x11
#define RW_PD_OE      0x12

static struct gpio_state_t
{
    MemoryRegion iomem;
    struct nand_state_t *nand;
    struct tempsensor_t tempsensor;
    uint32_t regs[0x5c / 4];
} gpio_state;

static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
{
    struct gpio_state_t *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr)
    {
        case R_PA_DIN:
            r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];

            /* Encode pins from the nand.  */
            r |= s->nand->rdy << 7;
            break;
        case R_PD_DIN:
            r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];

            /* Encode temp sensor pins.  */
            r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
            break;

        default:
            r = s->regs[addr];
            break;
    }
    return r;
    D(printf("%s %x=%x\n", __func__, addr, r));
}

static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
                       unsigned size)
{
    struct gpio_state_t *s = opaque;
    D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));

    addr >>= 2;
    switch (addr)
    {
        case RW_PA_DOUT:
            /* Decode nand pins.  */
            s->nand->ale = !!(value & (1 << 6));
            s->nand->cle = !!(value & (1 << 5));
            s->nand->ce  = !!(value & (1 << 4));

            s->regs[addr] = value;
            break;

        case RW_PD_DOUT:
            /* Temp sensor clk.  */
            if ((s->regs[addr] ^ value) & 2)
                tempsensor_clkedge(&s->tempsensor, !!(value & 2),
                                   !!(value & 16));
            s->regs[addr] = value;
            break;

        default:
            s->regs[addr] = value;
            break;
    }
}

static const MemoryRegionOps gpio_ops = {
    .read = gpio_read,
    .write = gpio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

#define INTMEM_SIZE (128 * 1024)

static struct cris_load_info li;

static
void axisdev88_init(QEMUMachineInitArgs *args)
{
    ram_addr_t ram_size = args->ram_size;
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    const char *kernel_cmdline = args->kernel_cmdline;
    CRISCPU *cpu;
    CPUCRISState *env;
    DeviceState *dev;
    SysBusDevice *s;
    DriveInfo *nand;
    qemu_irq irq[30], nmi[2];
    void *etraxfs_dmac;
    struct etraxfs_dma_client *dma_eth;
    int i;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "crisv32";
    }
    cpu = cpu_cris_init(cpu_model);
    env = &cpu->env;

    /* allocate RAM */
    memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size);
    vmstate_register_ram_global(phys_ram);
    memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);

    /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the 
       internal memory.  */
    memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE);
    vmstate_register_ram_global(phys_intmem);
    memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);

      /* Attach a NAND flash to CS1.  */
    nand = drive_get(IF_MTD, 0, 0);
    nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
                                NAND_MFR_STMICRO, 0x39);
    memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
                          "nand", 0x05000000);
    memory_region_add_subregion(address_space_mem, 0x10000000,
                                &nand_state.iomem);

    gpio_state.nand = &nand_state;
    memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
                          "gpio", 0x5c);
    memory_region_add_subregion(address_space_mem, 0x3001a000,
                                &gpio_state.iomem);


    dev = qdev_create(NULL, "etraxfs,pic");
    /* FIXME: Is there a proper way to signal vectors to the CPU core?  */
    qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0x3001c000);
    sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
    sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
    for (i = 0; i < 30; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }
    nmi[0] = qdev_get_gpio_in(dev, 30);
    nmi[1] = qdev_get_gpio_in(dev, 31);

    etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
    for (i = 0; i < 10; i++) {
        /* On ETRAX, odd numbered channels are inputs.  */
        etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
    }

    /* Add the two ethernet blocks.  */
    dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels.  */
    etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
    if (nb_nics > 1) {
        etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
    }

    /* The DMA Connector block is missing, hardwire things for now.  */
    etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
    etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
    if (nb_nics > 1) {
        etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
        etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
    }

    /* 2 timers.  */
    sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
    sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);

    for (i = 0; i < 4; i++) {
        sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
                             irq[0x14 + i]);
    }

    if (kernel_filename) {
        li.image_filename = kernel_filename;
        li.cmdline = kernel_cmdline;
        cris_load_image(cpu, &li);
    } else if (!qtest_enabled()) {
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }
}

static QEMUMachine axisdev88_machine = {
    .name = "axis-dev88",
    .desc = "AXIS devboard 88",
    .init = axisdev88_init,
    .is_default = 1,
};

static void axisdev88_machine_init(void)
{
    qemu_register_machine(&axisdev88_machine);
}

machine_init(axisdev88_machine_init);
Commit	Line	Data
10c144e2 EI	1	/*
	2	* QEMU model for the AXIS devboard 88.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
4b816985	24
83c9f4ca	25	#include "hw/sysbus.h"
1422e32d	26	#include "net/net.h"
0d09e41a	27	#include "hw/block/flash.h"
83c9f4ca	28	#include "hw/boards.h"
0d09e41a	29	#include "hw/cris/etraxfs.h"
83c9f4ca	30	#include "hw/loader.h"
ca20cf32	31	#include "elf.h"
47b43a1f	32	#include "boot.h"
9c17d615	33	#include "sysemu/blockdev.h"
022c62cb	34	#include "exec/address-spaces.h"
5efe843a	35	#include "sysemu/qtest.h"
10c144e2 EI	36
	37	#define D(x)
	38	#define DNAND(x)
	39
	40	struct nand_state_t
	41	{
d4220389	42	DeviceState *nand;
838335ec	43	MemoryRegion iomem;
10c144e2 EI	44	unsigned int rdy:1;
	45	unsigned int ale:1;
	46	unsigned int cle:1;
	47	unsigned int ce:1;
	48	};
	49
	50	static struct nand_state_t nand_state;
a8170e5e	51	static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
10c144e2 EI	52	{
	53	struct nand_state_t *s = opaque;
	54	uint32_t r;
	55	int rdy;
	56
	57	r = nand_getio(s->nand);
	58	nand_getpins(s->nand, &rdy);
	59	s->rdy = rdy;
	60
	61	DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
	62	return r;
	63	}
	64
	65	static void
a8170e5e	66	nand_write(void *opaque, hwaddr addr, uint64_t value,
838335ec	67	unsigned size)
10c144e2 EI	68	{
	69	struct nand_state_t *s = opaque;
	70	int rdy;
	71
838335ec	72	DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
10c144e2 EI	73	nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
	74	nand_setio(s->nand, value);
	75	nand_getpins(s->nand, &rdy);
	76	s->rdy = rdy;
	77	}
	78
838335ec AK	79	static const MemoryRegionOps nand_ops = {
	80	.read = nand_read,
	81	.write = nand_write,
	82	.endianness = DEVICE_NATIVE_ENDIAN,
10c144e2 EI	83	};
10c144e2 EI	84
4a1e6bea EI	85	struct tempsensor_t
	86	{
	87	unsigned int shiftreg;
	88	unsigned int count;
	89	enum {
	90	ST_OUT, ST_IN, ST_Z
	91	} state;
	92
	93	uint16_t regs[3];
	94	};
	95
	96	static void tempsensor_clkedge(struct tempsensor_t *s,
	97	unsigned int clk, unsigned int data_in)
	98	{
	99	D(printf("%s clk=%d state=%d sr=%x\n", __func__,
	100	clk, s->state, s->shiftreg));
	101	if (s->count == 0) {
	102	s->count = 16;
	103	s->state = ST_OUT;
	104	}
	105	switch (s->state) {
	106	case ST_OUT:
	107	/* Output reg is clocked at negedge. */
	108	if (!clk) {
	109	s->count--;
	110	s->shiftreg <<= 1;
	111	if (s->count == 0) {
	112	s->shiftreg = 0;
	113	s->state = ST_IN;
	114	s->count = 16;
	115	}
	116	}
	117	break;
	118	case ST_Z:
	119	if (clk) {
	120	s->count--;
	121	if (s->count == 0) {
	122	s->shiftreg = 0;
	123	s->state = ST_OUT;
	124	s->count = 16;
	125	}
	126	}
	127	break;
	128	case ST_IN:
	129	/* Indata is sampled at posedge. */
	130	if (clk) {
	131	s->count--;
	132	s->shiftreg <<= 1;
	133	s->shiftreg \|= data_in & 1;
	134	if (s->count == 0) {
	135	D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
	136	s->regs[0] = s->shiftreg;
	137	s->state = ST_OUT;
	138	s->count = 16;
	139
	140	if ((s->regs[0] & 0xff) == 0) {
	141	/* 25 degrees celcius. */
	142	s->shiftreg = 0x0b9f;
	143	} else if ((s->regs[0] & 0xff) == 0xff) {
	144	/* Sensor ID, 0x8100 LM70. */
	145	s->shiftreg = 0x8100;
	146	} else
	147	printf("Invalid tempsens state %x\n", s->regs[0]);
	148	}
149	}
150	break;
151	}
152	}
153
154
155	#define RW_PA_DOUT 0x00
156	#define R_PA_DIN 0x01
157	#define RW_PA_OE 0x02
158	#define RW_PD_DOUT 0x10
159	#define R_PD_DIN 0x11
160	#define RW_PD_OE 0x12
161
162	static struct gpio_state_t
10c144e2	163	{
838335ec	164	MemoryRegion iomem;
10c144e2	165	struct nand_state_t *nand;
4a1e6bea	166	struct tempsensor_t tempsensor;
10c144e2 EI	167	uint32_t regs[0x5c / 4];
	168	} gpio_state;
	169
a8170e5e	170	static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
10c144e2 EI	171	{
	172	struct gpio_state_t *s = opaque;
	173	uint32_t r = 0;
	174
	175	addr >>= 2;
	176	switch (addr)
	177	{
	178	case R_PA_DIN:
	179	r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
	180
	181	/* Encode pins from the nand. */
	182	r \|= s->nand->rdy << 7;
	183	break;
4a1e6bea EI	184	case R_PD_DIN:
	185	r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
	186
	187	/* Encode temp sensor pins. */
	188	r \|= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
	189	break;
	190
10c144e2 EI	191	default:
	192	r = s->regs[addr];
	193	break;
	194	}
	195	return r;
	196	D(printf("%s %x=%x\n", __func__, addr, r));
	197	}
	198
a8170e5e	199	static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
838335ec	200	unsigned size)
10c144e2 EI	201	{
10c144e2 EI	202	struct gpio_state_t *s = opaque;
838335ec	203	D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
10c144e2 EI	204
	205	addr >>= 2;
	206	switch (addr)
	207	{
	208	case RW_PA_DOUT:
	209	/* Decode nand pins. */
	210	s->nand->ale = !!(value & (1 << 6));
	211	s->nand->cle = !!(value & (1 << 5));
	212	s->nand->ce = !!(value & (1 << 4));
	213
	214	s->regs[addr] = value;
	215	break;
4a1e6bea EI	216
	217	case RW_PD_DOUT:
	218	/* Temp sensor clk. */
	219	if ((s->regs[addr] ^ value) & 2)
	220	tempsensor_clkedge(&s->tempsensor, !!(value & 2),
	221	!!(value & 16));
	222	s->regs[addr] = value;
	223	break;
	224
10c144e2 EI	225	default:
	226	s->regs[addr] = value;
	227	break;
	228	}
	229	}
	230
838335ec AK	231	static const MemoryRegionOps gpio_ops = {
	232	.read = gpio_read,
	233	.write = gpio_write,
	234	.endianness = DEVICE_NATIVE_ENDIAN,
	235	.valid = {
	236	.min_access_size = 4,
	237	.max_access_size = 4,
	238	},
10c144e2 EI	239	};
	240
	241	#define INTMEM_SIZE (128 * 1024)
	242
77d4f95e	243	static struct cris_load_info li;
409dbce5	244
10c144e2	245	static
5f072e1f	246	void axisdev88_init(QEMUMachineInitArgs *args)
10c144e2	247	{
5f072e1f EH	248	ram_addr_t ram_size = args->ram_size;
	249	const char *cpu_model = args->cpu_model;
	250	const char *kernel_filename = args->kernel_filename;
	251	const char *kernel_cmdline = args->kernel_cmdline;
ddeb9ae5	252	CRISCPU *cpu;
fc9bb176	253	CPUCRISState *env;
fd6dc90b EI	254	DeviceState *dev;
fd6dc90b EI	255	SysBusDevice *s;
522f253c	256	DriveInfo *nand;
4a6da670	257	qemu_irq irq[30], nmi[2];
10c144e2	258	void *etraxfs_dmac;
1da005b3	259	struct etraxfs_dma_client *dma_eth;
10c144e2	260	int i;
b0e3d5ac AK	261	MemoryRegion *address_space_mem = get_system_memory();
	262	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
	263	MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
10c144e2 EI	264
	265	/* init CPUs */
	266	if (cpu_model == NULL) {
	267	cpu_model = "crisv32";
	268	}
ddeb9ae5 AF	269	cpu = cpu_cris_init(cpu_model);
ddeb9ae5 AF	270	env = &cpu->env;
10c144e2 EI	271
10c144e2 EI	272	/* allocate RAM */
2c9b15ca	273	memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size);
c5705a77	274	vmstate_register_ram_global(phys_ram);
b0e3d5ac	275	memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
10c144e2 EI	276
	277	/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
	278	internal memory. */
2c9b15ca	279	memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE);
c5705a77	280	vmstate_register_ram_global(phys_intmem);
b0e3d5ac	281	memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
10c144e2 EI	282
10c144e2 EI	283	/* Attach a NAND flash to CS1. */
522f253c PM	284	nand = drive_get(IF_MTD, 0, 0);
	285	nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
	286	NAND_MFR_STMICRO, 0x39);
2c9b15ca	287	memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
838335ec AK	288	"nand", 0x05000000);
	289	memory_region_add_subregion(address_space_mem, 0x10000000,
	290	&nand_state.iomem);
10c144e2 EI	291
10c144e2 EI	292	gpio_state.nand = &nand_state;
2c9b15ca	293	memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
838335ec AK	294	"gpio", 0x5c);
	295	memory_region_add_subregion(address_space_mem, 0x3001a000,
	296	&gpio_state.iomem);
10c144e2 EI	297
10c144e2 EI	298
fd6dc90b EI	299	dev = qdev_create(NULL, "etraxfs,pic");
fd6dc90b EI	300	/* FIXME: Is there a proper way to signal vectors to the CPU core? */
ee6847d1	301	qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
e23a1b33	302	qdev_init_nofail(dev);
1356b98d	303	s = SYS_BUS_DEVICE(dev);
fd6dc90b	304	sysbus_mmio_map(s, 0, 0x3001c000);
4a6da670 EI	305	sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
4a6da670 EI	306	sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
fd6dc90b	307	for (i = 0; i < 30; i++) {
067a3ddc	308	irq[i] = qdev_get_gpio_in(dev, i);
fd6dc90b	309	}
067a3ddc PB	310	nmi[0] = qdev_get_gpio_in(dev, 30);
067a3ddc PB	311	nmi[1] = qdev_get_gpio_in(dev, 31);
73cfd29f	312
ba494313	313	etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
10c144e2 EI	314	for (i = 0; i < 10; i++) {
10c144e2 EI	315	/* On ETRAX, odd numbered channels are inputs. */
73cfd29f	316	etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
10c144e2 EI	317	}
	318
	319	/* Add the two ethernet blocks. */
7267c094	320	dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels. */
1da005b3 EI	321	etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
	322	if (nb_nics > 1) {
	323	etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
	324	}
10c144e2 EI	325
10c144e2 EI	326	/* The DMA Connector block is missing, hardwire things for now. */
1da005b3 EI	327	etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
	328	etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
	329	if (nb_nics > 1) {
	330	etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
	331	etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
10c144e2 EI	332	}
	333
	334	/* 2 timers. */
3b1fd90e EI	335	sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
3b1fd90e EI	336	sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
10c144e2 EI	337
10c144e2 EI	338	for (i = 0; i < 4; i++) {
4b816985	339	sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
3b1fd90e	340	irq[0x14 + i]);
10c144e2 EI	341	}
10c144e2 EI	342
5efe843a AF	343	if (kernel_filename) {
	344	li.image_filename = kernel_filename;
	345	li.cmdline = kernel_cmdline;
	346	cris_load_image(cpu, &li);
	347	} else if (!qtest_enabled()) {
77d4f95e EI	348	fprintf(stderr, "Kernel image must be specified\n");
77d4f95e EI	349	exit(1);
10c144e2	350	}
10c144e2 EI	351	}
10c144e2 EI	352
f80f9ec9	353	static QEMUMachine axisdev88_machine = {
10c144e2 EI	354	.name = "axis-dev88",
	355	.desc = "AXIS devboard 88",
	356	.init = axisdev88_init,
bbea04df	357	.is_default = 1,
10c144e2	358	};
f80f9ec9 AL	359
	360	static void axisdev88_machine_init(void)
	361	{
	362	qemu_register_machine(&axisdev88_machine);
	363	}
	364
	365	machine_init(axisdev88_machine_init);